Unified Coverage Report :: Module :: keymgr_dpe_csr_assert_fpv

Module : keymgr_dpe_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_dpe_csr_assert_0/keymgr_dpe_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_dpe_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_dpe_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_dpe_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	22	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	7405043	11546	0	0
intr_enable_rd_A	7405043	1454	0	0
key_version_rd_A	7405043	1361	0	0
reseed_interval_regwen_rd_A	7405043	697	0	0
salt_0_rd_A	7405043	1178	0	0
salt_1_rd_A	7405043	1320	0	0
salt_2_rd_A	7405043	1287	0	0
salt_3_rd_A	7405043	1335	0	0
salt_4_rd_A	7405043	1430	0	0
salt_5_rd_A	7405043	1271	0	0
salt_6_rd_A	7405043	1289	0	0
salt_7_rd_A	7405043	1169	0	0
sideload_clear_rd_A	7405043	1398	0	0
slot_policy_rd_A	7405043	1960	0	0
sw_binding_0_rd_A	7405043	1317	0	0
sw_binding_1_rd_A	7405043	1402	0	0
sw_binding_2_rd_A	7405043	1296	0	0
sw_binding_3_rd_A	7405043	1308	0	0
sw_binding_4_rd_A	7405043	1326	0	0
sw_binding_5_rd_A	7405043	1222	0	0
sw_binding_6_rd_A	7405043	1318	0	0
sw_binding_7_rd_A	7405043	1342	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7405043	11546	0	0
T19	4699	925	0	0
T20	8558	3	0	0
T21	10697	300	0	0
T29	3206	530	0	0
T30	27384	1	0	0
T32	1233	26	0	0
T37	0	66	0	0
T60	1408	15	0	0
T65	3382	27	0	0
T66	0	393	0	0
T68	1129	0	0	0
T72	2737	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7405043	1454	0	0
T21	10697	7	0	0
T30	27384	0	0	0
T38	1190	14	0	0
T40	916	19	0	0
T59	5015	18	0	0
T65	3382	3	0	0
T66	0	14	0	0
T68	1129	0	0	0
T69	929	0	0	0
T70	0	1	0	0
T85	821	23	0	0
T86	1224	7	0	0
T87	0	5	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7405043	1361	0	0
T21	10697	11	0	0
T30	27384	0	0	0
T35	0	5	0	0
T37	1424	0	0	0
T52	0	47	0	0
T59	5015	6	0	0
T64	0	18	0	0
T65	3382	11	0	0
T66	5727	0	0	0
T67	0	19	0	0
T68	1129	0	0	0
T69	929	0	0	0
T70	1633	7	0	0
T87	983	0	0	0
T88	0	27	0	0
T89	0	24	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7405043	697	0	0
T21	10697	30	0	0
T30	27384	0	0	0
T35	0	9	0	0
T37	1424	0	0	0
T59	5015	21	0	0
T64	0	17	0	0
T65	3382	1	0	0
T66	5727	2	0	0
T67	0	10	0	0
T68	1129	0	0	0
T69	929	0	0	0
T70	1633	0	0	0
T87	983	0	0	0
T88	0	42	0	0
T89	0	23	0	0
T90	0	6	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7405043	1178	0	0
T21	10697	12	0	0
T30	27384	0	0	0
T35	0	3	0	0
T37	1424	0	0	0
T52	0	47	0	0
T59	5015	13	0	0
T64	0	8	0	0
T65	3382	14	0	0
T66	5727	8	0	0
T67	0	15	0	0
T68	1129	0	0	0
T69	929	0	0	0
T70	1633	5	0	0
T87	983	0	0	0
T88	0	11	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7405043	1320	0	0
T30	27384	0	0	0
T35	0	12	0	0
T37	1424	0	0	0
T52	0	57	0	0
T59	5015	19	0	0
T64	0	19	0	0
T65	3382	9	0	0
T66	5727	3	0	0
T67	3311	8	0	0
T68	1129	0	0	0
T69	929	0	0	0
T70	1633	5	0	0
T87	983	0	0	0
T88	0	12	0	0
T89	0	21	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7405043	1287	0	0
T21	10697	9	0	0
T30	27384	0	0	0
T37	1424	0	0	0
T52	0	39	0	0
T59	5015	10	0	0
T64	0	8	0	0
T65	3382	22	0	0
T66	5727	4	0	0
T67	0	14	0	0
T68	1129	0	0	0
T69	929	0	0	0
T70	1633	5	0	0
T87	983	0	0	0
T88	0	12	0	0
T89	0	22	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7405043	1335	0	0
T21	10697	16	0	0
T30	27384	0	0	0
T35	0	11	0	0
T37	1424	0	0	0
T52	0	35	0	0
T59	5015	16	0	0
T64	0	15	0	0
T65	3382	4	0	0
T66	5727	0	0	0
T67	0	10	0	0
T68	1129	0	0	0
T69	929	0	0	0
T70	1633	8	0	0
T87	983	0	0	0
T88	0	10	0	0
T89	0	25	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7405043	1430	0	0
T21	10697	20	0	0
T30	27384	0	0	0
T35	0	5	0	0
T37	1424	0	0	0
T52	0	27	0	0
T59	5015	25	0	0
T64	0	33	0	0
T65	3382	10	0	0
T66	5727	0	0	0
T67	0	10	0	0
T68	1129	0	0	0
T69	929	0	0	0
T70	1633	6	0	0
T87	983	0	0	0
T88	0	28	0	0
T89	0	26	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7405043	1271	0	0
T21	10697	25	0	0
T30	27384	0	0	0
T35	0	12	0	0
T37	1424	0	0	0
T52	0	36	0	0
T59	5015	16	0	0
T64	0	4	0	0
T65	3382	1	0	0
T66	5727	6	0	0
T67	0	13	0	0
T68	1129	0	0	0
T69	929	0	0	0
T70	1633	7	0	0
T87	983	0	0	0
T88	0	9	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7405043	1289	0	0
T21	10697	21	0	0
T30	27384	0	0	0
T35	0	6	0	0
T37	1424	0	0	0
T52	0	21	0	0
T59	5015	9	0	0
T64	0	18	0	0
T65	3382	8	0	0
T66	5727	2	0	0
T67	0	20	0	0
T68	1129	0	0	0
T69	929	0	0	0
T70	1633	2	0	0
T87	983	0	0	0
T88	0	19	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7405043	1169	0	0
T21	10697	16	0	0
T30	27384	0	0	0
T35	0	4	0	0
T37	1424	0	0	0
T52	0	24	0	0
T59	5015	16	0	0
T64	0	16	0	0
T65	3382	4	0	0
T66	5727	4	0	0
T67	0	18	0	0
T68	1129	0	0	0
T69	929	0	0	0
T70	1633	8	0	0
T87	983	0	0	0
T88	0	16	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7405043	1398	0	0
T21	10697	6	0	0
T30	27384	0	0	0
T35	0	7	0	0
T37	1424	0	0	0
T52	0	50	0	0
T59	5015	9	0	0
T64	0	10	0	0
T65	3382	4	0	0
T66	5727	10	0	0
T67	0	15	0	0
T68	1129	0	0	0
T69	929	0	0	0
T70	1633	5	0	0
T87	983	0	0	0
T88	0	9	0	0

slot_policy_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7405043	1960	0	0
T21	10697	15	0	0
T30	27384	0	0	0
T37	1424	0	0	0
T52	0	69	0	0
T59	5015	17	0	0
T64	0	19	0	0
T65	3382	4	0	0
T66	5727	8	0	0
T67	0	11	0	0
T68	1129	0	0	0
T69	929	0	0	0
T70	1633	7	0	0
T87	983	0	0	0
T88	0	44	0	0
T89	0	19	0	0

sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7405043	1317	0	0
T21	10697	20	0	0
T30	27384	0	0	0
T35	0	3	0	0
T37	1424	0	0	0
T52	0	25	0	0
T59	5015	17	0	0
T64	0	18	0	0
T65	3382	3	0	0
T66	5727	3	0	0
T67	0	3	0	0
T68	1129	0	0	0
T69	929	0	0	0
T70	1633	9	0	0
T87	983	0	0	0
T88	0	31	0	0

sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7405043	1402	0	0
T21	10697	12	0	0
T30	27384	0	0	0
T35	0	9	0	0
T37	1424	0	0	0
T52	0	35	0	0
T59	5015	25	0	0
T64	0	16	0	0
T65	3382	11	0	0
T66	5727	0	0	0
T67	0	11	0	0
T68	1129	0	0	0
T69	929	0	0	0
T70	1633	5	0	0
T87	983	0	0	0
T88	0	19	0	0
T89	0	21	0	0

sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7405043	1296	0	0
T21	10697	19	0	0
T30	27384	0	0	0
T35	0	11	0	0
T37	1424	0	0	0
T52	0	42	0	0
T59	5015	11	0	0
T64	0	9	0	0
T65	3382	3	0	0
T66	5727	0	0	0
T67	0	9	0	0
T68	1129	0	0	0
T69	929	0	0	0
T70	1633	0	0	0
T87	983	0	0	0
T88	0	26	0	0
T89	0	27	0	0
T91	0	149	0	0

sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7405043	1308	0	0
T21	10697	13	0	0
T30	27384	0	0	0
T35	0	14	0	0
T37	1424	0	0	0
T52	0	51	0	0
T59	5015	17	0	0
T64	0	18	0	0
T65	3382	10	0	0
T66	5727	11	0	0
T67	0	10	0	0
T68	1129	0	0	0
T69	929	0	0	0
T70	1633	4	0	0
T87	983	0	0	0
T88	0	15	0	0

sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7405043	1326	0	0
T21	10697	14	0	0
T30	27384	0	0	0
T35	0	9	0	0
T37	1424	0	0	0
T52	0	53	0	0
T59	5015	14	0	0
T64	0	19	0	0
T65	3382	9	0	0
T66	5727	0	0	0
T67	0	8	0	0
T68	1129	0	0	0
T69	929	0	0	0
T70	1633	1	0	0
T87	983	0	0	0
T88	0	12	0	0
T89	0	26	0	0

sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7405043	1222	0	0
T21	10697	7	0	0
T30	27384	0	0	0
T35	0	3	0	0
T37	1424	0	0	0
T52	0	50	0	0
T59	5015	16	0	0
T64	0	11	0	0
T65	3382	4	0	0
T66	5727	3	0	0
T67	0	9	0	0
T68	1129	0	0	0
T69	929	0	0	0
T70	1633	5	0	0
T87	983	0	0	0
T88	0	21	0	0

sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7405043	1318	0	0
T21	10697	6	0	0
T30	27384	0	0	0
T35	0	4	0	0
T37	1424	0	0	0
T52	0	37	0	0
T59	5015	19	0	0
T64	0	20	0	0
T65	3382	8	0	0
T66	5727	0	0	0
T67	0	10	0	0
T68	1129	0	0	0
T69	929	0	0	0
T70	1633	0	0	0
T87	983	0	0	0
T88	0	9	0	0
T89	0	34	0	0
T90	0	12	0	0

sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7405043	1342	0	0
T21	10697	12	0	0
T30	27384	0	0	0
T35	0	7	0	0
T37	1424	0	0	0
T52	0	43	0	0
T59	5015	18	0	0
T64	0	23	0	0
T65	3382	8	0	0
T66	5727	4	0	0
T67	0	9	0	0
T68	1129	0	0	0
T69	929	0	0	0
T70	1633	3	0	0
T87	983	0	0	0
T88	0	38	0	0