Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	767298	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

250157

1

T1

2554

T2

2495

T3

2307

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	871395	1			T1	96553		T2	46095		T3	9241
values[0x0]	72530	1			T1	610		T2	595		T3	533
values[0x1]	73530	1			T1	632		T2	641		T3	529

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	527355	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

490100

1

T1

34351

T2

17352

T3

4797

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3090	1			T1	379		T3	30		T4	12
valid_sources[0x01]	3273	1			T1	457		T3	33		T7	96
valid_sources[0x02]	3139	1			T1	456		T3	58		T4	7
valid_sources[0x03]	3165	1			T1	411		T3	38		T4	10
valid_sources[0x04]	3348	1			T1	474		T3	44		T7	135
valid_sources[0x05]	3281	1			T1	344		T3	29		T4	1
valid_sources[0x06]	3539	1			T1	358		T3	32		T4	2
valid_sources[0x07]	3176	1			T1	371		T3	26		T4	6
valid_sources[0x08]	3427	1			T1	458		T3	83		T4	1
valid_sources[0x09]	3390	1			T1	465		T3	59		T4	6
valid_sources[0x0a]	3273	1			T1	305		T3	48		T4	8
valid_sources[0x0b]	3254	1			T1	364		T3	38		T4	5
valid_sources[0x0c]	3116	1			T1	378		T3	23		T4	2
valid_sources[0x0d]	3264	1			T1	451		T3	47		T4	11
valid_sources[0x0e]	3319	1			T1	371		T3	46		T4	1
valid_sources[0x0f]	3133	1			T1	319		T3	34		T4	1
valid_sources[0x10]	3035	1			T1	281		T3	36		T4	3
valid_sources[0x11]	3393	1			T1	270		T3	55		T4	3
valid_sources[0x12]	3620	1			T1	502		T3	79		T4	3
valid_sources[0x13]	3219	1			T1	416		T3	51		T4	6
valid_sources[0x14]	3421	1			T1	307		T3	41		T4	3
valid_sources[0x15]	3165	1			T1	458		T3	32		T4	5
valid_sources[0x16]	3331	1			T1	382		T3	52		T4	4
valid_sources[0x17]	4109	1			T1	475		T3	38		T4	16
valid_sources[0x18]	2948	1			T1	315		T3	17		T4	5
valid_sources[0x19]	3253	1			T1	278		T3	48		T4	14
valid_sources[0x1a]	3008	1			T1	249		T3	59		T4	4
valid_sources[0x1b]	3314	1			T1	288		T3	38		T7	115
valid_sources[0x1c]	3084	1			T1	270		T3	54		T4	3
valid_sources[0x1d]	3188	1			T1	372		T3	40		T4	9
valid_sources[0x1e]	3050	1			T1	341		T3	36		T7	120
valid_sources[0x1f]	3536	1			T1	551		T3	62		T4	15
valid_sources[0x20]	3218	1			T1	342		T3	43		T4	4
valid_sources[0x21]	3309	1			T1	378		T3	45		T4	4
valid_sources[0x22]	4303	1			T1	469		T3	27		T4	14
valid_sources[0x23]	3165	1			T1	352		T3	30		T4	2
valid_sources[0x24]	4658	1			T1	472		T3	26		T4	5
valid_sources[0x25]	3296	1			T1	327		T3	39		T4	6
valid_sources[0x26]	2928	1			T1	382		T3	31		T4	6
valid_sources[0x27]	5736	1			T1	332		T3	41		T4	3
valid_sources[0x28]	3134	1			T1	399		T3	86		T4	3
valid_sources[0x29]	2808	1			T1	331		T3	32		T4	7
valid_sources[0x2a]	3807	1			T1	446		T3	44		T4	4
valid_sources[0x2b]	3119	1			T1	370		T3	45		T4	4
valid_sources[0x2c]	2950	1			T1	387		T3	60		T4	11
valid_sources[0x2d]	2938	1			T1	308		T3	29		T4	5
valid_sources[0x2e]	3116	1			T1	304		T3	56		T4	3
valid_sources[0x2f]	3691	1			T1	344		T3	46		T4	9
valid_sources[0x30]	3982	1			T1	438		T3	36		T4	1
valid_sources[0x31]	3155	1			T1	351		T3	53		T4	4
valid_sources[0x32]	3198	1			T1	302		T3	25		T4	6
valid_sources[0x33]	3551	1			T1	407		T3	33		T4	10
valid_sources[0x34]	3422	1			T1	413		T3	49		T4	15
valid_sources[0x35]	3471	1			T1	310		T3	23		T4	6
valid_sources[0x36]	3018	1			T1	364		T3	18		T4	3
valid_sources[0x37]	3221	1			T1	384		T3	15		T4	2
valid_sources[0x38]	3635	1			T1	389		T3	56		T4	13
valid_sources[0x39]	7363	1			T1	540		T3	34		T4	1
valid_sources[0x3a]	3672	1			T1	421		T3	43		T4	5
valid_sources[0x3b]	3579	1			T1	404		T3	50		T7	119
valid_sources[0x3c]	3359	1			T1	376		T3	21		T4	6
valid_sources[0x3d]	31500	1			T1	314		T2	28386		T3	39
valid_sources[0x3e]	3206	1			T1	278		T3	39		T4	7
valid_sources[0x3f]	3255	1			T1	319		T3	48		T4	2
valid_sources[0x40]	3169	1			T1	396		T3	79		T4	1
valid_sources[0x41]	3108	1			T1	316		T3	49		T4	5
valid_sources[0x42]	3319	1			T1	497		T3	35		T4	7
valid_sources[0x43]	3437	1			T1	389		T3	72		T4	2
valid_sources[0x44]	3245	1			T1	421		T3	38		T4	8
valid_sources[0x45]	3153	1			T1	294		T3	14		T4	4
valid_sources[0x46]	3046	1			T1	393		T3	36		T4	5
valid_sources[0x47]	3198	1			T1	445		T3	53		T4	5
valid_sources[0x48]	3264	1			T1	422		T3	47		T4	2
valid_sources[0x49]	3083	1			T1	437		T3	49		T4	9
valid_sources[0x4a]	3798	1			T1	343		T3	27		T4	5
valid_sources[0x4b]	7546	1			T1	437		T2	2592		T3	59
valid_sources[0x4c]	3196	1			T1	266		T3	35		T7	104
valid_sources[0x4d]	3117	1			T1	379		T3	22		T4	9
valid_sources[0x4e]	3335	1			T1	339		T3	57		T4	5
valid_sources[0x4f]	3248	1			T1	371		T3	63		T4	4
valid_sources[0x50]	3432	1			T1	378		T3	19		T4	7
valid_sources[0x51]	2920	1			T1	309		T3	24		T4	14
valid_sources[0x52]	3600	1			T1	555		T3	45		T4	12
valid_sources[0x53]	3059	1			T1	458		T3	42		T4	2
valid_sources[0x54]	3703	1			T1	394		T3	22		T4	3
valid_sources[0x55]	3280	1			T1	346		T3	42		T4	5
valid_sources[0x56]	3228	1			T1	422		T3	11		T4	4
valid_sources[0x57]	2871	1			T1	481		T3	37		T7	116
valid_sources[0x58]	3213	1			T1	467		T3	33		T4	9
valid_sources[0x59]	2990	1			T1	391		T3	44		T4	4
valid_sources[0x5a]	3323	1			T1	308		T3	50		T4	7
valid_sources[0x5b]	3606	1			T1	437		T3	29		T4	7
valid_sources[0x5c]	3312	1			T1	316		T3	23		T4	6
valid_sources[0x5d]	3085	1			T1	389		T3	40		T4	14
valid_sources[0x5e]	3171	1			T1	416		T3	44		T4	3
valid_sources[0x5f]	3306	1			T1	372		T3	19		T4	4
valid_sources[0x60]	7635	1			T1	307		T3	51		T4	2
valid_sources[0x61]	3539	1			T1	431		T3	30		T4	4
valid_sources[0x62]	5303	1			T1	334		T2	2109		T3	46
valid_sources[0x63]	3138	1			T1	380		T3	31		T4	7
valid_sources[0x64]	3029	1			T1	280		T3	24		T4	8
valid_sources[0x65]	2913	1			T1	354		T3	56		T4	3
valid_sources[0x66]	2923	1			T1	378		T3	38		T4	5
valid_sources[0x67]	3171	1			T1	250		T3	51		T4	1
valid_sources[0x68]	3128	1			T1	361		T3	62		T4	2
valid_sources[0x69]	3188	1			T1	362		T3	43		T4	4
valid_sources[0x6a]	3441	1			T1	299		T3	27		T4	2
valid_sources[0x6b]	3273	1			T1	308		T3	31		T4	6
valid_sources[0x6c]	3365	1			T1	420		T3	24		T4	8
valid_sources[0x6d]	3225	1			T1	340		T3	44		T4	5
valid_sources[0x6e]	3922	1			T1	489		T3	39		T7	120
valid_sources[0x6f]	3186	1			T1	378		T3	62		T4	3
valid_sources[0x70]	3269	1			T1	368		T3	48		T4	5
valid_sources[0x71]	4887	1			T1	301		T3	47		T4	7
valid_sources[0x72]	3132	1			T1	300		T3	62		T4	8
valid_sources[0x73]	2969	1			T1	454		T3	24		T4	1
valid_sources[0x74]	3037	1			T1	369		T3	16		T4	4
valid_sources[0x75]	3225	1			T1	371		T3	32		T4	6
valid_sources[0x76]	3278	1			T1	273		T3	30		T4	3
valid_sources[0x77]	3396	1			T1	461		T3	41		T4	2
valid_sources[0x78]	4167	1			T1	451		T3	43		T4	4
valid_sources[0x79]	3222	1			T1	449		T3	42		T4	5
valid_sources[0x7a]	3077	1			T1	356		T3	11		T4	6
valid_sources[0x7b]	8051	1			T1	286		T3	40		T4	10
valid_sources[0x7c]	3077	1			T1	355		T3	45		T4	7
valid_sources[0x7d]	3359	1			T1	574		T3	53		T4	4
valid_sources[0x7e]	3098	1			T1	486		T3	42		T4	7
valid_sources[0x7f]	3444	1			T1	319		T3	33		T4	4
valid_sources[0x80]	2971	1			T1	301		T3	31		T4	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

138381

1

T1

1714

T2

1658

T3

1555

values[0x0]

all_enables

biggest_size

59679

1

T1

466

T2

452

T3

414

values[0x1]

all_enables

biggest_size

52097

1

T1

374

T2

385

T3

338