| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| keymgr_dpe_reg_block.control_shadowed.dest_sel_shadowed_errs_cov | 100.00 | 1 | 100 | 1 | 64 | 64 |
| keymgr_dpe_reg_block.control_shadowed.operation_shadowed_errs_cov | 100.00 | 1 | 100 | 1 | 64 | 64 |
| keymgr_dpe_reg_block.control_shadowed.slot_dst_sel_shadowed_errs_cov | 100.00 | 1 | 100 | 1 | 64 | 64 |
| keymgr_dpe_reg_block.control_shadowed.slot_src_sel_shadowed_errs_cov | 100.00 | 1 | 100 | 1 | 64 | 64 |
| keymgr_dpe_reg_block.max_key_ver_shadowed.val_shadowed_errs_cov | 100.00 | 1 | 100 | 1 | 64 | 64 |
| keymgr_dpe_reg_block.reseed_interval_shadowed.val_shadowed_errs_cov | 100.00 | 1 | 100 | 1 | 64 | 64 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 2 | 0 | 2 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_storage_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
| cp_update_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 2 | 0 | 2 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_storage_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
| cp_update_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 2 | 0 | 2 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_storage_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
| cp_update_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 2 | 0 | 2 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_storage_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
| cp_update_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 2 | 0 | 2 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_storage_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
| cp_update_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 2 | 0 | 2 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_storage_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
| cp_update_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 1 | 0 | 1 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| storage_err | 18582 | 1 | T1 | 292 | T2 | 298 | T3 | 258 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 1 | 0 | 1 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| update_err | 47 | 1 | T60 | 1 | T61 | 1 | T65 | 2 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 1 | 0 | 1 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| storage_err | 18582 | 1 | T1 | 292 | T2 | 298 | T3 | 258 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 1 | 0 | 1 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| update_err | 52 | 1 | T44 | 2 | T60 | 1 | T61 | 2 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 1 | 0 | 1 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| storage_err | 18582 | 1 | T1 | 292 | T2 | 298 | T3 | 258 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 1 | 0 | 1 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| update_err | 40 | 1 | T60 | 1 | T61 | 1 | T65 | 2 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 1 | 0 | 1 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| storage_err | 18582 | 1 | T1 | 292 | T2 | 298 | T3 | 258 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 1 | 0 | 1 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| update_err | 36 | 1 | T60 | 1 | T65 | 2 | T63 | 3 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 1 | 0 | 1 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| storage_err | 6059 | 1 | T1 | 64 | T2 | 66 | T3 | 68 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 1 | 0 | 1 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| update_err | 72 | 1 | T44 | 2 | T65 | 1 | T62 | 1 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 1 | 0 | 1 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| storage_err | 2784 | 1 | T1 | 2 | T2 | 2 | T3 | 2 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 1 | 0 | 1 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| update_err | 78 | 1 | T44 | 3 | T60 | 1 | T61 | 4 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |