Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sideload_ctrl.u_mubi_buf	100.00	100.00					100.00
tb.dut.gen_sw_assigns[0].u_mubi_buf	100.00	100.00					100.00
tb.dut.gen_sw_assigns[1].u_mubi_buf	100.00	100.00					100.00
tb.dut.gen_sw_assigns[2].u_mubi_buf	100.00	100.00					100.00
tb.dut.gen_sw_assigns[3].u_mubi_buf	100.00	100.00					100.00
tb.dut.gen_sw_assigns[4].u_mubi_buf	100.00	100.00					100.00
tb.dut.gen_sw_assigns[5].u_mubi_buf	100.00	100.00					100.00
tb.dut.gen_sw_assigns[6].u_mubi_buf	100.00	100.00					100.00
tb.dut.gen_sw_assigns[7].u_mubi_buf	100.00	100.00					100.00

---

Module Instance : tb.dut.u_sideload_ctrl.u_mubi_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.51	90.00	75.86		33.33	83.33	100.00	u_sideload_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=3,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_sideload_ctrl.u_mubi_buf

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	3	3

---

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=2,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.gen_sw_assigns[0].u_mubi_buf

SCORE	LINE
100.00	100.00

tb.dut.gen_sw_assigns[1].u_mubi_buf

SCORE	LINE
100.00	100.00

tb.dut.gen_sw_assigns[2].u_mubi_buf

SCORE	LINE
100.00	100.00

tb.dut.gen_sw_assigns[3].u_mubi_buf

SCORE	LINE
100.00	100.00

tb.dut.gen_sw_assigns[4].u_mubi_buf

SCORE	LINE
100.00	100.00

tb.dut.gen_sw_assigns[5].u_mubi_buf

SCORE	LINE
100.00	100.00

tb.dut.gen_sw_assigns[6].u_mubi_buf

SCORE	LINE
100.00	100.00

tb.dut.gen_sw_assigns[7].u_mubi_buf

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	2	2

---

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	945	945	0	0
OutputsKnown_A	53719254	53161281	0	0
gen_no_flops.OutputDelay_A	53719254	53161281	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	945	945	0	0
T1	9	9	0	0
T2	9	9	0	0
T3	9	9	0	0
T4	9	9	0	0
T5	9	9	0	0
T7	9	9	0	0
T8	9	9	0	0
T9	9	9	0	0
T10	9	9	0	0
T14	9	9	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53719254	53161281	0	0
T1	5432616	5431923	0	0
T2	5093451	5092794	0	0
T3	755640	754785	0	0
T4	336402	274230	0	0
T5	364005	242748	0	0
T7	1044135	1043262	0	0
T8	228726	228186	0	0
T9	1106361	1105686	0	0
T10	658881	658170	0	0
T14	9468	8829	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53719254	53161281	0	0
T1	5432616	5431923	0	0
T2	5093451	5092794	0	0
T3	755640	754785	0	0
T4	336402	274230	0	0
T5	364005	242748	0	0
T7	1044135	1043262	0	0
T8	228726	228186	0	0
T9	1106361	1105686	0	0
T10	658881	658170	0	0
T14	9468	8829	0	0

Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	3	3

---

Assert Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	105	105	0	0
OutputsKnown_A	5968806	5906809	0	0
gen_no_flops.OutputDelay_A	5968806	5906809	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105	105	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5968806	5906809	0	0
T1	603624	603547	0	0
T2	565939	565866	0	0
T3	83960	83865	0	0
T4	37378	30470	0	0
T5	40445	26972	0	0
T7	116015	115918	0	0
T8	25414	25354	0	0
T9	122929	122854	0	0
T10	73209	73130	0	0
T14	1052	981	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5968806	5906809	0	0
T1	603624	603547	0	0
T2	565939	565866	0	0
T3	83960	83865	0	0
T4	37378	30470	0	0
T5	40445	26972	0	0
T7	116015	115918	0	0
T8	25414	25354	0	0
T9	122929	122854	0	0
T10	73209	73130	0	0
T14	1052	981	0	0

Line Coverage for Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	2	2

---

Assert Coverage for Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	105	105	0	0
OutputsKnown_A	5968806	5906809	0	0
gen_no_flops.OutputDelay_A	5968806	5906809	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105	105	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5968806	5906809	0	0
T1	603624	603547	0	0
T2	565939	565866	0	0
T3	83960	83865	0	0
T4	37378	30470	0	0
T5	40445	26972	0	0
T7	116015	115918	0	0
T8	25414	25354	0	0
T9	122929	122854	0	0
T10	73209	73130	0	0
T14	1052	981	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5968806	5906809	0	0
T1	603624	603547	0	0
T2	565939	565866	0	0
T3	83960	83865	0	0
T4	37378	30470	0	0
T5	40445	26972	0	0
T7	116015	115918	0	0
T8	25414	25354	0	0
T9	122929	122854	0	0
T10	73209	73130	0	0
T14	1052	981	0	0

Line Coverage for Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	2	2

---

Assert Coverage for Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	105	105	0	0
OutputsKnown_A	5968806	5906809	0	0
gen_no_flops.OutputDelay_A	5968806	5906809	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105	105	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5968806	5906809	0	0
T1	603624	603547	0	0
T2	565939	565866	0	0
T3	83960	83865	0	0
T4	37378	30470	0	0
T5	40445	26972	0	0
T7	116015	115918	0	0
T8	25414	25354	0	0
T9	122929	122854	0	0
T10	73209	73130	0	0
T14	1052	981	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5968806	5906809	0	0
T1	603624	603547	0	0
T2	565939	565866	0	0
T3	83960	83865	0	0
T4	37378	30470	0	0
T5	40445	26972	0	0
T7	116015	115918	0	0
T8	25414	25354	0	0
T9	122929	122854	0	0
T10	73209	73130	0	0
T14	1052	981	0	0

Line Coverage for Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	2	2

---

Assert Coverage for Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	105	105	0	0
OutputsKnown_A	5968806	5906809	0	0
gen_no_flops.OutputDelay_A	5968806	5906809	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105	105	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5968806	5906809	0	0
T1	603624	603547	0	0
T2	565939	565866	0	0
T3	83960	83865	0	0
T4	37378	30470	0	0
T5	40445	26972	0	0
T7	116015	115918	0	0
T8	25414	25354	0	0
T9	122929	122854	0	0
T10	73209	73130	0	0
T14	1052	981	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5968806	5906809	0	0
T1	603624	603547	0	0
T2	565939	565866	0	0
T3	83960	83865	0	0
T4	37378	30470	0	0
T5	40445	26972	0	0
T7	116015	115918	0	0
T8	25414	25354	0	0
T9	122929	122854	0	0
T10	73209	73130	0	0
T14	1052	981	0	0

Line Coverage for Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	2	2

---

Assert Coverage for Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	105	105	0	0
OutputsKnown_A	5968806	5906809	0	0
gen_no_flops.OutputDelay_A	5968806	5906809	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105	105	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5968806	5906809	0	0
T1	603624	603547	0	0
T2	565939	565866	0	0
T3	83960	83865	0	0
T4	37378	30470	0	0
T5	40445	26972	0	0
T7	116015	115918	0	0
T8	25414	25354	0	0
T9	122929	122854	0	0
T10	73209	73130	0	0
T14	1052	981	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5968806	5906809	0	0
T1	603624	603547	0	0
T2	565939	565866	0	0
T3	83960	83865	0	0
T4	37378	30470	0	0
T5	40445	26972	0	0
T7	116015	115918	0	0
T8	25414	25354	0	0
T9	122929	122854	0	0
T10	73209	73130	0	0
T14	1052	981	0	0

Line Coverage for Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	2	2

---

Assert Coverage for Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	105	105	0	0
OutputsKnown_A	5968806	5906809	0	0
gen_no_flops.OutputDelay_A	5968806	5906809	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105	105	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5968806	5906809	0	0
T1	603624	603547	0	0
T2	565939	565866	0	0
T3	83960	83865	0	0
T4	37378	30470	0	0
T5	40445	26972	0	0
T7	116015	115918	0	0
T8	25414	25354	0	0
T9	122929	122854	0	0
T10	73209	73130	0	0
T14	1052	981	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5968806	5906809	0	0
T1	603624	603547	0	0
T2	565939	565866	0	0
T3	83960	83865	0	0
T4	37378	30470	0	0
T5	40445	26972	0	0
T7	116015	115918	0	0
T8	25414	25354	0	0
T9	122929	122854	0	0
T10	73209	73130	0	0
T14	1052	981	0	0

Line Coverage for Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	2	2

---

Assert Coverage for Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	105	105	0	0
OutputsKnown_A	5968806	5906809	0	0
gen_no_flops.OutputDelay_A	5968806	5906809	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105	105	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5968806	5906809	0	0
T1	603624	603547	0	0
T2	565939	565866	0	0
T3	83960	83865	0	0
T4	37378	30470	0	0
T5	40445	26972	0	0
T7	116015	115918	0	0
T8	25414	25354	0	0
T9	122929	122854	0	0
T10	73209	73130	0	0
T14	1052	981	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5968806	5906809	0	0
T1	603624	603547	0	0
T2	565939	565866	0	0
T3	83960	83865	0	0
T4	37378	30470	0	0
T5	40445	26972	0	0
T7	116015	115918	0	0
T8	25414	25354	0	0
T9	122929	122854	0	0
T10	73209	73130	0	0
T14	1052	981	0	0

Line Coverage for Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	2	2

---

Assert Coverage for Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	105	105	0	0
OutputsKnown_A	5968806	5906809	0	0
gen_no_flops.OutputDelay_A	5968806	5906809	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105	105	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5968806	5906809	0	0
T1	603624	603547	0	0
T2	565939	565866	0	0
T3	83960	83865	0	0
T4	37378	30470	0	0
T5	40445	26972	0	0
T7	116015	115918	0	0
T8	25414	25354	0	0
T9	122929	122854	0	0
T10	73209	73130	0	0
T14	1052	981	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5968806	5906809	0	0
T1	603624	603547	0	0
T2	565939	565866	0	0
T3	83960	83865	0	0
T4	37378	30470	0	0
T5	40445	26972	0	0
T7	116015	115918	0	0
T8	25414	25354	0	0
T9	122929	122854	0	0
T10	73209	73130	0	0
T14	1052	981	0	0

Line Coverage for Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	2	2

---

Assert Coverage for Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	105	105	0	0
OutputsKnown_A	5968806	5906809	0	0
gen_no_flops.OutputDelay_A	5968806	5906809	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105	105	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5968806	5906809	0	0
T1	603624	603547	0	0
T2	565939	565866	0	0
T3	83960	83865	0	0
T4	37378	30470	0	0
T5	40445	26972	0	0
T7	116015	115918	0	0
T8	25414	25354	0	0
T9	122929	122854	0	0
T10	73209	73130	0	0
T14	1052	981	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5968806	5906809	0	0
T1	603624	603547	0	0
T2	565939	565866	0	0
T3	83960	83865	0	0
T4	37378	30470	0	0
T5	40445	26972	0	0
T7	116015	115918	0	0
T8	25414	25354	0	0
T9	122929	122854	0	0
T10	73209	73130	0	0
T14	1052	981	0	0