Unified Coverage Report :: Module :: keymgr_dpe_csr_assert_fpv

Module : keymgr_dpe_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_dpe_csr_assert_0/keymgr_dpe_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_dpe_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_dpe_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_dpe_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	22	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	7277817	10355	0	0
intr_enable_rd_A	7277817	2133	0	0
key_version_rd_A	7277817	1945	0	0
reseed_interval_regwen_rd_A	7277817	785	0	0
salt_0_rd_A	7277817	1775	0	0
salt_1_rd_A	7277817	1717	0	0
salt_2_rd_A	7277817	1747	0	0
salt_3_rd_A	7277817	1854	0	0
salt_4_rd_A	7277817	1865	0	0
salt_5_rd_A	7277817	1755	0	0
salt_6_rd_A	7277817	1877	0	0
salt_7_rd_A	7277817	1846	0	0
sideload_clear_rd_A	7277817	1891	0	0
slot_policy_rd_A	7277817	2590	0	0
sw_binding_0_rd_A	7277817	1767	0	0
sw_binding_1_rd_A	7277817	1835	0	0
sw_binding_2_rd_A	7277817	1825	0	0
sw_binding_3_rd_A	7277817	1659	0	0
sw_binding_4_rd_A	7277817	1796	0	0
sw_binding_5_rd_A	7277817	1958	0	0
sw_binding_6_rd_A	7277817	1798	0	0
sw_binding_7_rd_A	7277817	1854	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7277817	10355	0	0
T17	1205	3	0	0
T18	1699	121	0	0
T19	1435	57	0	0
T23	0	475	0	0
T28	1152	32	0	0
T66	1124	18	0	0
T67	938	0	0	0
T68	1921	59	0	0
T99	1303	15	0	0
T100	2201	6	0	0
T101	1775	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7277817	2133	0	0
T23	3005	0	0	0
T24	1526	0	0	0
T26	0	17	0	0
T34	0	29	0	0
T35	5285	9	0	0
T37	979	21	0	0
T60	0	28	0	0
T63	0	33	0	0
T65	0	30	0	0
T69	8946	14	0	0
T70	1845	0	0	0
T85	1062	0	0	0
T86	822	0	0	0
T87	1327	0	0	0
T101	1775	16	0	0
T102	0	21	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7277817	1945	0	0
T23	3005	0	0	0
T24	1526	0	0	0
T25	4432	0	0	0
T26	0	10	0	0
T34	0	6	0	0
T35	5285	0	0	0
T60	0	26	0	0
T63	0	16	0	0
T65	0	31	0	0
T69	8946	65	0	0
T70	1845	0	0	0
T81	0	32	0	0
T85	1062	0	0	0
T86	822	0	0	0
T87	1327	0	0	0
T101	1775	8	0	0
T103	0	67	0	0
T104	0	104	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7277817	785	0	0
T23	3005	0	0	0
T24	1526	0	0	0
T25	4432	0	0	0
T34	0	9	0	0
T35	5285	7	0	0
T60	0	8	0	0
T63	0	16	0	0
T65	0	20	0	0
T69	8946	70	0	0
T70	1845	0	0	0
T81	0	18	0	0
T85	1062	0	0	0
T86	822	0	0	0
T87	1327	0	0	0
T101	1775	3	0	0
T103	0	13	0	0
T104	0	51	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7277817	1775	0	0
T23	3005	0	0	0
T24	1526	0	0	0
T25	4432	0	0	0
T26	0	25	0	0
T34	0	16	0	0
T35	5285	3	0	0
T60	4930	11	0	0
T63	0	13	0	0
T65	0	15	0	0
T69	8946	39	0	0
T70	1845	0	0	0
T81	0	46	0	0
T85	1062	0	0	0
T86	822	0	0	0
T87	1327	0	0	0
T103	0	115	0	0
T104	0	71	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7277817	1717	0	0
T23	3005	0	0	0
T24	1526	0	0	0
T25	4432	0	0	0
T26	0	24	0	0
T34	0	16	0	0
T35	5285	0	0	0
T60	0	16	0	0
T63	0	17	0	0
T65	0	17	0	0
T69	8946	85	0	0
T70	1845	0	0	0
T81	0	37	0	0
T85	1062	0	0	0
T86	822	0	0	0
T87	1327	0	0	0
T101	1775	8	0	0
T103	0	51	0	0
T104	0	22	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7277817	1747	0	0
T23	3005	0	0	0
T24	1526	0	0	0
T25	4432	0	0	0
T26	0	15	0	0
T34	0	14	0	0
T35	5285	7	0	0
T60	0	8	0	0
T63	0	20	0	0
T65	0	17	0	0
T69	8946	36	0	0
T70	1845	0	0	0
T81	0	44	0	0
T85	1062	0	0	0
T86	822	0	0	0
T87	1327	0	0	0
T101	1775	5	0	0
T103	0	70	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7277817	1854	0	0
T23	3005	0	0	0
T24	1526	0	0	0
T25	4432	0	0	0
T26	0	33	0	0
T34	0	22	0	0
T35	5285	8	0	0
T60	0	15	0	0
T63	0	26	0	0
T65	0	15	0	0
T69	8946	41	0	0
T70	1845	0	0	0
T81	0	89	0	0
T85	1062	0	0	0
T86	822	0	0	0
T87	1327	0	0	0
T101	1775	17	0	0
T103	0	111	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7277817	1865	0	0
T23	3005	0	0	0
T24	1526	0	0	0
T25	4432	0	0	0
T26	0	5	0	0
T34	0	29	0	0
T35	5285	5	0	0
T60	0	18	0	0
T63	0	26	0	0
T65	0	11	0	0
T69	8946	73	0	0
T70	1845	0	0	0
T81	0	27	0	0
T85	1062	0	0	0
T86	822	0	0	0
T87	1327	0	0	0
T101	1775	11	0	0
T103	0	76	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7277817	1755	0	0
T23	3005	0	0	0
T24	1526	0	0	0
T25	4432	0	0	0
T26	0	42	0	0
T34	0	14	0	0
T35	5285	0	0	0
T60	0	17	0	0
T63	0	26	0	0
T65	0	16	0	0
T69	8946	31	0	0
T70	1845	0	0	0
T81	0	49	0	0
T85	1062	0	0	0
T86	822	0	0	0
T87	1327	0	0	0
T101	1775	5	0	0
T103	0	81	0	0
T104	0	74	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7277817	1877	0	0
T23	3005	0	0	0
T24	1526	0	0	0
T25	4432	0	0	0
T26	0	6	0	0
T34	0	4	0	0
T35	5285	13	0	0
T60	0	9	0	0
T63	0	5	0	0
T65	0	25	0	0
T69	8946	18	0	0
T70	1845	0	0	0
T81	0	52	0	0
T85	1062	0	0	0
T86	822	0	0	0
T87	1327	0	0	0
T101	1775	9	0	0
T103	0	105	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7277817	1846	0	0
T23	3005	0	0	0
T24	1526	0	0	0
T25	4432	0	0	0
T26	0	14	0	0
T34	0	9	0	0
T35	5285	7	0	0
T60	0	21	0	0
T63	0	11	0	0
T65	0	16	0	0
T69	8946	37	0	0
T70	1845	0	0	0
T81	0	47	0	0
T85	1062	0	0	0
T86	822	0	0	0
T87	1327	0	0	0
T101	1775	14	0	0
T103	0	105	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7277817	1891	0	0
T23	3005	0	0	0
T24	1526	0	0	0
T25	4432	0	0	0
T26	0	9	0	0
T34	0	20	0	0
T35	5285	5	0	0
T60	0	21	0	0
T63	0	8	0	0
T65	0	17	0	0
T69	8946	42	0	0
T70	1845	0	0	0
T81	0	48	0	0
T85	1062	0	0	0
T86	822	0	0	0
T87	1327	0	0	0
T101	1775	4	0	0
T103	0	107	0	0

slot_policy_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7277817	2590	0	0
T23	3005	0	0	0
T24	1526	0	0	0
T25	4432	0	0	0
T26	0	50	0	0
T34	0	16	0	0
T35	5285	0	0	0
T60	0	21	0	0
T63	0	12	0	0
T65	0	8	0	0
T69	8946	39	0	0
T70	1845	0	0	0
T81	0	16	0	0
T85	1062	0	0	0
T86	822	0	0	0
T87	1327	0	0	0
T101	1775	4	0	0
T103	0	164	0	0
T104	0	18	0	0

sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7277817	1767	0	0
T23	3005	0	0	0
T24	1526	0	0	0
T25	4432	0	0	0
T26	0	22	0	0
T34	0	6	0	0
T35	5285	5	0	0
T60	0	23	0	0
T63	0	20	0	0
T65	0	15	0	0
T69	8946	39	0	0
T70	1845	0	0	0
T81	0	4	0	0
T85	1062	0	0	0
T86	822	0	0	0
T87	1327	0	0	0
T101	1775	3	0	0
T103	0	94	0	0

sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7277817	1835	0	0
T23	3005	0	0	0
T24	1526	0	0	0
T25	4432	0	0	0
T26	0	8	0	0
T34	0	8	0	0
T35	5285	8	0	0
T60	0	18	0	0
T63	0	31	0	0
T65	0	18	0	0
T69	8946	37	0	0
T70	1845	0	0	0
T81	0	52	0	0
T85	1062	0	0	0
T86	822	0	0	0
T87	1327	0	0	0
T101	1775	1	0	0
T103	0	118	0	0

sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7277817	1825	0	0
T23	3005	0	0	0
T24	1526	0	0	0
T25	4432	0	0	0
T26	0	33	0	0
T35	5285	6	0	0
T60	0	8	0	0
T63	0	22	0	0
T65	0	15	0	0
T69	8946	33	0	0
T70	1845	0	0	0
T81	0	59	0	0
T85	1062	0	0	0
T86	822	0	0	0
T87	1327	0	0	0
T101	1775	12	0	0
T103	0	91	0	0
T104	0	100	0	0

sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7277817	1659	0	0
T23	3005	0	0	0
T24	1526	0	0	0
T25	4432	0	0	0
T26	0	29	0	0
T34	0	21	0	0
T35	5285	2	0	0
T60	0	11	0	0
T63	0	7	0	0
T65	0	6	0	0
T69	8946	31	0	0
T70	1845	0	0	0
T81	0	7	0	0
T85	1062	0	0	0
T86	822	0	0	0
T87	1327	0	0	0
T101	1775	1	0	0
T103	0	110	0	0

sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7277817	1796	0	0
T23	3005	0	0	0
T24	1526	0	0	0
T25	4432	0	0	0
T26	0	26	0	0
T34	0	14	0	0
T35	5285	0	0	0
T60	4930	18	0	0
T63	0	22	0	0
T65	0	38	0	0
T69	8946	47	0	0
T70	1845	0	0	0
T81	0	30	0	0
T83	0	203	0	0
T85	1062	0	0	0
T86	822	0	0	0
T87	1327	0	0	0
T103	0	101	0	0
T104	0	34	0	0

sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7277817	1958	0	0
T23	3005	0	0	0
T24	1526	0	0	0
T25	4432	0	0	0
T26	0	31	0	0
T34	0	9	0	0
T35	5285	0	0	0
T60	0	10	0	0
T63	0	7	0	0
T65	0	9	0	0
T69	8946	47	0	0
T70	1845	0	0	0
T81	0	78	0	0
T85	1062	0	0	0
T86	822	0	0	0
T87	1327	0	0	0
T101	1775	5	0	0
T103	0	114	0	0
T104	0	70	0	0

sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7277817	1798	0	0
T23	3005	0	0	0
T24	1526	0	0	0
T25	4432	0	0	0
T26	0	31	0	0
T35	5285	4	0	0
T60	0	13	0	0
T63	0	13	0	0
T65	0	27	0	0
T69	8946	14	0	0
T70	1845	0	0	0
T81	0	37	0	0
T85	1062	0	0	0
T86	822	0	0	0
T87	1327	0	0	0
T101	1775	1	0	0
T103	0	135	0	0
T104	0	24	0	0

sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7277817	1854	0	0
T23	3005	0	0	0
T24	1526	0	0	0
T25	4432	0	0	0
T26	0	26	0	0
T34	0	4	0	0
T35	5285	0	0	0
T60	0	21	0	0
T63	0	15	0	0
T65	0	15	0	0
T69	8946	39	0	0
T70	1845	0	0	0
T81	0	65	0	0
T85	1062	0	0	0
T86	822	0	0	0
T87	1327	0	0	0
T101	1775	8	0	0
T103	0	101	0	0
T104	0	79	0	0