Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1433644	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

235277

1

T1

774

T2

3125

T3

3247

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1533809	1			T1	777		T2	6424		T3	70366
values[0x0]	67110	1			T1	260		T2	797		T3	775
values[0x1]	68002	1			T1	284		T2	761		T3	778

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	969761	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

699160

1

T1

963

T2

4429

T3

25779

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4597	1			T2	28		T3	332		T4	18
valid_sources[0x01]	5007	1			T2	26		T3	355		T4	24
valid_sources[0x02]	5312	1			T2	39		T3	345		T4	20
valid_sources[0x03]	5201	1			T2	32		T3	266		T4	19
valid_sources[0x04]	4821	1			T2	35		T3	227		T4	10
valid_sources[0x05]	5042	1			T2	27		T3	340		T4	18
valid_sources[0x06]	5092	1			T2	36		T3	281		T4	23
valid_sources[0x07]	4948	1			T2	21		T3	279		T4	16
valid_sources[0x08]	4841	1			T2	38		T3	288		T4	17
valid_sources[0x09]	4847	1			T2	38		T3	325		T4	12
valid_sources[0x0a]	5262	1			T2	21		T3	376		T4	8
valid_sources[0x0b]	4758	1			T2	38		T3	340		T4	12
valid_sources[0x0c]	4748	1			T2	29		T3	335		T4	28
valid_sources[0x0d]	5047	1			T2	30		T3	269		T4	13
valid_sources[0x0e]	4941	1			T2	27		T3	274		T4	18
valid_sources[0x0f]	4987	1			T2	35		T3	256		T4	14
valid_sources[0x10]	4858	1			T2	37		T3	283		T4	18
valid_sources[0x11]	4782	1			T2	32		T3	217		T4	15
valid_sources[0x12]	4735	1			T2	35		T3	226		T4	18
valid_sources[0x13]	4932	1			T2	22		T3	269		T4	24
valid_sources[0x14]	14255	1			T2	23		T3	348		T4	13
valid_sources[0x15]	4807	1			T2	24		T3	304		T4	28
valid_sources[0x16]	4847	1			T2	36		T3	325		T4	19
valid_sources[0x17]	4668	1			T2	33		T3	272		T4	11
valid_sources[0x18]	4854	1			T2	31		T3	210		T4	13
valid_sources[0x19]	4793	1			T2	29		T3	375		T4	16
valid_sources[0x1a]	5221	1			T2	39		T3	308		T4	18
valid_sources[0x1b]	4817	1			T2	37		T3	310		T4	13
valid_sources[0x1c]	4793	1			T2	32		T3	238		T4	17
valid_sources[0x1d]	6252	1			T2	21		T3	291		T4	18
valid_sources[0x1e]	4913	1			T2	36		T3	224		T4	19
valid_sources[0x1f]	5839	1			T2	27		T3	259		T4	13
valid_sources[0x20]	5066	1			T2	27		T3	388		T4	15
valid_sources[0x21]	4772	1			T2	25		T3	283		T4	21
valid_sources[0x22]	4941	1			T2	31		T3	258		T4	21
valid_sources[0x23]	5110	1			T2	39		T3	365		T4	18
valid_sources[0x24]	4932	1			T2	37		T3	260		T4	24
valid_sources[0x25]	4925	1			T2	29		T3	232		T4	23
valid_sources[0x26]	5002	1			T2	26		T3	370		T4	29
valid_sources[0x27]	4832	1			T2	29		T3	159		T4	16
valid_sources[0x28]	5031	1			T2	27		T3	358		T4	4
valid_sources[0x29]	5009	1			T2	24		T3	200		T4	7
valid_sources[0x2a]	5052	1			T2	20		T3	323		T4	10
valid_sources[0x2b]	4765	1			T2	25		T3	333		T4	18
valid_sources[0x2c]	4834	1			T2	41		T3	214		T4	24
valid_sources[0x2d]	4930	1			T2	34		T3	314		T4	25
valid_sources[0x2e]	5680	1			T2	41		T3	274		T4	28
valid_sources[0x2f]	4714	1			T2	22		T3	266		T4	19
valid_sources[0x30]	5005	1			T2	37		T3	334		T4	13
valid_sources[0x31]	4911	1			T2	25		T3	249		T4	29
valid_sources[0x32]	4802	1			T2	25		T3	269		T4	14
valid_sources[0x33]	5217	1			T2	24		T3	365		T4	25
valid_sources[0x34]	4871	1			T2	49		T3	343		T4	30
valid_sources[0x35]	4789	1			T2	18		T3	247		T4	15
valid_sources[0x36]	5052	1			T2	38		T3	256		T4	17
valid_sources[0x37]	4847	1			T2	20		T3	214		T4	39
valid_sources[0x38]	4764	1			T2	30		T3	353		T4	24
valid_sources[0x39]	4961	1			T2	32		T3	265		T4	14
valid_sources[0x3a]	4983	1			T2	41		T3	290		T4	37
valid_sources[0x3b]	4958	1			T2	31		T3	278		T4	18
valid_sources[0x3c]	14178	1			T2	31		T3	367		T4	19
valid_sources[0x3d]	4902	1			T2	41		T3	230		T4	20
valid_sources[0x3e]	5152	1			T2	34		T3	200		T4	19
valid_sources[0x3f]	4868	1			T2	32		T3	300		T4	29
valid_sources[0x40]	5184	1			T2	32		T3	341		T4	23
valid_sources[0x41]	4911	1			T2	43		T3	243		T4	24
valid_sources[0x42]	4790	1			T2	23		T3	312		T4	22
valid_sources[0x43]	5578	1			T2	31		T3	306		T4	10
valid_sources[0x44]	5162	1			T2	26		T3	281		T4	19
valid_sources[0x45]	4769	1			T2	26		T3	238		T4	19
valid_sources[0x46]	5007	1			T2	30		T3	363		T4	17
valid_sources[0x47]	4826	1			T2	31		T3	248		T4	19
valid_sources[0x48]	4860	1			T2	37		T3	207		T4	10
valid_sources[0x49]	4970	1			T2	27		T3	312		T4	12
valid_sources[0x4a]	4882	1			T2	30		T3	329		T4	13
valid_sources[0x4b]	28167	1			T2	34		T3	278		T4	26
valid_sources[0x4c]	5072	1			T2	22		T3	264		T4	21
valid_sources[0x4d]	4609	1			T2	34		T3	367		T4	26
valid_sources[0x4e]	4730	1			T2	43		T3	252		T4	37
valid_sources[0x4f]	4851	1			T2	30		T3	262		T4	19
valid_sources[0x50]	26862	1			T2	19		T3	186		T4	18
valid_sources[0x51]	5050	1			T2	29		T3	237		T4	34
valid_sources[0x52]	4749	1			T2	36		T3	299		T4	19
valid_sources[0x53]	4898	1			T2	41		T3	264		T4	19
valid_sources[0x54]	4940	1			T2	36		T3	246		T4	18
valid_sources[0x55]	4876	1			T2	36		T3	318		T4	23
valid_sources[0x56]	4827	1			T2	27		T3	347		T4	13
valid_sources[0x57]	5242	1			T2	45		T3	300		T4	22
valid_sources[0x58]	4658	1			T2	22		T3	316		T4	12
valid_sources[0x59]	5015	1			T2	41		T3	238		T4	12
valid_sources[0x5a]	4654	1			T2	27		T3	192		T4	22
valid_sources[0x5b]	4690	1			T2	28		T3	247		T4	24
valid_sources[0x5c]	4790	1			T2	34		T3	325		T4	8
valid_sources[0x5d]	4649	1			T2	44		T3	195		T4	17
valid_sources[0x5e]	97946	1			T2	27		T3	343		T4	14
valid_sources[0x5f]	5117	1			T2	29		T3	292		T4	27
valid_sources[0x60]	5057	1			T2	38		T3	264		T4	29
valid_sources[0x61]	5311	1			T2	38		T3	322		T4	17
valid_sources[0x62]	7869	1			T2	27		T3	280		T4	23
valid_sources[0x63]	8750	1			T2	35		T3	220		T4	32
valid_sources[0x64]	5406	1			T2	25		T3	244		T4	18
valid_sources[0x65]	4912	1			T2	26		T3	310		T4	8
valid_sources[0x66]	5070	1			T2	32		T3	360		T4	13
valid_sources[0x67]	4847	1			T2	36		T3	304		T4	21
valid_sources[0x68]	5240	1			T2	34		T3	323		T4	5
valid_sources[0x69]	4706	1			T2	32		T3	352		T4	8
valid_sources[0x6a]	5017	1			T2	29		T3	293		T4	22
valid_sources[0x6b]	4907	1			T2	36		T3	255		T4	17
valid_sources[0x6c]	4949	1			T2	26		T3	288		T4	9
valid_sources[0x6d]	4956	1			T2	25		T3	356		T4	24
valid_sources[0x6e]	5137	1			T2	29		T3	210		T4	8
valid_sources[0x6f]	5203	1			T2	24		T3	325		T4	14
valid_sources[0x70]	5000	1			T2	28		T3	294		T4	17
valid_sources[0x71]	4818	1			T2	28		T3	236		T4	15
valid_sources[0x72]	4581	1			T2	35		T3	241		T4	14
valid_sources[0x73]	5130	1			T2	27		T3	262		T4	12
valid_sources[0x74]	4896	1			T2	24		T3	331		T4	17
valid_sources[0x75]	5292	1			T2	29		T3	331		T4	29
valid_sources[0x76]	10416	1			T2	46		T3	306		T4	32
valid_sources[0x77]	4951	1			T2	38		T3	298		T4	32
valid_sources[0x78]	5151	1			T2	28		T3	355		T4	21
valid_sources[0x79]	4831	1			T2	26		T3	298		T4	19
valid_sources[0x7a]	4990	1			T2	46		T3	377		T4	23
valid_sources[0x7b]	4789	1			T2	44		T3	247		T4	18
valid_sources[0x7c]	4752	1			T2	39		T3	323		T4	17
valid_sources[0x7d]	11219	1			T2	32		T3	212		T4	12
valid_sources[0x7e]	8730	1			T2	29		T3	281		T4	22
valid_sources[0x7f]	4758	1			T2	38		T3	216		T4	37
valid_sources[0x80]	4927	1			T2	34		T3	280		T4	20

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

131491

1

T1

358

T2

2074

T3

2181

values[0x0]

all_enables

biggest_size

55302

1

T1

220

T2

591

T3

587

values[0x1]

all_enables

biggest_size

48484

1

T1

196

T2

460

T3

479