Unified Coverage Report :: Module :: keymgr_dpe_csr_assert_fpv

Module : keymgr_dpe_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_dpe_csr_assert_0/keymgr_dpe_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_dpe_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_dpe_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_dpe_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	22	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12040154	8628	0	0
intr_enable_rd_A	12040154	2711	0	0
key_version_rd_A	12040154	2349	0	0
reseed_interval_regwen_rd_A	12040154	970	0	0
salt_0_rd_A	12040154	2258	0	0
salt_1_rd_A	12040154	2375	0	0
salt_2_rd_A	12040154	2282	0	0
salt_3_rd_A	12040154	2393	0	0
salt_4_rd_A	12040154	2312	0	0
salt_5_rd_A	12040154	2507	0	0
salt_6_rd_A	12040154	2369	0	0
salt_7_rd_A	12040154	2230	0	0
sideload_clear_rd_A	12040154	2212	0	0
slot_policy_rd_A	12040154	3166	0	0
sw_binding_0_rd_A	12040154	2271	0	0
sw_binding_1_rd_A	12040154	2331	0	0
sw_binding_2_rd_A	12040154	2428	0	0
sw_binding_3_rd_A	12040154	2186	0	0
sw_binding_4_rd_A	12040154	2243	0	0
sw_binding_5_rd_A	12040154	2462	0	0
sw_binding_6_rd_A	12040154	2340	0	0
sw_binding_7_rd_A	12040154	2402	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12040154	8628	0	0
T19	3074	207	0	0
T21	2051	134	0	0
T26	4687	469	0	0
T32	8817	391	0	0
T33	0	218	0	0
T54	1864	1	0	0
T56	9419	0	0	0
T57	0	18	0	0
T59	7575	0	0	0
T60	1625	0	0	0
T61	1344	0	0	0
T86	2775	16	0	0
T87	0	1	0	0
T88	0	16	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12040154	2711	0	0
T30	1322	6	0	0
T33	5903	0	0	0
T38	28736	179	0	0
T54	1864	13	0	0
T61	1344	13	0	0
T62	812	7	0	0
T63	1225	0	0	0
T77	4813	25	0	0
T79	4403	7	0	0
T87	0	8	0	0
T89	1190	13	0	0
T90	0	6	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12040154	2349	0	0
T28	0	34	0	0
T30	1322	4	0	0
T33	5903	0	0	0
T38	28736	137	0	0
T54	1864	6	0	0
T58	0	12	0	0
T77	4813	49	0	0
T79	4403	21	0	0
T87	1127	0	0	0
T89	1190	0	0	0
T90	0	6	0	0
T91	0	165	0	0
T92	0	13	0	0
T93	1130	0	0	0
T94	21176	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12040154	970	0	0
T33	5903	0	0	0
T38	28736	49	0	0
T54	1864	2	0	0
T58	0	15	0	0
T77	4813	77	0	0
T79	4403	20	0	0
T87	1127	10	0	0
T89	1190	0	0	0
T90	0	8	0	0
T91	0	47	0	0
T92	0	9	0	0
T93	1130	0	0	0
T94	21176	0	0	0
T95	0	21	0	0
T96	4117	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12040154	2258	0	0
T28	0	27	0	0
T30	1322	3	0	0
T33	5903	0	0	0
T38	28736	214	0	0
T54	1864	5	0	0
T58	0	9	0	0
T77	4813	10	0	0
T79	4403	19	0	0
T87	1127	1	0	0
T89	1190	0	0	0
T90	0	10	0	0
T91	0	143	0	0
T93	1130	0	0	0
T94	21176	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12040154	2375	0	0
T28	0	46	0	0
T33	5903	0	0	0
T38	28736	198	0	0
T54	1864	18	0	0
T58	0	6	0	0
T77	4813	36	0	0
T79	4403	17	0	0
T87	1127	2	0	0
T89	1190	0	0	0
T90	0	10	0	0
T91	0	178	0	0
T92	0	7	0	0
T93	1130	0	0	0
T94	21176	0	0	0
T96	4117	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12040154	2282	0	0
T28	0	41	0	0
T30	1322	6	0	0
T33	5903	0	0	0
T38	28736	184	0	0
T54	1864	11	0	0
T58	0	5	0	0
T77	4813	14	0	0
T79	4403	6	0	0
T87	1127	6	0	0
T89	1190	0	0	0
T90	0	12	0	0
T91	0	158	0	0
T93	1130	0	0	0
T94	21176	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12040154	2393	0	0
T28	0	17	0	0
T30	1322	6	0	0
T33	5903	0	0	0
T38	28736	168	0	0
T54	1864	12	0	0
T58	0	9	0	0
T77	4813	3	0	0
T79	4403	29	0	0
T87	1127	4	0	0
T89	1190	0	0	0
T90	0	4	0	0
T91	0	181	0	0
T93	1130	0	0	0
T94	21176	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12040154	2312	0	0
T28	0	46	0	0
T30	1322	5	0	0
T33	5903	0	0	0
T38	28736	168	0	0
T54	1864	8	0	0
T58	0	4	0	0
T77	4813	27	0	0
T79	4403	9	0	0
T87	1127	0	0	0
T89	1190	0	0	0
T90	0	22	0	0
T91	0	114	0	0
T92	0	7	0	0
T93	1130	0	0	0
T94	21176	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12040154	2507	0	0
T28	0	43	0	0
T30	1322	2	0	0
T33	5903	0	0	0
T38	28736	162	0	0
T54	1864	15	0	0
T58	0	11	0	0
T77	4813	30	0	0
T79	4403	20	0	0
T87	1127	2	0	0
T89	1190	0	0	0
T90	0	3	0	0
T91	0	167	0	0
T93	1130	0	0	0
T94	21176	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12040154	2369	0	0
T28	0	35	0	0
T33	5903	0	0	0
T38	28736	148	0	0
T54	1864	15	0	0
T58	0	7	0	0
T77	4813	21	0	0
T79	4403	9	0	0
T87	1127	4	0	0
T89	1190	0	0	0
T90	0	9	0	0
T91	0	185	0	0
T92	0	14	0	0
T93	1130	0	0	0
T94	21176	0	0	0
T96	4117	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12040154	2230	0	0
T28	0	39	0	0
T30	1322	1	0	0
T33	5903	0	0	0
T38	28736	159	0	0
T54	1864	4	0	0
T58	0	12	0	0
T77	4813	42	0	0
T79	4403	16	0	0
T87	1127	0	0	0
T89	1190	0	0	0
T90	0	9	0	0
T91	0	139	0	0
T92	0	9	0	0
T93	1130	0	0	0
T94	21176	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12040154	2212	0	0
T28	0	31	0	0
T30	1322	6	0	0
T33	5903	0	0	0
T38	28736	123	0	0
T54	1864	5	0	0
T58	0	12	0	0
T79	4403	11	0	0
T87	1127	7	0	0
T89	1190	0	0	0
T90	0	26	0	0
T91	0	152	0	0
T92	0	7	0	0
T93	1130	0	0	0
T94	21176	0	0	0
T96	4117	0	0	0

slot_policy_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12040154	3166	0	0
T28	0	69	0	0
T30	1322	13	0	0
T33	5903	0	0	0
T38	28736	291	0	0
T54	1864	6	0	0
T58	0	3	0	0
T77	4813	2	0	0
T79	4403	11	0	0
T87	1127	2	0	0
T89	1190	0	0	0
T90	0	13	0	0
T91	0	297	0	0
T93	1130	0	0	0
T94	21176	0	0	0

sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12040154	2271	0	0
T28	0	41	0	0
T30	1322	2	0	0
T33	5903	0	0	0
T38	28736	166	0	0
T54	1864	10	0	0
T58	0	7	0	0
T77	4813	37	0	0
T79	4403	24	0	0
T87	1127	7	0	0
T89	1190	0	0	0
T90	0	16	0	0
T91	0	136	0	0
T93	1130	0	0	0
T94	21176	0	0	0

sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12040154	2331	0	0
T28	0	54	0	0
T30	1322	6	0	0
T33	5903	0	0	0
T38	28736	167	0	0
T54	1864	14	0	0
T58	0	7	0	0
T77	4813	28	0	0
T79	4403	15	0	0
T87	1127	3	0	0
T89	1190	0	0	0
T90	0	3	0	0
T91	0	147	0	0
T93	1130	0	0	0
T94	21176	0	0	0

sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12040154	2428	0	0
T28	0	33	0	0
T30	1322	5	0	0
T33	5903	0	0	0
T38	28736	171	0	0
T54	1864	9	0	0
T58	0	11	0	0
T77	4813	13	0	0
T79	4403	1	0	0
T87	1127	0	0	0
T89	1190	0	0	0
T90	0	15	0	0
T91	0	177	0	0
T92	0	9	0	0
T93	1130	0	0	0
T94	21176	0	0	0

sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12040154	2186	0	0
T28	0	40	0	0
T30	1322	5	0	0
T33	5903	0	0	0
T38	28736	145	0	0
T54	1864	18	0	0
T58	0	14	0	0
T77	4813	32	0	0
T79	4403	24	0	0
T87	1127	7	0	0
T89	1190	0	0	0
T90	0	2	0	0
T91	0	166	0	0
T93	1130	0	0	0
T94	21176	0	0	0

sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12040154	2243	0	0
T28	0	44	0	0
T30	1322	6	0	0
T33	5903	0	0	0
T38	28736	180	0	0
T54	1864	3	0	0
T58	0	8	0	0
T77	4813	1	0	0
T79	4403	14	0	0
T87	1127	5	0	0
T89	1190	0	0	0
T90	0	13	0	0
T91	0	129	0	0
T93	1130	0	0	0
T94	21176	0	0	0

sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12040154	2462	0	0
T28	0	32	0	0
T30	1322	3	0	0
T33	5903	0	0	0
T38	28736	186	0	0
T54	1864	6	0	0
T58	0	13	0	0
T77	4813	46	0	0
T79	4403	17	0	0
T87	1127	6	0	0
T89	1190	0	0	0
T90	0	12	0	0
T91	0	153	0	0
T93	1130	0	0	0
T94	21176	0	0	0

sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12040154	2340	0	0
T28	0	46	0	0
T30	1322	1	0	0
T33	5903	0	0	0
T38	28736	176	0	0
T54	1864	17	0	0
T58	0	16	0	0
T77	4813	50	0	0
T79	4403	17	0	0
T87	1127	6	0	0
T89	1190	0	0	0
T90	0	5	0	0
T91	0	147	0	0
T93	1130	0	0	0
T94	21176	0	0	0

sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12040154	2402	0	0
T28	0	45	0	0
T30	1322	4	0	0
T33	5903	0	0	0
T38	28736	146	0	0
T54	1864	10	0	0
T58	0	4	0	0
T77	4813	21	0	0
T79	4403	43	0	0
T87	1127	7	0	0
T89	1190	0	0	0
T90	0	14	0	0
T91	0	168	0	0
T93	1130	0	0	0
T94	21176	0	0	0