Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1328653	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

248509

1

T1

3027

T2

2698

T3

2812

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1435741	1			T1	5202		T2	22197		T3	136922
values[0x0]	70189	1			T1	710		T2	630		T3	671
values[0x1]	71232	1			T1	743		T2	717		T3	678

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	901715	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

675447

1

T1

3992

T2

9591

T3

47651

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5397	1			T1	30		T3	524		T4	4
valid_sources[0x01]	5348	1			T1	42		T3	545		T7	22
valid_sources[0x02]	5096	1			T1	26		T3	464		T7	46
valid_sources[0x03]	5267	1			T1	22		T3	556		T4	5
valid_sources[0x04]	5152	1			T1	31		T3	553		T4	11
valid_sources[0x05]	5566	1			T1	19		T3	536		T7	10
valid_sources[0x06]	7088	1			T1	33		T3	540		T8	101
valid_sources[0x07]	5415	1			T1	28		T3	577		T4	9
valid_sources[0x08]	5191	1			T1	13		T3	535		T4	1
valid_sources[0x09]	5505	1			T1	36		T3	542		T7	27
valid_sources[0x0a]	21453	1			T1	26		T3	540		T4	8
valid_sources[0x0b]	5463	1			T1	30		T3	511		T7	41
valid_sources[0x0c]	5485	1			T1	25		T3	526		T4	9
valid_sources[0x0d]	7367	1			T1	37		T3	501		T7	41
valid_sources[0x0e]	5199	1			T1	25		T3	477		T4	9
valid_sources[0x0f]	5590	1			T1	13		T3	548		T4	5
valid_sources[0x10]	5111	1			T1	27		T3	580		T4	2
valid_sources[0x11]	4938	1			T1	22		T3	512		T4	1
valid_sources[0x12]	5397	1			T1	24		T3	545		T4	14
valid_sources[0x13]	5276	1			T1	29		T3	497		T7	13
valid_sources[0x14]	5541	1			T1	28		T3	619		T7	19
valid_sources[0x15]	5192	1			T1	21		T3	567		T4	13
valid_sources[0x16]	7169	1			T1	17		T3	544		T4	14
valid_sources[0x17]	5476	1			T1	12		T3	566		T8	153
valid_sources[0x18]	5673	1			T1	25		T3	504		T7	47
valid_sources[0x19]	5481	1			T1	27		T3	521		T4	9
valid_sources[0x1a]	5402	1			T1	34		T3	486		T7	4
valid_sources[0x1b]	5070	1			T1	33		T3	540		T7	21
valid_sources[0x1c]	5457	1			T1	31		T3	567		T4	6
valid_sources[0x1d]	5478	1			T1	25		T3	523		T7	23
valid_sources[0x1e]	5145	1			T1	22		T3	463		T7	3
valid_sources[0x1f]	5400	1			T1	28		T3	523		T7	34
valid_sources[0x20]	5278	1			T1	26		T3	545		T4	6
valid_sources[0x21]	5125	1			T1	20		T3	555		T4	5
valid_sources[0x22]	5709	1			T1	31		T3	534		T7	71
valid_sources[0x23]	5296	1			T1	20		T3	534		T4	1
valid_sources[0x24]	5716	1			T1	28		T3	558		T4	6
valid_sources[0x25]	5486	1			T1	27		T3	582		T7	2
valid_sources[0x26]	5510	1			T1	34		T3	597		T7	30
valid_sources[0x27]	5324	1			T1	25		T3	546		T4	18
valid_sources[0x28]	5298	1			T1	31		T3	572		T4	8
valid_sources[0x29]	5309	1			T1	17		T3	651		T4	24
valid_sources[0x2a]	5481	1			T1	26		T3	532		T7	18
valid_sources[0x2b]	5382	1			T1	30		T3	534		T4	22
valid_sources[0x2c]	5532	1			T1	32		T3	587		T4	12
valid_sources[0x2d]	5663	1			T1	27		T3	532		T4	1
valid_sources[0x2e]	5170	1			T1	39		T3	612		T4	22
valid_sources[0x2f]	6684	1			T1	24		T2	1335		T3	501
valid_sources[0x30]	5389	1			T1	27		T3	523		T4	21
valid_sources[0x31]	5480	1			T1	35		T3	497		T4	13
valid_sources[0x32]	5326	1			T1	21		T3	509		T7	51
valid_sources[0x33]	5370	1			T1	18		T3	519		T7	12
valid_sources[0x34]	5411	1			T1	19		T3	520		T7	8
valid_sources[0x35]	5351	1			T1	24		T3	541		T7	13
valid_sources[0x36]	5123	1			T1	29		T3	515		T7	9
valid_sources[0x37]	5576	1			T1	35		T3	495		T4	42
valid_sources[0x38]	5285	1			T1	24		T3	548		T7	33
valid_sources[0x39]	5297	1			T1	25		T3	574		T4	5
valid_sources[0x3a]	5535	1			T1	29		T3	506		T7	48
valid_sources[0x3b]	5361	1			T1	29		T3	551		T4	4
valid_sources[0x3c]	5784	1			T1	25		T3	555		T4	6
valid_sources[0x3d]	5227	1			T1	31		T3	525		T7	17
valid_sources[0x3e]	5141	1			T1	23		T3	549		T4	4
valid_sources[0x3f]	5472	1			T1	26		T3	555		T7	12
valid_sources[0x40]	5226	1			T1	23		T3	556		T4	8
valid_sources[0x41]	5316	1			T1	35		T3	530		T4	9
valid_sources[0x42]	5694	1			T1	33		T3	569		T4	7
valid_sources[0x43]	5336	1			T1	22		T3	550		T4	1
valid_sources[0x44]	5414	1			T1	34		T3	602		T7	70
valid_sources[0x45]	5818	1			T1	27		T3	532		T7	21
valid_sources[0x46]	5488	1			T1	40		T3	615		T4	1
valid_sources[0x47]	5232	1			T1	34		T3	510		T4	19
valid_sources[0x48]	5333	1			T1	30		T3	495		T7	31
valid_sources[0x49]	5155	1			T1	33		T3	477		T7	11
valid_sources[0x4a]	5098	1			T1	22		T3	521		T7	24
valid_sources[0x4b]	5263	1			T1	31		T3	591		T4	13
valid_sources[0x4c]	4947	1			T1	24		T3	535		T4	8
valid_sources[0x4d]	5343	1			T1	19		T3	537		T4	1
valid_sources[0x4e]	5154	1			T1	22		T3	544		T7	1
valid_sources[0x4f]	5457	1			T1	26		T3	501		T4	1
valid_sources[0x50]	5429	1			T1	22		T3	517		T7	34
valid_sources[0x51]	5382	1			T1	31		T3	486		T4	5
valid_sources[0x52]	5303	1			T1	26		T3	550		T4	16
valid_sources[0x53]	5275	1			T1	24		T3	493		T7	17
valid_sources[0x54]	5328	1			T1	20		T3	560		T7	2
valid_sources[0x55]	11330	1			T1	19		T3	583		T7	24
valid_sources[0x56]	5268	1			T1	24		T3	506		T4	10
valid_sources[0x57]	5452	1			T1	28		T3	546		T4	6
valid_sources[0x58]	5198	1			T1	10		T3	545		T7	16
valid_sources[0x59]	103278	1			T1	33		T3	545		T8	63
valid_sources[0x5a]	5333	1			T1	23		T3	513		T4	10
valid_sources[0x5b]	5343	1			T1	19		T3	538		T4	12
valid_sources[0x5c]	5287	1			T1	22		T3	541		T7	28
valid_sources[0x5d]	5505	1			T1	35		T3	527		T4	9
valid_sources[0x5e]	5031	1			T1	19		T3	555		T4	3
valid_sources[0x5f]	5330	1			T1	20		T3	531		T7	15
valid_sources[0x60]	5724	1			T1	29		T3	526		T7	9
valid_sources[0x61]	5360	1			T1	24		T3	579		T4	12
valid_sources[0x62]	5573	1			T1	19		T3	552		T7	55
valid_sources[0x63]	5352	1			T1	30		T3	536		T7	28
valid_sources[0x64]	5370	1			T1	21		T3	576		T7	30
valid_sources[0x65]	5300	1			T1	20		T3	545		T4	2
valid_sources[0x66]	5352	1			T1	22		T3	511		T7	28
valid_sources[0x67]	5469	1			T1	22		T3	524		T7	46
valid_sources[0x68]	5292	1			T1	19		T3	566		T7	13
valid_sources[0x69]	5083	1			T1	24		T3	511		T4	6
valid_sources[0x6a]	5255	1			T1	19		T3	514		T4	4
valid_sources[0x6b]	5677	1			T1	29		T3	512		T7	25
valid_sources[0x6c]	5511	1			T1	18		T3	580		T7	26
valid_sources[0x6d]	5189	1			T1	38		T3	528		T7	28
valid_sources[0x6e]	5160	1			T1	26		T3	568		T7	18
valid_sources[0x6f]	5729	1			T1	37		T3	603		T7	28
valid_sources[0x70]	5307	1			T1	18		T3	557		T7	39
valid_sources[0x71]	5315	1			T1	27		T3	536		T4	3
valid_sources[0x72]	50005	1			T1	33		T3	539		T7	21
valid_sources[0x73]	5158	1			T1	24		T3	555		T7	4
valid_sources[0x74]	5333	1			T1	34		T3	515		T4	3
valid_sources[0x75]	5074	1			T1	27		T3	568		T4	8
valid_sources[0x76]	5520	1			T1	27		T3	505		T7	44
valid_sources[0x77]	5758	1			T1	23		T3	588		T4	7
valid_sources[0x78]	5627	1			T1	22		T3	609		T4	16
valid_sources[0x79]	5292	1			T1	26		T3	482		T7	52
valid_sources[0x7a]	5379	1			T1	21		T3	605		T7	13
valid_sources[0x7b]	5639	1			T1	26		T3	539		T4	7
valid_sources[0x7c]	5280	1			T1	31		T3	520		T4	13
valid_sources[0x7d]	5288	1			T1	14		T3	507		T7	29
valid_sources[0x7e]	5597	1			T1	21		T3	552		T4	11
valid_sources[0x7f]	5406	1			T1	16		T3	597		T7	14
valid_sources[0x80]	5315	1			T1	30		T3	566		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

140243

1

T1

2034

T2

1781

T3

1878

values[0x0]

all_enables

biggest_size

57648

1

T1

553

T2

479

T3

517

values[0x1]

all_enables

biggest_size

50618

1

T1

440

T2

438

T3

417