Unified Coverage Report :: Module :: keymgr_dpe_csr_assert_fpv

Module : keymgr_dpe_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_dpe_csr_assert_0/keymgr_dpe_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_dpe_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_dpe_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.32	100.00	79.89	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_dpe_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	22	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11490738	8265	0	0
intr_enable_rd_A	11490738	3350	0	0
key_version_rd_A	11490738	3370	0	0
reseed_interval_regwen_rd_A	11490738	1761	0	0
salt_0_rd_A	11490738	3308	0	0
salt_1_rd_A	11490738	3307	0	0
salt_2_rd_A	11490738	3299	0	0
salt_3_rd_A	11490738	3238	0	0
salt_4_rd_A	11490738	3275	0	0
salt_5_rd_A	11490738	3262	0	0
salt_6_rd_A	11490738	3213	0	0
salt_7_rd_A	11490738	3251	0	0
sideload_clear_rd_A	11490738	3335	0	0
slot_policy_rd_A	11490738	4140	0	0
sw_binding_0_rd_A	11490738	3373	0	0
sw_binding_1_rd_A	11490738	3205	0	0
sw_binding_2_rd_A	11490738	3433	0	0
sw_binding_3_rd_A	11490738	3230	0	0
sw_binding_4_rd_A	11490738	3325	0	0
sw_binding_5_rd_A	11490738	3212	0	0
sw_binding_6_rd_A	11490738	3276	0	0
sw_binding_7_rd_A	11490738	3388	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11490738	8265	0	0
T18	20160	4	0	0
T19	2238	16	0	0
T20	5379	117	0	0
T30	8127	310	0	0
T31	0	2	0	0
T32	0	3	0	0
T33	0	308	0	0
T58	2157	7	0	0
T63	0	2	0	0
T85	1211	0	0	0
T86	6556	0	0	0
T90	0	6	0	0
T91	2119	0	0	0
T92	3435	0	0	0
T93	850	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11490738	3350	0	0
T34	25845	166	0	0
T35	4401	4	0	0
T40	1187	32	0	0
T57	8137	0	0	0
T59	24859	172	0	0
T77	2623	5	0	0
T78	1560	5	0	0
T80	4773	6	0	0
T81	0	156	0	0
T94	1029	27	0	0
T95	1230	14	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11490738	3370	0	0
T30	0	3	0	0
T34	25845	189	0	0
T35	4401	10	0	0
T57	8137	0	0	0
T58	0	5	0	0
T59	24859	164	0	0
T77	2623	6	0	0
T78	1560	6	0	0
T80	4773	33	0	0
T81	26732	197	0	0
T82	8538	13	0	0
T83	12561	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11490738	1761	0	0
T30	0	2	0	0
T34	25845	34	0	0
T35	4401	29	0	0
T57	8137	0	0	0
T58	0	5	0	0
T59	24859	16	0	0
T63	0	1	0	0
T77	2623	7	0	0
T80	4773	25	0	0
T81	26732	221	0	0
T82	8538	46	0	0
T83	12561	0	0	0
T84	1155	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11490738	3308	0	0
T19	2238	9	0	0
T34	25845	152	0	0
T35	4401	15	0	0
T57	8137	0	0	0
T58	0	4	0	0
T59	24859	157	0	0
T77	2623	5	0	0
T78	1560	1	0	0
T80	4773	18	0	0
T81	26732	200	0	0
T82	8538	71	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11490738	3307	0	0
T20	5379	2	0	0
T34	25845	167	0	0
T35	4401	1	0	0
T57	8137	0	0	0
T58	0	16	0	0
T59	24859	194	0	0
T77	2623	7	0	0
T78	1560	9	0	0
T80	4773	41	0	0
T81	26732	187	0	0
T82	8538	61	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11490738	3299	0	0
T31	0	5	0	0
T34	25845	146	0	0
T35	4401	32	0	0
T57	8137	0	0	0
T58	0	7	0	0
T59	24859	178	0	0
T77	2623	6	0	0
T78	1560	4	0	0
T80	4773	14	0	0
T81	26732	161	0	0
T82	8538	17	0	0
T83	12561	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11490738	3238	0	0
T19	2238	6	0	0
T34	25845	159	0	0
T35	4401	19	0	0
T57	8137	0	0	0
T58	0	23	0	0
T59	24859	150	0	0
T77	2623	6	0	0
T78	1560	3	0	0
T80	4773	7	0	0
T81	26732	160	0	0
T82	8538	28	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11490738	3275	0	0
T19	2238	7	0	0
T34	25845	169	0	0
T35	4401	9	0	0
T57	8137	0	0	0
T58	0	10	0	0
T59	24859	180	0	0
T77	2623	8	0	0
T78	1560	5	0	0
T80	4773	15	0	0
T81	26732	218	0	0
T82	8538	55	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11490738	3262	0	0
T19	2238	1	0	0
T20	5379	3	0	0
T34	25845	145	0	0
T35	4401	11	0	0
T57	8137	0	0	0
T59	24859	142	0	0
T77	2623	8	0	0
T78	1560	4	0	0
T80	4773	32	0	0
T81	26732	215	0	0
T82	0	16	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11490738	3213	0	0
T20	5379	13	0	0
T34	25845	175	0	0
T35	4401	5	0	0
T57	8137	0	0	0
T58	0	9	0	0
T59	24859	205	0	0
T77	2623	6	0	0
T78	1560	4	0	0
T80	4773	35	0	0
T81	26732	200	0	0
T82	8538	17	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11490738	3251	0	0
T19	2238	10	0	0
T20	5379	5	0	0
T34	25845	159	0	0
T35	4401	15	0	0
T57	8137	0	0	0
T59	24859	158	0	0
T77	2623	3	0	0
T78	1560	3	0	0
T80	4773	20	0	0
T81	26732	255	0	0
T82	0	21	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11490738	3335	0	0
T19	2238	7	0	0
T20	5379	2	0	0
T34	25845	163	0	0
T35	4401	38	0	0
T57	8137	0	0	0
T59	24859	165	0	0
T77	2623	7	0	0
T78	1560	4	0	0
T80	4773	21	0	0
T81	26732	210	0	0
T82	0	55	0	0

slot_policy_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11490738	4140	0	0
T30	0	8	0	0
T34	25845	288	0	0
T35	4401	2	0	0
T57	8137	0	0	0
T58	0	9	0	0
T59	24859	287	0	0
T77	2623	11	0	0
T78	1560	20	0	0
T80	4773	14	0	0
T81	26732	190	0	0
T82	8538	66	0	0
T83	12561	0	0	0

sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11490738	3373	0	0
T19	2238	18	0	0
T34	25845	146	0	0
T35	4401	9	0	0
T57	8137	0	0	0
T58	0	9	0	0
T59	24859	130	0	0
T77	2623	6	0	0
T78	1560	4	0	0
T80	4773	28	0	0
T81	26732	221	0	0
T82	8538	16	0	0

sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11490738	3205	0	0
T19	2238	3	0	0
T34	25845	172	0	0
T35	4401	31	0	0
T57	8137	0	0	0
T58	0	12	0	0
T59	24859	149	0	0
T77	2623	4	0	0
T78	1560	4	0	0
T80	4773	15	0	0
T81	26732	181	0	0
T82	8538	26	0	0

sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11490738	3433	0	0
T19	2238	10	0	0
T34	25845	165	0	0
T35	4401	18	0	0
T57	8137	0	0	0
T58	0	13	0	0
T59	24859	161	0	0
T77	2623	10	0	0
T78	1560	4	0	0
T80	4773	4	0	0
T81	26732	200	0	0
T82	8538	31	0	0

sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11490738	3230	0	0
T19	2238	3	0	0
T20	5379	2	0	0
T34	25845	156	0	0
T35	4401	38	0	0
T57	8137	0	0	0
T59	24859	143	0	0
T77	2623	9	0	0
T78	1560	5	0	0
T80	4773	20	0	0
T81	26732	186	0	0
T82	0	50	0	0

sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11490738	3325	0	0
T19	2238	1	0	0
T34	25845	157	0	0
T35	4401	23	0	0
T57	8137	0	0	0
T58	0	11	0	0
T59	24859	158	0	0
T77	2623	7	0	0
T78	1560	3	0	0
T80	4773	3	0	0
T81	26732	193	0	0
T82	8538	56	0	0

sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11490738	3212	0	0
T19	2238	6	0	0
T30	0	3	0	0
T34	25845	150	0	0
T35	4401	13	0	0
T57	8137	0	0	0
T58	0	12	0	0
T59	24859	157	0	0
T77	2623	1	0	0
T80	4773	20	0	0
T81	26732	149	0	0
T82	8538	44	0	0
T83	12561	0	0	0

sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11490738	3276	0	0
T19	2238	3	0	0
T34	25845	195	0	0
T35	4401	13	0	0
T57	8137	0	0	0
T58	0	11	0	0
T59	24859	163	0	0
T77	2623	7	0	0
T78	1560	1	0	0
T80	4773	14	0	0
T81	26732	154	0	0
T82	8538	31	0	0

sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11490738	3388	0	0
T20	5379	8	0	0
T30	0	4	0	0
T34	25845	155	0	0
T57	8137	0	0	0
T58	0	5	0	0
T59	24859	165	0	0
T77	2623	10	0	0
T78	1560	3	0	0
T80	4773	30	0	0
T81	26732	189	0	0
T82	8538	44	0	0
T83	12561	0	0	0