Unified Coverage Report :: Group :: keymgr_dpe_env_pkg::keymgr_dpe_sw_input_cg_wrap::keymgr_dpe_sw_input_cg

Group : keymgr_dpe_env_pkg::keymgr_dpe_sw_input_cg_wrap::keymgr_dpe_sw_input_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	7.47	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_dpe_env_0.1/keymgr_dpe_env_cov.sv

19 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
salt_1	0.00	1	100	1	64	64
salt_2	0.00	1	100	1	64	64
salt_3	0.00	1	100	1	64	64
salt_4	0.00	1	100	1	64	64
salt_5	0.00	1	100	1	64	64
salt_6	0.00	1	100	1	64	64
salt_7	0.00	1	100	1	64	64
sw_binding_1	0.00	1	100	1	64	64
sw_binding_2	0.00	1	100	1	64	64
sw_binding_3	0.00	1	100	1	64	64
sw_binding_4	0.00	1	100	1	64	64
sw_binding_5	0.00	1	100	1	64	64
sw_binding_6	0.00	1	100	1	64	64
sw_binding_7	0.00	1	100	1	64	64
key_version	3.06	1	100	1	64	64
max_key_ver_shadowed	3.06	1	100	1	64	64
start	3.06	1	100	1	64	64
salt_0	66.33	1	100	1	64	64
sw_binding_0	66.33	1	100	1	64	64

---

Group Instance : salt_1

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance salt_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance salt_1

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance salt_1

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : salt_2

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance salt_2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance salt_2

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance salt_2

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : salt_3

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance salt_3

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance salt_3

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance salt_3

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : salt_4

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance salt_4

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance salt_4

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance salt_4

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : salt_5

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance salt_5

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance salt_5

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance salt_5

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : salt_6

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance salt_6

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance salt_6

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance salt_6

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : salt_7

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance salt_7

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance salt_7

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance salt_7

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : sw_binding_1

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance sw_binding_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance sw_binding_1

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance sw_binding_1

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : sw_binding_2

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance sw_binding_2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance sw_binding_2

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance sw_binding_2

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : sw_binding_3

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance sw_binding_3

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance sw_binding_3

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance sw_binding_3

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : sw_binding_4

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance sw_binding_4

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance sw_binding_4

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance sw_binding_4

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : sw_binding_5

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance sw_binding_5

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance sw_binding_5

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance sw_binding_5

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : sw_binding_6

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance sw_binding_6

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance sw_binding_6

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance sw_binding_6

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : sw_binding_7

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance sw_binding_7

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance sw_binding_7

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance sw_binding_7

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : key_version

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
3.06	1	100	1	64	64

---

Summary for Group Instance key_version

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	32	2	5.88
Crosses	64	63	1	1.56

Variables for Group Instance key_version

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	1	1	50.00	100	1	1	2
sw_input_cp	32	31	1	3.12	100	1	1	32

Crosses for Group Instance key_version

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	63	1	1.56	100	1	1	0

---

Group Instance : max_key_ver_shadowed

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
3.06	1	100	1	64	64

---

Summary for Group Instance max_key_ver_shadowed

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	32	2	5.88
Crosses	64	63	1	1.56

Variables for Group Instance max_key_ver_shadowed

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	1	1	50.00	100	1	1	2
sw_input_cp	32	31	1	3.12	100	1	1	32

Crosses for Group Instance max_key_ver_shadowed

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	63	1	1.56	100	1	1	0

---

Group Instance : start

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
3.06	1	100	1	64	64

---

Summary for Group Instance start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	32	2	5.88
Crosses	64	63	1	1.56

Variables for Group Instance start

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	1	1	50.00	100	1	1	2
sw_input_cp	32	31	1	3.12	100	1	1	32

Crosses for Group Instance start

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	63	1	1.56	100	1	1	0

---

Group Instance : salt_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
66.33	1	100	1	64	64

---

Summary for Group Instance salt_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	1	33	97.06
Crosses	64	32	32	50.00

Variables for Group Instance salt_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	1	1	50.00	100	1	1	2
sw_input_cp	32	0	32	100.00	100	1	1	32

Crosses for Group Instance salt_0

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	32	32	50.00	100	1	1	0

---

Group Instance : sw_binding_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
66.33	1	100	1	64	64

---

Summary for Group Instance sw_binding_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	1	33	97.06
Crosses	64	32	32	50.00

Variables for Group Instance sw_binding_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	1	1	50.00	100	1	1	2
sw_input_cp	32	0	32	100.00	100	1	1	32

Crosses for Group Instance sw_binding_0

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	32	32	50.00	100	1	1	0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10254

1

T2

222

T3

188

T4

222

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	31	1	3.12

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	--	--	31

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0:134217727]

10254

1

T2

222

T3

188

T4

222

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	63	1	1.56	63

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Element holes

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	*	--	--	62

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727]]	[auto[1]]	0	1	1

Covered bins

sw_input_cp

regwen_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0:134217727]

auto[0]

10254

1

T2

222

T3

188

T4

222

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

3282

1

T2

70

T3

74

T4

64

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	31	1	3.12

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	--	--	31

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0:134217727]

3282

1

T2

70

T3

74

T4

64

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	63	1	1.56	63

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Element holes

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	*	--	--	62

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727]]	[auto[0]]	0	1	1

Covered bins

sw_input_cp

regwen_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0:134217727]

auto[1]

3282

1

T2

70

T3

74

T4

64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9574

1

T2

209

T3

189

T4

201

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	31	1	3.12

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	--	--	31

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0:134217727]

9574

1

T2

209

T3

189

T4

201

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	63	1	1.56	63

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Element holes

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	*	--	--	62

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727]]	[auto[1]]	0	1	1

Covered bins

sw_input_cp

regwen_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0:134217727]

auto[0]

9574

1

T2

209

T3

189

T4

201

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6872

1

T2

146

T3

130

T4

149

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	201	1			T2	5		T3	3		T4	2
auto[134217728:268435455]	184	1			T2	6		T3	2		T4	6
auto[268435456:402653183]	212	1			T2	5		T3	3		T4	2
auto[402653184:536870911]	218	1			T2	7		T3	1		T4	4
auto[536870912:671088639]	214	1			T2	5		T3	5		T4	4
auto[671088640:805306367]	213	1			T2	4		T3	7		T4	2
auto[805306368:939524095]	222	1			T2	2		T3	6		T4	4
auto[939524096:1073741823]	210	1			T2	5		T3	1		T4	4
auto[1073741824:1207959551]	221	1			T2	2		T3	6		T4	5
auto[1207959552:1342177279]	209	1			T2	4		T3	3		T4	5
auto[1342177280:1476395007]	202	1			T2	3		T3	1		T4	2
auto[1476395008:1610612735]	211	1			T2	7		T3	5		T4	5
auto[1610612736:1744830463]	227	1			T2	4		T3	4		T4	2
auto[1744830464:1879048191]	196	1			T2	3		T3	8		T4	2
auto[1879048192:2013265919]	207	1			T2	5		T3	2		T4	4
auto[2013265920:2147483647]	215	1			T2	4		T3	3		T4	5
auto[2147483648:2281701375]	203	1			T2	3		T3	5		T4	3
auto[2281701376:2415919103]	243	1			T2	4		T3	3		T4	11
auto[2415919104:2550136831]	206	1			T2	6		T3	4		T4	2
auto[2550136832:2684354559]	210	1			T2	6		T3	1		T4	3
auto[2684354560:2818572287]	210	1			T2	5		T3	3		T4	4
auto[2818572288:2952790015]	217	1			T2	3		T3	4		T4	5
auto[2952790016:3087007743]	204	1			T2	3		T3	5		T4	2
auto[3087007744:3221225471]	237	1			T2	4		T3	5		T4	10
auto[3221225472:3355443199]	213	1			T2	5		T3	7		T4	7
auto[3355443200:3489660927]	219	1			T2	7		T3	4		T4	7
auto[3489660928:3623878655]	213	1			T2	4		T3	5		T4	5
auto[3623878656:3758096383]	232	1			T2	5		T3	5		T4	6
auto[3758096384:3892314111]	217	1			T2	5		T3	4		T4	5
auto[3892314112:4026531839]	227	1			T2	4		T3	3		T4	6
auto[4026531840:4160749567]	228	1			T2	6		T3	6		T4	7
auto[4160749568:4294967295]	231	1			T2	5		T3	6		T4	8

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	32	32	50.00	32

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Element holes

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	32

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	201	1			T2	5		T3	3		T4	2
auto[134217728:268435455]	auto[0]	184	1			T2	6		T3	2		T4	6
auto[268435456:402653183]	auto[0]	212	1			T2	5		T3	3		T4	2
auto[402653184:536870911]	auto[0]	218	1			T2	7		T3	1		T4	4
auto[536870912:671088639]	auto[0]	214	1			T2	5		T3	5		T4	4
auto[671088640:805306367]	auto[0]	213	1			T2	4		T3	7		T4	2
auto[805306368:939524095]	auto[0]	222	1			T2	2		T3	6		T4	4
auto[939524096:1073741823]	auto[0]	210	1			T2	5		T3	1		T4	4
auto[1073741824:1207959551]	auto[0]	221	1			T2	2		T3	6		T4	5
auto[1207959552:1342177279]	auto[0]	209	1			T2	4		T3	3		T4	5
auto[1342177280:1476395007]	auto[0]	202	1			T2	3		T3	1		T4	2
auto[1476395008:1610612735]	auto[0]	211	1			T2	7		T3	5		T4	5
auto[1610612736:1744830463]	auto[0]	227	1			T2	4		T3	4		T4	2
auto[1744830464:1879048191]	auto[0]	196	1			T2	3		T3	8		T4	2
auto[1879048192:2013265919]	auto[0]	207	1			T2	5		T3	2		T4	4
auto[2013265920:2147483647]	auto[0]	215	1			T2	4		T3	3		T4	5
auto[2147483648:2281701375]	auto[0]	203	1			T2	3		T3	5		T4	3
auto[2281701376:2415919103]	auto[0]	243	1			T2	4		T3	3		T4	11
auto[2415919104:2550136831]	auto[0]	206	1			T2	6		T3	4		T4	2
auto[2550136832:2684354559]	auto[0]	210	1			T2	6		T3	1		T4	3
auto[2684354560:2818572287]	auto[0]	210	1			T2	5		T3	3		T4	4
auto[2818572288:2952790015]	auto[0]	217	1			T2	3		T3	4		T4	5
auto[2952790016:3087007743]	auto[0]	204	1			T2	3		T3	5		T4	2
auto[3087007744:3221225471]	auto[0]	237	1			T2	4		T3	5		T4	10
auto[3221225472:3355443199]	auto[0]	213	1			T2	5		T3	7		T4	7
auto[3355443200:3489660927]	auto[0]	219	1			T2	7		T3	4		T4	7
auto[3489660928:3623878655]	auto[0]	213	1			T2	4		T3	5		T4	5
auto[3623878656:3758096383]	auto[0]	232	1			T2	5		T3	5		T4	6
auto[3758096384:3892314111]	auto[0]	217	1			T2	5		T3	4		T4	5
auto[3892314112:4026531839]	auto[0]	227	1			T2	4		T3	3		T4	6
auto[4026531840:4160749567]	auto[0]	228	1			T2	6		T3	6		T4	7
auto[4160749568:4294967295]	auto[0]	231	1			T2	5		T3	6		T4	8

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

1641

1

T2

35

T3

37

T4

32

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	41	1			T3	1		T4	1		T10	1
auto[134217728:268435455]	49	1			T3	2		T8	2		T9	2
auto[268435456:402653183]	45	1			T2	1		T4	1		T9	2
auto[402653184:536870911]	55	1			T8	2		T9	3		T10	1
auto[536870912:671088639]	41	1			T2	1		T4	2		T8	1
auto[671088640:805306367]	44	1			T2	1		T3	1		T10	1
auto[805306368:939524095]	43	1			T3	3		T8	1		T12	2
auto[939524096:1073741823]	44	1			T3	3		T4	5		T8	1
auto[1073741824:1207959551]	44	1			T2	1		T9	1		T10	2
auto[1207959552:1342177279]	69	1			T8	4		T9	1		T10	1
auto[1342177280:1476395007]	53	1			T2	1		T3	1		T4	1
auto[1476395008:1610612735]	54	1			T2	2		T3	1		T9	4
auto[1610612736:1744830463]	55	1			T2	3		T4	1		T8	1
auto[1744830464:1879048191]	41	1			T2	1		T3	1		T4	1
auto[1879048192:2013265919]	51	1			T3	1		T4	1		T8	2
auto[2013265920:2147483647]	51	1			T3	1		T4	1		T9	1
auto[2147483648:2281701375]	58	1			T2	5		T3	1		T4	2
auto[2281701376:2415919103]	49	1			T2	2		T3	3		T4	1
auto[2415919104:2550136831]	54	1			T2	1		T3	4		T8	2
auto[2550136832:2684354559]	59	1			T2	3		T3	1		T4	1
auto[2684354560:2818572287]	54	1			T2	1		T11	2		T12	3
auto[2818572288:2952790015]	42	1			T2	3		T3	2		T4	3
auto[2952790016:3087007743]	53	1			T4	2		T8	4		T9	1
auto[3087007744:3221225471]	49	1			T2	3		T3	2		T4	2
auto[3221225472:3355443199]	56	1			T2	1		T3	1		T8	2
auto[3355443200:3489660927]	49	1			T3	1		T9	1		T10	1
auto[3489660928:3623878655]	47	1			T2	1		T4	1		T8	1
auto[3623878656:3758096383]	49	1			T2	2		T3	1		T8	3
auto[3758096384:3892314111]	57	1			T2	1		T3	2		T4	2
auto[3892314112:4026531839]	53	1			T2	1		T3	1		T4	2
auto[4026531840:4160749567]	62	1			T3	1		T4	1		T9	1
auto[4160749568:4294967295]	70	1			T3	2		T4	1		T8	3

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	32	32	50.00	32

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Element holes

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[0]]	--	--	32

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[1]	41	1			T3	1		T4	1		T10	1
auto[134217728:268435455]	auto[1]	49	1			T3	2		T8	2		T9	2
auto[268435456:402653183]	auto[1]	45	1			T2	1		T4	1		T9	2
auto[402653184:536870911]	auto[1]	55	1			T8	2		T9	3		T10	1
auto[536870912:671088639]	auto[1]	41	1			T2	1		T4	2		T8	1
auto[671088640:805306367]	auto[1]	44	1			T2	1		T3	1		T10	1
auto[805306368:939524095]	auto[1]	43	1			T3	3		T8	1		T12	2
auto[939524096:1073741823]	auto[1]	44	1			T3	3		T4	5		T8	1
auto[1073741824:1207959551]	auto[1]	44	1			T2	1		T9	1		T10	2
auto[1207959552:1342177279]	auto[1]	69	1			T8	4		T9	1		T10	1
auto[1342177280:1476395007]	auto[1]	53	1			T2	1		T3	1		T4	1
auto[1476395008:1610612735]	auto[1]	54	1			T2	2		T3	1		T9	4
auto[1610612736:1744830463]	auto[1]	55	1			T2	3		T4	1		T8	1
auto[1744830464:1879048191]	auto[1]	41	1			T2	1		T3	1		T4	1
auto[1879048192:2013265919]	auto[1]	51	1			T3	1		T4	1		T8	2
auto[2013265920:2147483647]	auto[1]	51	1			T3	1		T4	1		T9	1
auto[2147483648:2281701375]	auto[1]	58	1			T2	5		T3	1		T4	2
auto[2281701376:2415919103]	auto[1]	49	1			T2	2		T3	3		T4	1
auto[2415919104:2550136831]	auto[1]	54	1			T2	1		T3	4		T8	2
auto[2550136832:2684354559]	auto[1]	59	1			T2	3		T3	1		T4	1
auto[2684354560:2818572287]	auto[1]	54	1			T2	1		T11	2		T12	3
auto[2818572288:2952790015]	auto[1]	42	1			T2	3		T3	2		T4	3
auto[2952790016:3087007743]	auto[1]	53	1			T4	2		T8	4		T9	1
auto[3087007744:3221225471]	auto[1]	49	1			T2	3		T3	2		T4	2
auto[3221225472:3355443199]	auto[1]	56	1			T2	1		T3	1		T8	2
auto[3355443200:3489660927]	auto[1]	49	1			T3	1		T9	1		T10	1
auto[3489660928:3623878655]	auto[1]	47	1			T2	1		T4	1		T8	1
auto[3623878656:3758096383]	auto[1]	49	1			T2	2		T3	1		T8	3
auto[3758096384:3892314111]	auto[1]	57	1			T2	1		T3	2		T4	2
auto[3892314112:4026531839]	auto[1]	53	1			T2	1		T3	1		T4	2
auto[4026531840:4160749567]	auto[1]	62	1			T3	1		T4	1		T9	1
auto[4160749568:4294967295]	auto[1]	70	1			T3	2		T4	1		T8	3