Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	818679	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

247421

1

T1

4

T2

2838

T3

2653

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	922971	1			T1	1		T2	11687		T3	4511
values[0x0]	70842	1			T1	6		T2	677		T3	654
values[0x1]	72287	1			T1	8		T2	679		T3	666

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	561651	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

504449

1

T1

4

T2

5967

T3

3472

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3597	1			T2	46		T4	91		T9	101
valid_sources[0x01]	3536	1			T2	64		T4	126		T9	94
valid_sources[0x02]	3476	1			T2	52		T4	80		T15	1
valid_sources[0x03]	3819	1			T2	51		T4	104		T9	90
valid_sources[0x04]	3333	1			T2	45		T4	122		T9	135
valid_sources[0x05]	3440	1			T2	54		T4	89		T9	84
valid_sources[0x06]	3573	1			T2	44		T4	130		T9	85
valid_sources[0x07]	3418	1			T2	56		T4	143		T15	3
valid_sources[0x08]	3325	1			T2	54		T4	119		T9	86
valid_sources[0x09]	3539	1			T2	53		T4	159		T9	62
valid_sources[0x0a]	3649	1			T2	46		T3	135		T4	52
valid_sources[0x0b]	3757	1			T2	53		T4	92		T9	112
valid_sources[0x0c]	3795	1			T2	42		T3	132		T4	91
valid_sources[0x0d]	24113	1			T2	52		T4	99		T9	113
valid_sources[0x0e]	3399	1			T2	63		T4	92		T9	76
valid_sources[0x0f]	3334	1			T2	53		T4	84		T9	87
valid_sources[0x10]	6582	1			T2	53		T4	93		T15	2
valid_sources[0x11]	3289	1			T2	33		T4	101		T9	98
valid_sources[0x12]	3675	1			T2	55		T4	97		T15	1
valid_sources[0x13]	3547	1			T2	54		T4	92		T9	101
valid_sources[0x14]	3526	1			T2	71		T4	103		T9	94
valid_sources[0x15]	3381	1			T2	58		T4	92		T15	1
valid_sources[0x16]	3509	1			T2	51		T4	110		T9	95
valid_sources[0x17]	5180	1			T2	53		T4	121		T9	79
valid_sources[0x18]	3580	1			T2	55		T4	121		T9	116
valid_sources[0x19]	3233	1			T2	73		T4	131		T9	85
valid_sources[0x1a]	3324	1			T2	43		T4	86		T9	55
valid_sources[0x1b]	3804	1			T2	40		T4	116		T9	104
valid_sources[0x1c]	7102	1			T2	50		T4	83		T9	54
valid_sources[0x1d]	3674	1			T2	50		T4	126		T9	121
valid_sources[0x1e]	3917	1			T2	64		T4	74		T9	109
valid_sources[0x1f]	3710	1			T2	76		T4	108		T9	71
valid_sources[0x20]	3776	1			T2	39		T4	94		T9	123
valid_sources[0x21]	3587	1			T2	54		T4	89		T9	97
valid_sources[0x22]	3301	1			T2	45		T4	97		T9	72
valid_sources[0x23]	3272	1			T2	44		T4	95		T9	45
valid_sources[0x24]	3477	1			T2	35		T4	91		T9	39
valid_sources[0x25]	3346	1			T2	59		T4	115		T15	2
valid_sources[0x26]	3763	1			T2	44		T4	106		T9	79
valid_sources[0x27]	3898	1			T2	50		T4	109		T9	42
valid_sources[0x28]	3423	1			T2	33		T4	118		T15	2
valid_sources[0x29]	6975	1			T2	48		T4	118		T9	100
valid_sources[0x2a]	3570	1			T2	41		T4	109		T9	122
valid_sources[0x2b]	3531	1			T2	63		T4	117		T9	101
valid_sources[0x2c]	3701	1			T2	43		T4	109		T9	150
valid_sources[0x2d]	3380	1			T2	53		T4	114		T9	99
valid_sources[0x2e]	3446	1			T2	66		T4	117		T9	80
valid_sources[0x2f]	3529	1			T2	62		T4	109		T15	1
valid_sources[0x30]	5865	1			T2	50		T4	97		T9	78
valid_sources[0x31]	3541	1			T2	45		T4	95		T15	1
valid_sources[0x32]	3537	1			T2	55		T4	109		T9	126
valid_sources[0x33]	3182	1			T2	44		T4	79		T9	135
valid_sources[0x34]	6653	1			T2	53		T4	76		T9	53
valid_sources[0x35]	6704	1			T2	53		T4	94		T9	140
valid_sources[0x36]	18400	1			T2	49		T4	95		T9	82
valid_sources[0x37]	3590	1			T2	55		T4	94		T9	90
valid_sources[0x38]	3234	1			T2	45		T4	78		T9	80
valid_sources[0x39]	3712	1			T2	49		T4	91		T9	98
valid_sources[0x3a]	3321	1			T2	54		T4	88		T9	88
valid_sources[0x3b]	3584	1			T2	61		T4	82		T9	125
valid_sources[0x3c]	3826	1			T2	52		T4	104		T9	116
valid_sources[0x3d]	9204	1			T2	34		T4	110		T9	83
valid_sources[0x3e]	3623	1			T2	54		T4	92		T9	75
valid_sources[0x3f]	4058	1			T2	54		T4	92		T9	110
valid_sources[0x40]	3611	1			T2	68		T4	105		T9	119
valid_sources[0x41]	3221	1			T2	62		T4	104		T9	116
valid_sources[0x42]	3341	1			T2	45		T4	81		T9	80
valid_sources[0x43]	3359	1			T2	45		T4	116		T9	97
valid_sources[0x44]	3479	1			T2	54		T4	111		T9	89
valid_sources[0x45]	3328	1			T2	37		T4	76		T9	114
valid_sources[0x46]	4251	1			T2	51		T4	85		T9	105
valid_sources[0x47]	3554	1			T2	49		T4	93		T9	102
valid_sources[0x48]	3753	1			T2	67		T4	121		T9	73
valid_sources[0x49]	10883	1			T2	48		T4	112		T9	94
valid_sources[0x4a]	3805	1			T2	64		T4	80		T9	117
valid_sources[0x4b]	3264	1			T2	42		T4	90		T9	83
valid_sources[0x4c]	3457	1			T2	52		T4	84		T9	64
valid_sources[0x4d]	3528	1			T2	45		T4	93		T9	64
valid_sources[0x4e]	3533	1			T2	43		T4	117		T9	97
valid_sources[0x4f]	3583	1			T2	46		T4	102		T9	52
valid_sources[0x50]	3301	1			T2	52		T4	78		T9	87
valid_sources[0x51]	3722	1			T2	45		T4	109		T9	131
valid_sources[0x52]	3856	1			T2	51		T4	106		T9	121
valid_sources[0x53]	3490	1			T2	46		T4	99		T9	87
valid_sources[0x54]	3573	1			T2	50		T4	88		T9	77
valid_sources[0x55]	3526	1			T2	44		T4	105		T9	69
valid_sources[0x56]	3271	1			T2	48		T4	115		T9	75
valid_sources[0x57]	3015	1			T2	55		T4	62		T9	84
valid_sources[0x58]	3737	1			T2	48		T4	102		T9	90
valid_sources[0x59]	3685	1			T2	48		T4	102		T9	118
valid_sources[0x5a]	3727	1			T2	74		T4	73		T9	95
valid_sources[0x5b]	11395	1			T2	49		T4	78		T15	1
valid_sources[0x5c]	3739	1			T2	41		T4	118		T9	121
valid_sources[0x5d]	3306	1			T2	54		T4	117		T9	76
valid_sources[0x5e]	3518	1			T2	65		T4	91		T9	117
valid_sources[0x5f]	3545	1			T2	58		T4	96		T15	4
valid_sources[0x60]	6156	1			T2	64		T4	104		T9	120
valid_sources[0x61]	3706	1			T2	65		T4	63		T9	108
valid_sources[0x62]	3560	1			T2	62		T4	103		T9	83
valid_sources[0x63]	3450	1			T2	49		T4	80		T9	87
valid_sources[0x64]	4028	1			T2	58		T4	103		T15	2
valid_sources[0x65]	3144	1			T2	45		T4	83		T9	75
valid_sources[0x66]	3669	1			T2	46		T4	93		T9	90
valid_sources[0x67]	3251	1			T2	53		T4	79		T9	86
valid_sources[0x68]	5083	1			T2	53		T3	1635		T4	73
valid_sources[0x69]	3644	1			T2	55		T4	120		T9	93
valid_sources[0x6a]	3742	1			T2	58		T4	109		T9	105
valid_sources[0x6b]	5418	1			T2	55		T4	112		T9	83
valid_sources[0x6c]	3348	1			T2	46		T4	113		T9	88
valid_sources[0x6d]	3540	1			T2	49		T4	124		T9	93
valid_sources[0x6e]	3440	1			T2	43		T4	87		T9	55
valid_sources[0x6f]	8433	1			T2	48		T4	87		T9	80
valid_sources[0x70]	3601	1			T2	48		T4	96		T9	88
valid_sources[0x71]	3271	1			T2	45		T4	83		T9	70
valid_sources[0x72]	3814	1			T2	51		T4	95		T9	85
valid_sources[0x73]	3374	1			T2	52		T4	82		T9	102
valid_sources[0x74]	3158	1			T2	44		T4	75		T9	77
valid_sources[0x75]	3449	1			T2	48		T4	94		T9	91
valid_sources[0x76]	7319	1			T2	48		T3	3929		T4	124
valid_sources[0x77]	3605	1			T2	66		T4	97		T9	84
valid_sources[0x78]	3342	1			T2	46		T4	105		T9	106
valid_sources[0x79]	3387	1			T2	51		T4	87		T9	144
valid_sources[0x7a]	3522	1			T2	43		T4	108		T9	90
valid_sources[0x7b]	3145	1			T2	40		T4	93		T9	83
valid_sources[0x7c]	7033	1			T2	57		T4	117		T9	71
valid_sources[0x7d]	3529	1			T2	58		T4	101		T9	79
valid_sources[0x7e]	3410	1			T2	41		T4	106		T9	82
valid_sources[0x7f]	3592	1			T2	50		T4	115		T9	87
valid_sources[0x80]	3410	1			T2	68		T4	95		T9	104

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

138092

1

T1

1

T2

1893

T3

1759

values[0x0]

all_enables

biggest_size

58030

1

T1

1

T2

523

T3

491

values[0x1]

all_enables

biggest_size

51299

1

T1

2

T2

422

T3

403