Unified Coverage Report :: Module :: keymgr_dpe_op_state

Module : keymgr_dpe_op_state_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00	66.67		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_op_state_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ctrl.u_op_state	93.33	100.00	66.67		100.00	100.00	100.00

Module Instance : tb.dut.u_ctrl.u_op_state

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00	66.67		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00	66.67		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.88	94.29	87.24		61.54	90.62	85.71	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr_dpe_op_state_ctrl

	Line No.	Total	Covered	Percent
TOTAL		34	34	100.00
ALWAYS	68	3	3	100.00
CONT_ASSIGN	71	1	1	100.00
ALWAYS	74	30	30	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_op_state_ctrl.sv' or '../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_op_state_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	3	3
71	1	1
74	1	1
75	1	1
76	1	1
77	1	1
80	1	1
82	1	1
83	1	1
85	1	1
87	1	1
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	1	1
94	1	1
			MISSING_ELSE
104	1	1
105	1	1
106	1	1
110	1	1
111	1	1
113	1	1
114	1	1
115	1	1
116	1	1
			MISSING_ELSE
122	1	1
123	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Module : keymgr_dpe_op_state_ctrl

	Total	Covered	Percent
Conditions	3	2	66.67
Logical	3	2	66.67
Non-Logical	0	0
Event	0	0

 LINE       71
 EXPRESSION (gen_en & gen_req_i)
             ---1--   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T3,T4

FSM Coverage for Module : keymgr_dpe_op_state_ctrl

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
StAdv	90	Covered	T2,T3,T4
StDis	88	Covered	T2,T3,T4
StErase	94	Covered	T2,T3,T4
StIdle	106	Covered	T1,T2,T3
StWait	92	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
StAdv->StIdle	116	Covered	T2,T3,T4
StDis->StIdle	106	Covered	T2,T3,T4
StErase->StIdle	106	Covered	T2,T3,T4
StIdle->StAdv	90	Covered	T2,T3,T4
StIdle->StDis	88	Covered	T2,T3,T4
StIdle->StErase	94	Covered	T2,T3,T4
StIdle->StWait	92	Covered	T2,T3,T4
StWait->StIdle	127	Covered	T2,T3,T4

Branch Coverage for Module : keymgr_dpe_op_state_ctrl

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
IF	68	2	2	100.00
CASE	85	11	11	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_op_state_ctrl.sv' or '../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_op_state_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	68	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	85	case (state_q)
-2-:	87	if (dis_req_i)
-3-:	89	if (adv_req_i)
-4-:	91	if (gen_req_i)
-5-:	93	if (erase_req_i)
-6-:	113	if (kmac_done_i)
-7-:	125	if (kmac_done_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
StIdle	1	-	-	-	-	-	Covered	T2,T3,T4
StIdle	0	1	-	-	-	-	Covered	T2,T3,T4
StIdle	0	0	1	-	-	-	Covered	T2,T3,T4
StIdle	0	0	0	1	-	-	Covered	T2,T3,T4
StIdle	0	0	0	0	-	-	Covered	T1,T2,T3
StErase StDis	-	-	-	-	-	-	Covered	T2,T3,T4
StAdv	-	-	-	-	1	-	Covered	T2,T3,T4
StAdv	-	-	-	-	0	-	Covered	T2,T3,T4
StWait	-	-	-	-	-	1	Covered	T2,T3,T4
StWait	-	-	-	-	-	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	Covered	T5,T6,T7

Assert Coverage for Module : keymgr_dpe_op_state_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
u_state_regs_A	5935035	5887059	0	0

u_state_regs_A

Name	Attempts	Real Successes
Total	5935035	5887059
T1	992	914
T2	47418	47320
T3	13675	13594
T4	138568	138499
T5	30884	24152
T8	26159	26099
T9	123393	123336
T10	50945	50871
T15	1601	1520
T16	719	646