Unified Coverage Report :: Module :: keymgr_dpe_csr_assert_fpv

Module : keymgr_dpe_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_dpe_csr_assert_0/keymgr_dpe_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_dpe_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_dpe_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.32	100.00	79.89	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_dpe_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	22	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	7230261	7728	0	0
intr_enable_rd_A	7230261	2488	0	0
key_version_rd_A	7230261	2285	0	0
reseed_interval_regwen_rd_A	7230261	831	0	0
salt_0_rd_A	7230261	2203	0	0
salt_1_rd_A	7230261	2109	0	0
salt_2_rd_A	7230261	2235	0	0
salt_3_rd_A	7230261	2328	0	0
salt_4_rd_A	7230261	2269	0	0
salt_5_rd_A	7230261	2324	0	0
salt_6_rd_A	7230261	2289	0	0
salt_7_rd_A	7230261	2327	0	0
sideload_clear_rd_A	7230261	2163	0	0
slot_policy_rd_A	7230261	3195	0	0
sw_binding_0_rd_A	7230261	2411	0	0
sw_binding_1_rd_A	7230261	2111	0	0
sw_binding_2_rd_A	7230261	2440	0	0
sw_binding_3_rd_A	7230261	2230	0	0
sw_binding_4_rd_A	7230261	2180	0	0
sw_binding_5_rd_A	7230261	2442	0	0
sw_binding_6_rd_A	7230261	2287	0	0
sw_binding_7_rd_A	7230261	2275	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7230261	7728	0	0
T18	1047	12	0	0
T19	22004	2	0	0
T20	2466	13	0	0
T26	6911	393	0	0
T27	1537	68	0	0
T30	2103	83	0	0
T35	0	444	0	0
T58	10860	0	0	0
T63	934	0	0	0
T64	838	0	0	0
T79	2630	2	0	0
T80	0	46	0	0
T81	0	11	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7230261	2488	0	0
T19	22004	81	0	0
T20	2466	4	0	0
T32	8534	30	0	0
T41	1625	26	0	0
T59	22019	0	0	0
T64	838	9	0	0
T65	1323	3	0	0
T66	1142	0	0	0
T71	9254	63	0	0
T79	2630	6	0	0
T81	0	1	0	0
T82	0	28	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7230261	2285	0	0
T19	22004	89	0	0
T20	2466	5	0	0
T32	8534	48	0	0
T39	0	11	0	0
T59	22019	0	0	0
T65	1323	9	0	0
T66	1142	0	0	0
T71	9254	100	0	0
T79	2630	1	0	0
T80	1485	0	0	0
T81	2112	7	0	0
T82	0	34	0	0
T83	0	174	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7230261	831	0	0
T20	2466	12	0	0
T28	8847	0	0	0
T32	8534	52	0	0
T39	0	8	0	0
T40	0	10	0	0
T62	18436	0	0	0
T71	9254	35	0	0
T79	2630	9	0	0
T82	6686	30	0	0
T83	0	151	0	0
T84	0	21	0	0
T85	0	17	0	0
T86	897	0	0	0
T87	3691	0	0	0
T88	1333	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7230261	2203	0	0
T19	22004	77	0	0
T20	2466	9	0	0
T32	8534	26	0	0
T39	0	2	0	0
T59	22019	0	0	0
T65	1323	3	0	0
T66	1142	0	0	0
T71	9254	67	0	0
T79	2630	7	0	0
T80	1485	0	0	0
T81	2112	8	0	0
T82	0	20	0	0
T83	0	205	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7230261	2109	0	0
T19	22004	53	0	0
T20	2466	11	0	0
T32	8534	56	0	0
T35	11659	0	0	0
T39	0	7	0	0
T60	4326	0	0	0
T61	19631	0	0	0
T71	9254	15	0	0
T73	7295	0	0	0
T79	2630	6	0	0
T81	2112	6	0	0
T82	0	25	0	0
T83	0	153	0	0
T84	0	12	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7230261	2235	0	0
T19	22004	75	0	0
T20	2466	11	0	0
T32	8534	65	0	0
T35	11659	0	0	0
T39	0	8	0	0
T60	4326	0	0	0
T61	19631	0	0	0
T71	9254	52	0	0
T73	7295	0	0	0
T79	2630	1	0	0
T81	2112	2	0	0
T82	0	18	0	0
T83	0	220	0	0
T84	0	46	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7230261	2328	0	0
T19	22004	84	0	0
T20	2466	13	0	0
T32	8534	119	0	0
T39	0	10	0	0
T59	22019	0	0	0
T65	1323	5	0	0
T66	1142	0	0	0
T71	9254	24	0	0
T79	2630	2	0	0
T80	1485	0	0	0
T81	2112	3	0	0
T82	0	34	0	0
T83	0	203	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7230261	2269	0	0
T19	22004	76	0	0
T20	2466	7	0	0
T32	8534	40	0	0
T39	0	6	0	0
T59	22019	0	0	0
T65	1323	5	0	0
T66	1142	0	0	0
T71	9254	62	0	0
T79	2630	5	0	0
T80	1485	0	0	0
T81	2112	16	0	0
T82	0	15	0	0
T83	0	180	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7230261	2324	0	0
T19	22004	72	0	0
T20	2466	20	0	0
T32	8534	19	0	0
T39	0	14	0	0
T59	22019	0	0	0
T65	1323	4	0	0
T66	1142	0	0	0
T71	9254	53	0	0
T79	2630	5	0	0
T80	1485	0	0	0
T81	2112	4	0	0
T82	0	36	0	0
T83	0	206	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7230261	2289	0	0
T19	22004	105	0	0
T20	2466	2	0	0
T32	8534	77	0	0
T35	11659	0	0	0
T40	0	27	0	0
T60	4326	0	0	0
T61	19631	0	0	0
T71	9254	36	0	0
T73	7295	0	0	0
T79	2630	1	0	0
T81	2112	8	0	0
T82	0	20	0	0
T83	0	200	0	0
T84	0	35	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7230261	2327	0	0
T19	22004	61	0	0
T20	2466	11	0	0
T32	8534	51	0	0
T35	11659	0	0	0
T39	0	3	0	0
T40	0	19	0	0
T60	4326	0	0	0
T61	19631	0	0	0
T71	9254	42	0	0
T73	7295	0	0	0
T81	2112	17	0	0
T82	6686	24	0	0
T83	0	208	0	0
T84	0	29	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7230261	2163	0	0
T19	22004	92	0	0
T20	2466	26	0	0
T32	8534	16	0	0
T39	0	12	0	0
T59	22019	0	0	0
T65	1323	3	0	0
T66	1142	0	0	0
T71	9254	17	0	0
T79	2630	6	0	0
T80	1485	0	0	0
T81	2112	5	0	0
T82	0	19	0	0
T83	0	177	0	0

slot_policy_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7230261	3195	0	0
T19	22004	164	0	0
T20	2466	7	0	0
T32	8534	52	0	0
T39	0	4	0	0
T59	22019	0	0	0
T65	1323	4	0	0
T66	1142	0	0	0
T71	9254	37	0	0
T79	2630	6	0	0
T80	1485	0	0	0
T81	2112	15	0	0
T82	0	14	0	0
T83	0	234	0	0

sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7230261	2411	0	0
T19	22004	86	0	0
T20	2466	4	0	0
T32	8534	52	0	0
T35	11659	0	0	0
T39	0	2	0	0
T60	4326	0	0	0
T61	19631	0	0	0
T71	9254	27	0	0
T73	7295	0	0	0
T79	2630	6	0	0
T81	2112	1	0	0
T82	0	21	0	0
T83	0	229	0	0
T84	0	14	0	0

sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7230261	2111	0	0
T19	22004	87	0	0
T20	2466	6	0	0
T32	8534	59	0	0
T35	11659	0	0	0
T40	0	20	0	0
T60	4326	0	0	0
T61	19631	0	0	0
T71	9254	7	0	0
T73	7295	0	0	0
T79	2630	1	0	0
T81	2112	7	0	0
T82	0	42	0	0
T83	0	165	0	0
T84	0	33	0	0

sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7230261	2440	0	0
T19	22004	87	0	0
T20	2466	10	0	0
T32	8534	83	0	0
T35	11659	0	0	0
T39	0	17	0	0
T40	0	28	0	0
T60	4326	0	0	0
T61	19631	0	0	0
T71	9254	19	0	0
T73	7295	0	0	0
T81	2112	3	0	0
T82	6686	26	0	0
T83	0	231	0	0
T84	0	32	0	0

sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7230261	2230	0	0
T19	22004	91	0	0
T20	2466	7	0	0
T32	8534	32	0	0
T35	11659	0	0	0
T40	0	17	0	0
T60	4326	0	0	0
T61	19631	0	0	0
T71	9254	23	0	0
T73	7295	0	0	0
T79	2630	1	0	0
T81	2112	6	0	0
T82	0	13	0	0
T83	0	192	0	0
T84	0	23	0	0

sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7230261	2180	0	0
T19	22004	84	0	0
T20	2466	5	0	0
T32	8534	42	0	0
T39	0	8	0	0
T59	22019	0	0	0
T65	1323	8	0	0
T66	1142	0	0	0
T71	9254	36	0	0
T79	2630	4	0	0
T80	1485	0	0	0
T81	2112	6	0	0
T82	0	21	0	0
T83	0	184	0	0

sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7230261	2442	0	0
T19	22004	78	0	0
T20	2466	14	0	0
T32	8534	25	0	0
T35	11659	0	0	0
T39	0	5	0	0
T60	4326	0	0	0
T61	19631	0	0	0
T71	9254	63	0	0
T73	7295	0	0	0
T79	2630	3	0	0
T81	2112	18	0	0
T82	0	24	0	0
T83	0	225	0	0
T84	0	12	0	0

sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7230261	2287	0	0
T19	22004	97	0	0
T20	2466	20	0	0
T32	8534	43	0	0
T39	0	13	0	0
T59	22019	0	0	0
T65	1323	2	0	0
T66	1142	0	0	0
T71	9254	59	0	0
T79	2630	3	0	0
T80	1485	0	0	0
T81	2112	11	0	0
T82	0	28	0	0
T83	0	149	0	0

sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7230261	2275	0	0
T19	22004	89	0	0
T20	2466	11	0	0
T32	8534	32	0	0
T35	11659	0	0	0
T39	0	15	0	0
T60	4326	0	0	0
T61	19631	0	0	0
T71	9254	40	0	0
T73	7295	0	0	0
T79	2630	6	0	0
T81	2112	22	0	0
T82	0	30	0	0
T83	0	168	0	0
T84	0	9	0	0