Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	843615	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

244274

1

T1

11

T2

2615

T3

2453

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	944182	1			T1	1		T2	8654		T3	6149
values[0x0]	71173	1			T1	14		T2	617		T3	617
values[0x1]	72534	1			T1	13		T2	621		T3	641

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	577769	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

510120

1

T1

11

T2

4809

T3

4001

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3844	1			T2	45		T3	24		T9	124
valid_sources[0x01]	9891	1			T2	43		T3	28		T9	129
valid_sources[0x02]	3870	1			T2	42		T3	27		T9	153
valid_sources[0x03]	4029	1			T2	38		T3	24		T9	117
valid_sources[0x04]	6547	1			T1	1		T2	35		T3	15
valid_sources[0x05]	3739	1			T2	40		T3	34		T15	1
valid_sources[0x06]	3723	1			T2	33		T3	32		T9	129
valid_sources[0x07]	3879	1			T2	49		T3	33		T9	112
valid_sources[0x08]	3528	1			T2	24		T3	15		T9	149
valid_sources[0x09]	3824	1			T2	22		T3	26		T9	132
valid_sources[0x0a]	4108	1			T2	39		T3	33		T9	123
valid_sources[0x0b]	5040	1			T2	41		T3	30		T9	126
valid_sources[0x0c]	3677	1			T1	1		T2	29		T3	22
valid_sources[0x0d]	10808	1			T2	29		T3	22		T9	116
valid_sources[0x0e]	3436	1			T2	49		T3	27		T9	159
valid_sources[0x0f]	3571	1			T2	39		T3	43		T9	116
valid_sources[0x10]	3886	1			T1	1		T2	41		T3	26
valid_sources[0x11]	3818	1			T1	1		T2	51		T3	25
valid_sources[0x12]	3987	1			T2	40		T3	27		T9	165
valid_sources[0x13]	4229	1			T2	52		T3	31		T9	144
valid_sources[0x14]	3472	1			T2	41		T3	27		T9	149
valid_sources[0x15]	3953	1			T2	36		T3	22		T9	141
valid_sources[0x16]	3402	1			T2	29		T3	38		T9	100
valid_sources[0x17]	3741	1			T1	1		T2	49		T3	28
valid_sources[0x18]	3846	1			T2	37		T3	36		T9	127
valid_sources[0x19]	3720	1			T2	43		T3	20		T9	97
valid_sources[0x1a]	4531	1			T2	41		T3	32		T4	263
valid_sources[0x1b]	3807	1			T1	2		T2	34		T3	20
valid_sources[0x1c]	9579	1			T2	44		T3	42		T9	138
valid_sources[0x1d]	3806	1			T2	42		T3	31		T9	142
valid_sources[0x1e]	3629	1			T1	2		T2	39		T3	30
valid_sources[0x1f]	3527	1			T2	35		T3	16		T9	151
valid_sources[0x20]	3566	1			T2	40		T3	38		T9	152
valid_sources[0x21]	3810	1			T2	43		T3	37		T9	118
valid_sources[0x22]	8202	1			T2	36		T3	34		T9	113
valid_sources[0x23]	3966	1			T2	28		T3	30		T15	1
valid_sources[0x24]	3808	1			T2	49		T3	29		T9	132
valid_sources[0x25]	3799	1			T2	27		T3	21		T9	141
valid_sources[0x26]	3900	1			T2	37		T3	28		T9	137
valid_sources[0x27]	3684	1			T2	53		T3	22		T9	115
valid_sources[0x28]	4119	1			T2	55		T3	32		T9	95
valid_sources[0x29]	3754	1			T2	34		T3	29		T9	84
valid_sources[0x2a]	3759	1			T2	48		T3	30		T9	124
valid_sources[0x2b]	3695	1			T2	44		T3	35		T9	129
valid_sources[0x2c]	3658	1			T1	1		T2	39		T3	38
valid_sources[0x2d]	4317	1			T2	41		T3	33		T9	142
valid_sources[0x2e]	3411	1			T2	28		T3	34		T9	128
valid_sources[0x2f]	3770	1			T2	45		T3	29		T9	110
valid_sources[0x30]	3719	1			T2	39		T3	31		T9	103
valid_sources[0x31]	3684	1			T2	46		T3	25		T9	125
valid_sources[0x32]	4228	1			T1	1		T2	42		T3	22
valid_sources[0x33]	3646	1			T2	34		T3	39		T9	122
valid_sources[0x34]	3706	1			T2	35		T3	22		T9	103
valid_sources[0x35]	5279	1			T2	42		T3	32		T9	135
valid_sources[0x36]	26428	1			T2	40		T3	30		T9	98
valid_sources[0x37]	3861	1			T2	42		T3	17		T9	136
valid_sources[0x38]	3969	1			T2	46		T3	32		T9	132
valid_sources[0x39]	3572	1			T2	36		T3	18		T9	115
valid_sources[0x3a]	3940	1			T2	39		T3	32		T9	139
valid_sources[0x3b]	12599	1			T2	32		T3	26		T9	138
valid_sources[0x3c]	3748	1			T2	52		T3	32		T9	128
valid_sources[0x3d]	3875	1			T2	39		T3	31		T9	122
valid_sources[0x3e]	3789	1			T2	37		T3	26		T9	138
valid_sources[0x3f]	3851	1			T2	35		T3	21		T9	126
valid_sources[0x40]	3339	1			T2	42		T3	32		T9	132
valid_sources[0x41]	3629	1			T2	41		T3	23		T9	148
valid_sources[0x42]	3977	1			T2	44		T3	43		T9	109
valid_sources[0x43]	3837	1			T1	1		T2	40		T3	24
valid_sources[0x44]	4229	1			T2	31		T3	28		T9	112
valid_sources[0x45]	3709	1			T2	32		T3	37		T9	111
valid_sources[0x46]	3770	1			T2	40		T3	22		T9	159
valid_sources[0x47]	3890	1			T2	30		T3	24		T9	135
valid_sources[0x48]	3639	1			T2	51		T3	34		T9	109
valid_sources[0x49]	3804	1			T2	42		T3	39		T9	155
valid_sources[0x4a]	3340	1			T2	47		T3	37		T9	143
valid_sources[0x4b]	14648	1			T2	37		T3	25		T8	10998
valid_sources[0x4c]	3684	1			T2	37		T3	34		T9	134
valid_sources[0x4d]	3694	1			T2	54		T3	28		T9	132
valid_sources[0x4e]	3890	1			T2	42		T3	38		T9	121
valid_sources[0x4f]	6129	1			T2	45		T3	21		T9	121
valid_sources[0x50]	4199	1			T2	42		T3	32		T15	2
valid_sources[0x51]	3478	1			T2	44		T3	12		T9	103
valid_sources[0x52]	3783	1			T2	50		T3	43		T9	133
valid_sources[0x53]	3771	1			T1	1		T2	37		T3	21
valid_sources[0x54]	7308	1			T2	38		T3	15		T9	147
valid_sources[0x55]	3796	1			T2	44		T3	31		T9	154
valid_sources[0x56]	3447	1			T2	29		T3	34		T9	138
valid_sources[0x57]	5571	1			T2	42		T3	35		T4	2050
valid_sources[0x58]	3519	1			T2	29		T3	33		T9	112
valid_sources[0x59]	3732	1			T2	35		T3	30		T9	127
valid_sources[0x5a]	3763	1			T2	40		T3	18		T9	126
valid_sources[0x5b]	3593	1			T2	38		T3	31		T9	101
valid_sources[0x5c]	3501	1			T2	26		T3	34		T9	115
valid_sources[0x5d]	3778	1			T2	42		T3	25		T9	119
valid_sources[0x5e]	3671	1			T2	32		T3	26		T9	163
valid_sources[0x5f]	3516	1			T2	57		T3	15		T9	134
valid_sources[0x60]	3388	1			T2	28		T3	36		T9	148
valid_sources[0x61]	3552	1			T2	69		T3	27		T9	116
valid_sources[0x62]	3880	1			T2	24		T3	27		T9	126
valid_sources[0x63]	3817	1			T2	33		T3	20		T9	102
valid_sources[0x64]	4030	1			T2	24		T3	29		T9	149
valid_sources[0x65]	3847	1			T2	38		T3	43		T9	133
valid_sources[0x66]	3434	1			T1	1		T2	40		T3	29
valid_sources[0x67]	4337	1			T2	41		T3	31		T9	132
valid_sources[0x68]	3607	1			T2	33		T3	31		T9	132
valid_sources[0x69]	3813	1			T2	40		T3	26		T9	153
valid_sources[0x6a]	3703	1			T2	43		T3	29		T9	136
valid_sources[0x6b]	3736	1			T2	27		T3	31		T9	124
valid_sources[0x6c]	3641	1			T2	31		T3	16		T9	116
valid_sources[0x6d]	4078	1			T2	38		T3	28		T9	166
valid_sources[0x6e]	3899	1			T2	39		T3	15		T9	137
valid_sources[0x6f]	3784	1			T2	42		T3	38		T9	106
valid_sources[0x70]	3735	1			T2	36		T3	39		T9	151
valid_sources[0x71]	3866	1			T2	39		T3	41		T9	119
valid_sources[0x72]	3503	1			T2	40		T3	30		T9	137
valid_sources[0x73]	3634	1			T1	1		T2	31		T3	30
valid_sources[0x74]	4069	1			T2	49		T3	30		T9	94
valid_sources[0x75]	3989	1			T2	30		T3	26		T9	140
valid_sources[0x76]	3465	1			T2	36		T3	25		T9	116
valid_sources[0x77]	3774	1			T2	32		T3	29		T9	121
valid_sources[0x78]	3636	1			T2	32		T3	32		T9	148
valid_sources[0x79]	3736	1			T2	40		T3	15		T9	123
valid_sources[0x7a]	3853	1			T2	40		T3	27		T9	115
valid_sources[0x7b]	3839	1			T2	33		T3	22		T9	118
valid_sources[0x7c]	4762	1			T2	36		T3	24		T9	129
valid_sources[0x7d]	4073	1			T2	29		T3	30		T9	135
valid_sources[0x7e]	3509	1			T2	35		T3	23		T9	107
valid_sources[0x7f]	3750	1			T1	1		T2	45		T3	31
valid_sources[0x80]	3679	1			T1	1		T2	31		T3	36

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

134004

1

T2

1754

T3

1598

T4

1773

values[0x0]

all_enables

biggest_size

58548

1

T1

7

T2

480

T3

471

values[0x1]

all_enables

biggest_size

51722

1

T1

4

T2

381

T3

384