Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	840530	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

239581

1

T1

3

T2

2

T3

2501

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	941210	1			T1	1		T2	1		T3	3593
values[0x0]	69001	1			T1	10		T2	5		T3	618
values[0x1]	69900	1			T1	5		T2	6		T3	574

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	576264	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

503847

1

T1

6

T2

3

T3

3052

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3074	1			T3	18		T4	35		T5	47
valid_sources[0x01]	3024	1			T3	17		T4	18		T5	49
valid_sources[0x02]	3087	1			T3	16		T4	20		T5	24
valid_sources[0x03]	3300	1			T3	32		T4	16		T5	71
valid_sources[0x04]	3059	1			T3	33		T4	22		T5	26
valid_sources[0x05]	3077	1			T3	16		T4	14		T5	17
valid_sources[0x06]	3213	1			T3	11		T4	19		T5	33
valid_sources[0x07]	3103	1			T3	15		T4	34		T5	20
valid_sources[0x08]	3036	1			T3	26		T4	28		T5	47
valid_sources[0x09]	2946	1			T3	31		T4	21		T5	61
valid_sources[0x0a]	2798	1			T3	22		T4	17		T5	23
valid_sources[0x0b]	2994	1			T3	41		T4	21		T5	19
valid_sources[0x0c]	2972	1			T3	25		T4	15		T5	28
valid_sources[0x0d]	3267	1			T3	8		T4	21		T5	7
valid_sources[0x0e]	2679	1			T1	1		T3	21		T4	19
valid_sources[0x0f]	2768	1			T3	15		T4	26		T5	36
valid_sources[0x10]	3276	1			T3	26		T4	22		T5	30
valid_sources[0x11]	3217	1			T3	31		T4	23		T5	38
valid_sources[0x12]	4426	1			T3	15		T4	20		T5	59
valid_sources[0x13]	3052	1			T3	34		T4	26		T5	36
valid_sources[0x14]	2980	1			T3	27		T4	21		T5	35
valid_sources[0x15]	3166	1			T3	8		T4	19		T5	30
valid_sources[0x16]	2928	1			T3	17		T4	26		T5	23
valid_sources[0x17]	2936	1			T3	15		T4	11		T5	29
valid_sources[0x18]	10486	1			T1	1		T3	15		T4	27
valid_sources[0x19]	2969	1			T3	9		T4	26		T5	21
valid_sources[0x1a]	3290	1			T3	28		T4	24		T5	19
valid_sources[0x1b]	12219	1			T3	10		T4	22		T5	15
valid_sources[0x1c]	3156	1			T3	20		T4	15		T5	23
valid_sources[0x1d]	2957	1			T3	16		T4	30		T5	19
valid_sources[0x1e]	3573	1			T3	23		T4	22		T5	18
valid_sources[0x1f]	3067	1			T3	24		T4	19		T5	25
valid_sources[0x20]	3131	1			T3	20		T4	28		T5	30
valid_sources[0x21]	3339	1			T3	5		T4	25		T5	51
valid_sources[0x22]	3016	1			T3	2		T4	18		T5	31
valid_sources[0x23]	2770	1			T3	14		T4	32		T5	14
valid_sources[0x24]	3167	1			T3	23		T4	21		T5	34
valid_sources[0x25]	2720	1			T3	19		T4	18		T5	8
valid_sources[0x26]	2874	1			T3	22		T4	32		T5	21
valid_sources[0x27]	2926	1			T3	8		T4	23		T5	19
valid_sources[0x28]	3032	1			T3	22		T4	18		T5	19
valid_sources[0x29]	3177	1			T3	25		T4	24		T5	17
valid_sources[0x2a]	3200	1			T3	24		T4	30		T5	26
valid_sources[0x2b]	3467	1			T3	29		T4	28		T5	36
valid_sources[0x2c]	2858	1			T3	28		T4	16		T5	19
valid_sources[0x2d]	2798	1			T3	12		T4	32		T5	41
valid_sources[0x2e]	2895	1			T3	31		T4	35		T5	21
valid_sources[0x2f]	2993	1			T3	27		T4	22		T5	23
valid_sources[0x30]	7877	1			T3	20		T4	21		T5	24
valid_sources[0x31]	3215	1			T3	10		T4	25		T5	36
valid_sources[0x32]	2854	1			T3	25		T4	40		T5	19
valid_sources[0x33]	3217	1			T3	29		T4	16		T5	20
valid_sources[0x34]	3033	1			T3	9		T4	14		T5	23
valid_sources[0x35]	2868	1			T3	25		T4	17		T5	19
valid_sources[0x36]	3005	1			T3	26		T4	19		T5	27
valid_sources[0x37]	2859	1			T3	18		T4	12		T5	25
valid_sources[0x38]	2987	1			T3	21		T4	32		T5	14
valid_sources[0x39]	3079	1			T3	43		T4	24		T5	5
valid_sources[0x3a]	2993	1			T3	15		T4	27		T5	49
valid_sources[0x3b]	3046	1			T3	26		T4	32		T5	22
valid_sources[0x3c]	2859	1			T3	19		T4	19		T5	14
valid_sources[0x3d]	3068	1			T3	15		T4	32		T5	23
valid_sources[0x3e]	3216	1			T3	22		T4	33		T5	20
valid_sources[0x3f]	2785	1			T3	6		T4	17		T5	25
valid_sources[0x40]	3035	1			T3	26		T4	10		T5	42
valid_sources[0x41]	6737	1			T3	21		T4	19		T5	40
valid_sources[0x42]	3099	1			T1	1		T3	7		T4	15
valid_sources[0x43]	2970	1			T3	23		T4	13		T5	31
valid_sources[0x44]	2994	1			T3	21		T4	28		T5	43
valid_sources[0x45]	2755	1			T3	27		T4	45		T5	4
valid_sources[0x46]	3332	1			T3	17		T4	16		T5	45
valid_sources[0x47]	2907	1			T3	43		T4	20		T5	23
valid_sources[0x48]	3057	1			T3	14		T4	20		T5	27
valid_sources[0x49]	3123	1			T3	26		T4	22		T5	14
valid_sources[0x4a]	4444	1			T3	26		T4	44		T5	52
valid_sources[0x4b]	2850	1			T3	9		T4	25		T5	16
valid_sources[0x4c]	2746	1			T3	37		T4	20		T5	40
valid_sources[0x4d]	2782	1			T3	3		T4	34		T5	54
valid_sources[0x4e]	3322	1			T3	19		T4	21		T5	14
valid_sources[0x4f]	2797	1			T3	7		T4	31		T5	24
valid_sources[0x50]	2984	1			T3	19		T4	14		T5	33
valid_sources[0x51]	17903	1			T3	19		T4	11		T5	12
valid_sources[0x52]	8152	1			T3	12		T4	18		T5	18
valid_sources[0x53]	3107	1			T3	17		T4	17		T5	11
valid_sources[0x54]	2911	1			T3	14		T4	21		T5	24
valid_sources[0x55]	3004	1			T3	24		T4	19		T5	14
valid_sources[0x56]	3048	1			T3	9		T4	21		T5	20
valid_sources[0x57]	3638	1			T3	16		T4	23		T5	63
valid_sources[0x58]	3424	1			T3	16		T4	33		T5	43
valid_sources[0x59]	2841	1			T3	12		T4	24		T5	20
valid_sources[0x5a]	2971	1			T3	15		T4	17		T5	13
valid_sources[0x5b]	2828	1			T3	5		T4	19		T5	12
valid_sources[0x5c]	2889	1			T3	22		T4	25		T5	38
valid_sources[0x5d]	3461	1			T3	18		T4	17		T5	48
valid_sources[0x5e]	3198	1			T3	6		T4	29		T5	19
valid_sources[0x5f]	2940	1			T3	14		T4	18		T5	19
valid_sources[0x60]	3228	1			T3	6		T4	17		T5	32
valid_sources[0x61]	2980	1			T3	24		T4	23		T5	14
valid_sources[0x62]	2589	1			T3	5		T4	21		T5	20
valid_sources[0x63]	3162	1			T3	27		T4	14		T5	22
valid_sources[0x64]	2857	1			T3	10		T4	18		T5	16
valid_sources[0x65]	3176	1			T3	22		T4	22		T5	35
valid_sources[0x66]	32820	1			T3	15		T4	30		T5	7
valid_sources[0x67]	3116	1			T3	6		T4	16		T5	22
valid_sources[0x68]	3110	1			T1	2		T3	21		T4	26
valid_sources[0x69]	2898	1			T3	43		T4	20		T5	15
valid_sources[0x6a]	2941	1			T3	12		T4	14		T5	38
valid_sources[0x6b]	2873	1			T3	21		T4	22		T5	57
valid_sources[0x6c]	3057	1			T3	11		T4	14		T5	10
valid_sources[0x6d]	2756	1			T3	12		T4	11		T5	28
valid_sources[0x6e]	3335	1			T3	28		T4	31		T5	19
valid_sources[0x6f]	2895	1			T3	18		T4	17		T5	27
valid_sources[0x70]	3435	1			T3	8		T4	25		T5	19
valid_sources[0x71]	3327	1			T3	18		T4	22		T5	41
valid_sources[0x72]	3206	1			T3	15		T4	29		T5	14
valid_sources[0x73]	2811	1			T3	27		T4	21		T5	14
valid_sources[0x74]	4451	1			T3	29		T4	17		T5	37
valid_sources[0x75]	3433	1			T3	14		T4	25		T5	13
valid_sources[0x76]	3005	1			T3	12		T4	19		T5	36
valid_sources[0x77]	2870	1			T3	8		T4	19		T5	7
valid_sources[0x78]	2876	1			T3	30		T4	18		T5	18
valid_sources[0x79]	2897	1			T3	17		T4	29		T5	22
valid_sources[0x7a]	3172	1			T3	32		T4	17		T5	15
valid_sources[0x7b]	2878	1			T3	39		T4	37		T5	48
valid_sources[0x7c]	3003	1			T3	16		T4	36		T5	9
valid_sources[0x7d]	3202	1			T3	18		T4	30		T5	40
valid_sources[0x7e]	3335	1			T3	21		T4	12		T5	24
valid_sources[0x7f]	3111	1			T1	2		T3	19		T4	24
valid_sources[0x80]	2876	1			T3	14		T4	18		T5	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

133372

1

T3

1663

T4

1658

T5

2034

values[0x0]

all_enables

biggest_size

56570

1

T1

2

T2

2

T3

474

values[0x1]

all_enables

biggest_size

49639

1

T1

1

T3

364

T4

335