Unified Coverage Report :: Module :: keymgr_dpe_csr_assert_fpv

Module : keymgr_dpe_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_dpe_csr_assert_0/keymgr_dpe_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_dpe_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_dpe_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.32	100.00	79.89	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_dpe_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	22	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	8986218	9861	0	0
intr_enable_rd_A	8986218	2370	0	0
key_version_rd_A	8986218	1831	0	0
reseed_interval_regwen_rd_A	8986218	796	0	0
salt_0_rd_A	8986218	1770	0	0
salt_1_rd_A	8986218	1861	0	0
salt_2_rd_A	8986218	1722	0	0
salt_3_rd_A	8986218	1648	0	0
salt_4_rd_A	8986218	1836	0	0
salt_5_rd_A	8986218	1770	0	0
salt_6_rd_A	8986218	1928	0	0
salt_7_rd_A	8986218	1807	0	0
sideload_clear_rd_A	8986218	1866	0	0
slot_policy_rd_A	8986218	2386	0	0
sw_binding_0_rd_A	8986218	1802	0	0
sw_binding_1_rd_A	8986218	1769	0	0
sw_binding_2_rd_A	8986218	1762	0	0
sw_binding_3_rd_A	8986218	1809	0	0
sw_binding_4_rd_A	8986218	1849	0	0
sw_binding_5_rd_A	8986218	1880	0	0
sw_binding_6_rd_A	8986218	1906	0	0
sw_binding_7_rd_A	8986218	1951	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8986218	9861	0	0
T21	16224	1	0	0
T22	1047	21	0	0
T39	8925	2	0	0
T40	8725	1	0	0
T41	6678	308	0	0
T42	1490	34	0	0
T43	10780	605	0	0
T48	0	487	0	0
T49	0	656	0	0
T77	15129	0	0	0
T78	7610	0	0	0
T79	1213	0	0	0
T96	0	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8986218	2370	0	0
T43	10780	0	0	0
T48	0	6	0	0
T51	1067	12	0	0
T70	8574	0	0	0
T71	13049	0	0	0
T77	15129	148	0	0
T78	7610	23	0	0
T79	1213	21	0	0
T87	5297	80	0	0
T97	1216	15	0	0
T98	1237	7	0	0
T99	0	17	0	0
T100	0	5	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8986218	1831	0	0
T43	10780	0	0	0
T48	11382	7	0	0
T49	0	8	0	0
T54	0	11	0	0
T55	0	20	0	0
T70	8574	0	0	0
T71	13049	0	0	0
T77	15129	193	0	0
T78	7610	40	0	0
T79	1213	0	0	0
T80	821	0	0	0
T87	5297	27	0	0
T99	1274	0	0	0
T101	0	13	0	0
T102	0	94	0	0
T103	0	4	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8986218	796	0	0
T43	10780	0	0	0
T48	11382	15	0	0
T49	0	23	0	0
T54	0	8	0	0
T55	0	23	0	0
T70	8574	0	0	0
T71	13049	0	0	0
T77	15129	195	0	0
T78	7610	7	0	0
T79	1213	0	0	0
T80	821	0	0	0
T87	5297	31	0	0
T99	1274	0	0	0
T101	0	4	0	0
T104	0	4	0	0
T105	0	9	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8986218	1770	0	0
T43	10780	0	0	0
T48	11382	22	0	0
T49	0	4	0	0
T55	0	11	0	0
T70	8574	0	0	0
T71	13049	0	0	0
T77	15129	185	0	0
T78	7610	31	0	0
T79	1213	0	0	0
T80	821	0	0	0
T87	5297	19	0	0
T99	1274	0	0	0
T101	0	15	0	0
T102	0	123	0	0
T103	0	13	0	0
T104	0	8	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8986218	1861	0	0
T43	10780	0	0	0
T48	11382	4	0	0
T49	0	4	0	0
T54	0	1	0	0
T55	0	4	0	0
T70	8574	0	0	0
T71	13049	0	0	0
T77	15129	170	0	0
T78	7610	78	0	0
T79	1213	0	0	0
T80	821	0	0	0
T85	0	6	0	0
T87	5297	43	0	0
T99	1274	0	0	0
T101	0	5	0	0
T102	0	125	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8986218	1722	0	0
T43	10780	0	0	0
T48	11382	1	0	0
T54	0	1	0	0
T55	0	11	0	0
T70	8574	0	0	0
T71	13049	0	0	0
T77	15129	184	0	0
T78	7610	18	0	0
T79	1213	0	0	0
T80	821	0	0	0
T85	0	8	0	0
T87	5297	5	0	0
T99	1274	0	0	0
T101	0	7	0	0
T102	0	97	0	0
T103	0	24	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8986218	1648	0	0
T43	10780	0	0	0
T48	11382	5	0	0
T54	0	10	0	0
T55	0	10	0	0
T70	8574	0	0	0
T71	13049	0	0	0
T77	15129	174	0	0
T78	7610	13	0	0
T79	1213	0	0	0
T80	821	0	0	0
T87	5297	12	0	0
T99	1274	0	0	0
T101	0	5	0	0
T102	0	135	0	0
T103	0	17	0	0
T104	0	20	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8986218	1836	0	0
T43	10780	0	0	0
T48	11382	0	0	0
T55	0	14	0	0
T70	8574	0	0	0
T71	13049	0	0	0
T77	15129	178	0	0
T78	7610	50	0	0
T79	1213	0	0	0
T80	821	0	0	0
T87	5297	37	0	0
T99	1274	0	0	0
T101	0	7	0	0
T102	0	127	0	0
T104	0	4	0	0
T105	0	3	0	0
T106	0	2	0	0
T107	0	28	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8986218	1770	0	0
T43	10780	0	0	0
T48	11382	9	0	0
T49	0	8	0	0
T54	0	4	0	0
T55	0	12	0	0
T70	8574	0	0	0
T71	13049	0	0	0
T77	15129	160	0	0
T78	7610	50	0	0
T79	1213	0	0	0
T80	821	0	0	0
T85	0	5	0	0
T87	5297	33	0	0
T99	1274	0	0	0
T102	0	144	0	0
T103	0	11	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8986218	1928	0	0
T43	10780	0	0	0
T48	11382	17	0	0
T54	0	17	0	0
T55	0	13	0	0
T70	8574	0	0	0
T71	13049	0	0	0
T77	15129	182	0	0
T78	7610	52	0	0
T79	1213	0	0	0
T80	821	0	0	0
T85	0	2	0	0
T87	5297	30	0	0
T99	1274	0	0	0
T101	0	6	0	0
T102	0	148	0	0
T104	0	28	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8986218	1807	0	0
T43	10780	0	0	0
T48	11382	8	0	0
T49	0	16	0	0
T54	0	8	0	0
T55	0	18	0	0
T70	8574	0	0	0
T71	13049	0	0	0
T77	15129	177	0	0
T78	7610	38	0	0
T79	1213	0	0	0
T80	821	0	0	0
T85	0	6	0	0
T96	1146	0	0	0
T99	1274	0	0	0
T101	0	6	0	0
T102	0	134	0	0
T103	0	12	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8986218	1866	0	0
T43	10780	0	0	0
T48	11382	0	0	0
T54	0	6	0	0
T55	0	14	0	0
T70	8574	0	0	0
T71	13049	0	0	0
T77	15129	162	0	0
T78	7610	25	0	0
T79	1213	0	0	0
T80	821	0	0	0
T87	5297	50	0	0
T99	1274	0	0	0
T102	0	167	0	0
T103	0	1	0	0
T104	0	13	0	0
T105	0	17	0	0
T107	0	36	0	0

slot_policy_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8986218	2386	0	0
T43	10780	0	0	0
T48	11382	12	0	0
T49	0	1	0	0
T54	0	15	0	0
T55	0	16	0	0
T70	8574	0	0	0
T71	13049	0	0	0
T77	15129	186	0	0
T78	7610	36	0	0
T79	1213	0	0	0
T80	821	0	0	0
T87	5297	8	0	0
T99	1274	0	0	0
T101	0	5	0	0
T102	0	134	0	0
T103	0	19	0	0

sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8986218	1802	0	0
T43	10780	0	0	0
T48	11382	8	0	0
T49	0	9	0	0
T54	0	7	0	0
T55	0	11	0	0
T70	8574	0	0	0
T71	13049	0	0	0
T77	15129	191	0	0
T78	7610	61	0	0
T79	1213	0	0	0
T80	821	0	0	0
T85	0	7	0	0
T87	5297	52	0	0
T99	1274	0	0	0
T101	0	4	0	0
T102	0	154	0	0

sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8986218	1769	0	0
T43	10780	0	0	0
T48	11382	3	0	0
T49	0	19	0	0
T54	0	8	0	0
T55	0	2	0	0
T70	8574	0	0	0
T71	13049	0	0	0
T77	15129	174	0	0
T78	7610	18	0	0
T79	1213	0	0	0
T80	821	0	0	0
T85	0	7	0	0
T87	5297	30	0	0
T99	1274	0	0	0
T101	0	1	0	0
T102	0	141	0	0

sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8986218	1762	0	0
T43	10780	0	0	0
T48	11382	9	0	0
T49	0	7	0	0
T55	0	41	0	0
T70	8574	0	0	0
T71	13049	0	0	0
T77	15129	152	0	0
T78	7610	20	0	0
T79	1213	0	0	0
T80	821	0	0	0
T87	5297	17	0	0
T99	1274	0	0	0
T101	0	5	0	0
T102	0	144	0	0
T103	0	12	0	0
T104	0	17	0	0

sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8986218	1809	0	0
T43	10780	0	0	0
T48	11382	9	0	0
T49	0	4	0	0
T54	0	27	0	0
T55	0	19	0	0
T70	8574	0	0	0
T71	13049	0	0	0
T77	15129	183	0	0
T78	7610	33	0	0
T79	1213	0	0	0
T80	821	0	0	0
T85	0	5	0	0
T87	5297	24	0	0
T99	1274	0	0	0
T102	0	77	0	0
T103	0	17	0	0

sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8986218	1849	0	0
T43	10780	0	0	0
T48	11382	0	0	0
T49	0	13	0	0
T54	0	2	0	0
T55	0	11	0	0
T70	8574	0	0	0
T71	13049	0	0	0
T77	15129	182	0	0
T78	7610	46	0	0
T79	1213	0	0	0
T80	821	0	0	0
T87	5297	16	0	0
T99	1274	0	0	0
T101	0	12	0	0
T102	0	158	0	0
T103	0	26	0	0
T104	0	20	0	0

sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8986218	1880	0	0
T43	10780	0	0	0
T48	11382	6	0	0
T49	0	8	0	0
T54	0	4	0	0
T55	0	21	0	0
T70	8574	0	0	0
T71	13049	0	0	0
T77	15129	163	0	0
T78	7610	64	0	0
T79	1213	0	0	0
T80	821	0	0	0
T85	0	3	0	0
T87	5297	31	0	0
T99	1274	0	0	0
T102	0	136	0	0
T103	0	3	0	0

sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8986218	1906	0	0
T43	10780	0	0	0
T48	11382	14	0	0
T49	0	1	0	0
T54	0	1	0	0
T55	0	13	0	0
T70	8574	0	0	0
T71	13049	0	0	0
T77	15129	184	0	0
T78	7610	82	0	0
T79	1213	0	0	0
T80	821	0	0	0
T85	0	3	0	0
T87	5297	24	0	0
T99	1274	0	0	0
T101	0	6	0	0
T102	0	157	0	0

sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8986218	1951	0	0
T43	10780	0	0	0
T48	11382	11	0	0
T54	0	20	0	0
T55	0	22	0	0
T70	8574	0	0	0
T71	13049	0	0	0
T77	15129	191	0	0
T78	7610	78	0	0
T79	1213	0	0	0
T80	821	0	0	0
T87	5297	35	0	0
T99	1274	0	0	0
T101	0	6	0	0
T102	0	126	0	0
T103	0	9	0	0
T104	0	17	0	0