Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
76.26 97.60 90.64 57.52 76.92 94.97 98.34 17.82


Total test records in report: 308
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T257 /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.1473543607 Jun 08 01:52:27 PM PDT 24 Jun 08 01:52:30 PM PDT 24 309494560 ps
T258 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.1712377181 Jun 08 01:52:37 PM PDT 24 Jun 08 01:52:55 PM PDT 24 575742799 ps
T259 /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.2715167360 Jun 08 01:53:24 PM PDT 24 Jun 08 01:53:26 PM PDT 24 76441800 ps
T260 /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.2390651181 Jun 08 01:53:17 PM PDT 24 Jun 08 01:53:19 PM PDT 24 30461608 ps
T261 /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.3359414975 Jun 08 01:53:11 PM PDT 24 Jun 08 01:53:17 PM PDT 24 353383999 ps
T262 /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.79048737 Jun 08 01:53:21 PM PDT 24 Jun 08 01:53:23 PM PDT 24 361505472 ps
T263 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.1836269450 Jun 08 01:52:33 PM PDT 24 Jun 08 01:52:35 PM PDT 24 132567073 ps
T264 /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.3671935302 Jun 08 01:52:45 PM PDT 24 Jun 08 01:52:46 PM PDT 24 7849552 ps
T265 /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.2700714226 Jun 08 01:53:22 PM PDT 24 Jun 08 01:53:24 PM PDT 24 151971812 ps
T266 /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.3050027631 Jun 08 01:52:59 PM PDT 24 Jun 08 01:53:05 PM PDT 24 145156007 ps
T267 /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.2297436615 Jun 08 01:53:06 PM PDT 24 Jun 08 01:53:07 PM PDT 24 40032966 ps
T268 /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors.3455913791 Jun 08 01:52:02 PM PDT 24 Jun 08 01:52:07 PM PDT 24 171548241 ps
T269 /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.1477210086 Jun 08 01:53:26 PM PDT 24 Jun 08 01:53:31 PM PDT 24 483608330 ps
T270 /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.440558962 Jun 08 01:53:02 PM PDT 24 Jun 08 01:53:04 PM PDT 24 35575797 ps
T271 /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.2430790931 Jun 08 01:52:54 PM PDT 24 Jun 08 01:52:56 PM PDT 24 81263237 ps
T272 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.2648228024 Jun 08 01:52:33 PM PDT 24 Jun 08 01:52:35 PM PDT 24 73379182 ps
T273 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.2945411897 Jun 08 01:52:43 PM PDT 24 Jun 08 01:52:49 PM PDT 24 310534132 ps
T274 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.2945988200 Jun 08 01:52:12 PM PDT 24 Jun 08 01:52:14 PM PDT 24 41540858 ps
T275 /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.3005212349 Jun 08 01:53:40 PM PDT 24 Jun 08 01:53:41 PM PDT 24 39228947 ps
T276 /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.2480770526 Jun 08 01:52:52 PM PDT 24 Jun 08 01:52:54 PM PDT 24 40996491 ps
T277 /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.725615330 Jun 08 01:52:52 PM PDT 24 Jun 08 01:52:53 PM PDT 24 19770778 ps
T278 /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.2654673161 Jun 08 01:52:56 PM PDT 24 Jun 08 01:52:58 PM PDT 24 82776216 ps
T279 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.2989827978 Jun 08 01:52:32 PM PDT 24 Jun 08 01:52:36 PM PDT 24 403127662 ps
T280 /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.2325521095 Jun 08 01:52:33 PM PDT 24 Jun 08 01:52:35 PM PDT 24 103319637 ps
T281 /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.328476660 Jun 08 01:53:01 PM PDT 24 Jun 08 01:53:05 PM PDT 24 116392869 ps
T282 /workspace/coverage/cover_reg_top/12.keymgr_dpe_same_csr_outstanding.587502345 Jun 08 01:53:12 PM PDT 24 Jun 08 01:53:14 PM PDT 24 153385964 ps
T283 /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_rw.2734528219 Jun 08 01:52:58 PM PDT 24 Jun 08 01:52:59 PM PDT 24 57560213 ps
T284 /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.645096461 Jun 08 01:53:22 PM PDT 24 Jun 08 01:53:24 PM PDT 24 27074081 ps
T285 /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.3157991823 Jun 08 01:53:09 PM PDT 24 Jun 08 01:53:10 PM PDT 24 56366387 ps
T286 /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.479959428 Jun 08 01:53:13 PM PDT 24 Jun 08 01:53:15 PM PDT 24 49625358 ps
T287 /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.3424133322 Jun 08 01:53:21 PM PDT 24 Jun 08 01:53:24 PM PDT 24 79265651 ps
T288 /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.1183232353 Jun 08 01:53:28 PM PDT 24 Jun 08 01:53:31 PM PDT 24 167071162 ps
T46 /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.2648814081 Jun 08 01:53:17 PM PDT 24 Jun 08 01:53:21 PM PDT 24 137958967 ps
T289 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.2475062138 Jun 08 01:52:42 PM PDT 24 Jun 08 01:52:43 PM PDT 24 104192562 ps
T290 /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.310993234 Jun 08 01:53:29 PM PDT 24 Jun 08 01:53:30 PM PDT 24 14969065 ps
T291 /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors.4143490006 Jun 08 01:52:47 PM PDT 24 Jun 08 01:52:49 PM PDT 24 74774791 ps
T292 /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.2038714589 Jun 08 01:53:22 PM PDT 24 Jun 08 01:53:26 PM PDT 24 603561678 ps
T40 /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.1303307474 Jun 08 01:52:28 PM PDT 24 Jun 08 01:52:34 PM PDT 24 922963772 ps
T293 /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.4071067610 Jun 08 01:53:21 PM PDT 24 Jun 08 01:53:23 PM PDT 24 171002279 ps
T41 /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.2148507202 Jun 08 01:52:16 PM PDT 24 Jun 08 01:52:20 PM PDT 24 179213146 ps
T294 /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.799293460 Jun 08 01:52:47 PM PDT 24 Jun 08 01:52:49 PM PDT 24 53927884 ps
T295 /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.1536740191 Jun 08 01:53:17 PM PDT 24 Jun 08 01:53:19 PM PDT 24 462525105 ps
T296 /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.1644749566 Jun 08 01:53:25 PM PDT 24 Jun 08 01:53:26 PM PDT 24 22020336 ps
T297 /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.326363460 Jun 08 01:53:08 PM PDT 24 Jun 08 01:53:10 PM PDT 24 63553577 ps
T54 /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.1197199002 Jun 08 01:53:25 PM PDT 24 Jun 08 01:53:27 PM PDT 24 51298328 ps
T298 /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.2675869829 Jun 08 01:53:39 PM PDT 24 Jun 08 01:53:40 PM PDT 24 19535482 ps
T299 /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.512761110 Jun 08 01:53:01 PM PDT 24 Jun 08 01:53:03 PM PDT 24 211873283 ps
T300 /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.2233746549 Jun 08 01:53:18 PM PDT 24 Jun 08 01:53:19 PM PDT 24 15977717 ps
T301 /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.3766101002 Jun 08 01:52:50 PM PDT 24 Jun 08 01:52:52 PM PDT 24 109182706 ps
T52 /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.4113014462 Jun 08 01:52:55 PM PDT 24 Jun 08 01:53:00 PM PDT 24 616091246 ps
T302 /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.345328462 Jun 08 01:53:18 PM PDT 24 Jun 08 01:53:21 PM PDT 24 293774298 ps
T303 /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.913986455 Jun 08 01:52:56 PM PDT 24 Jun 08 01:52:57 PM PDT 24 15480293 ps
T304 /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.597037453 Jun 08 01:52:54 PM PDT 24 Jun 08 01:52:55 PM PDT 24 31439010 ps
T305 /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.2185841509 Jun 08 01:53:10 PM PDT 24 Jun 08 01:53:11 PM PDT 24 29797541 ps
T48 /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.3774288077 Jun 08 01:53:24 PM PDT 24 Jun 08 01:53:32 PM PDT 24 3447688139 ps
T306 /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.3516990311 Jun 08 01:52:27 PM PDT 24 Jun 08 01:52:33 PM PDT 24 1334706048 ps
T307 /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.1779899097 Jun 08 01:53:27 PM PDT 24 Jun 08 01:53:28 PM PDT 24 17652260 ps
T308 /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors.2802005366 Jun 08 01:53:22 PM PDT 24 Jun 08 01:53:24 PM PDT 24 143754921 ps

Test location /workspace/coverage/default/28.keymgr_dpe_smoke.1580604678
Short name T2
Test name
Test status
Simulation time 12273532393 ps
CPU time 51.6 seconds
Started Jun 08 01:46:51 PM PDT 24
Finished Jun 08 01:47:43 PM PDT 24
Peak memory 207824 kb
Host smart-cb4196e8-f2fe-4363-bfc1-e4446f05911a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580604678 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_smoke.1580604678
Directory /workspace/28.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_sec_cm.3611348806
Short name T6
Test name
Test status
Simulation time 436580806 ps
CPU time 5.47 seconds
Started Jun 08 01:46:44 PM PDT 24
Finished Jun 08 01:46:49 PM PDT 24
Peak memory 232812 kb
Host smart-c9f1c858-25d2-458d-b310-9022e493edf2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611348806 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_sec_cm.3611348806
Directory /workspace/2.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.3886010480
Short name T55
Test name
Test status
Simulation time 253691332 ps
CPU time 4.95 seconds
Started Jun 08 01:53:24 PM PDT 24
Finished Jun 08 01:53:30 PM PDT 24
Peak memory 212832 kb
Host smart-5b0df9d1-d19a-4f91-a25a-0ea696b32c8f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886010480 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.keymgr_dpe_shadow_reg_errors_with_csr_rw.3886010480
Directory /workspace/18.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.3860113967
Short name T31
Test name
Test status
Simulation time 31599250 ps
CPU time 2.1 seconds
Started Jun 08 01:52:15 PM PDT 24
Finished Jun 08 01:52:17 PM PDT 24
Peak memory 212840 kb
Host smart-ccb36ffb-001d-4a76-be1f-816ae5ab1e30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860113967 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_tl_errors.3
860113967
Directory /workspace/1.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/default/9.keymgr_dpe_smoke.2351492182
Short name T10
Test name
Test status
Simulation time 7946938095 ps
CPU time 14.51 seconds
Started Jun 08 01:46:33 PM PDT 24
Finished Jun 08 01:46:47 PM PDT 24
Peak memory 208240 kb
Host smart-63bf1fb1-917d-467c-aaae-0feaf03346d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351492182 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_smoke.2351492182
Directory /workspace/9.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.41132996
Short name T57
Test name
Test status
Simulation time 213597508 ps
CPU time 5.35 seconds
Started Jun 08 01:53:13 PM PDT 24
Finished Jun 08 01:53:18 PM PDT 24
Peak memory 213148 kb
Host smart-6f73c9f4-f6a5-4a69-b524-467b10b5d983
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41132996 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_T
EST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 13.keymgr_dpe_shadow_reg_errors_with_csr_rw.41132996
Directory /workspace/13.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.3914971390
Short name T20
Test name
Test status
Simulation time 190944786 ps
CPU time 3.93 seconds
Started Jun 08 01:52:44 PM PDT 24
Finished Jun 08 01:52:48 PM PDT 24
Peak memory 212684 kb
Host smart-a4fdd8ce-92ef-4237-8892-1944c8fe9947
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914971390 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe
_tl_intg_err.3914971390
Directory /workspace/4.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/22.keymgr_dpe_alert_test.3254392951
Short name T104
Test name
Test status
Simulation time 38295325 ps
CPU time 0.81 seconds
Started Jun 08 01:46:46 PM PDT 24
Finished Jun 08 01:46:47 PM PDT 24
Peak memory 205528 kb
Host smart-aa8d4c2e-fd69-45b9-8057-d840acae23c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254392951 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_alert_test.
3254392951
Directory /workspace/22.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.2118548375
Short name T100
Test name
Test status
Simulation time 22687621 ps
CPU time 0.73 seconds
Started Jun 08 01:53:12 PM PDT 24
Finished Jun 08 01:53:13 PM PDT 24
Peak memory 204304 kb
Host smart-b95ee430-5bad-486c-8d57-c84127422514
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118548375 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_intr_test.
2118548375
Directory /workspace/12.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/default/31.keymgr_dpe_smoke.1235054562
Short name T8
Test name
Test status
Simulation time 9812352935 ps
CPU time 21.72 seconds
Started Jun 08 01:46:54 PM PDT 24
Finished Jun 08 01:47:16 PM PDT 24
Peak memory 208304 kb
Host smart-a520fcf4-a296-4e97-9125-4a52a5bb1442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235054562 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_smoke.1235054562
Directory /workspace/31.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.1472920989
Short name T223
Test name
Test status
Simulation time 626927079 ps
CPU time 5.59 seconds
Started Jun 08 01:53:09 PM PDT 24
Finished Jun 08 01:53:15 PM PDT 24
Peak memory 212844 kb
Host smart-fde49bfb-66d7-42db-9f41-d3cf0f75d910
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472920989 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_tl_errors.
1472920989
Directory /workspace/12.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.3774288077
Short name T48
Test name
Test status
Simulation time 3447688139 ps
CPU time 8.11 seconds
Started Jun 08 01:53:24 PM PDT 24
Finished Jun 08 01:53:32 PM PDT 24
Peak memory 212772 kb
Host smart-bd417aad-be84-4e2f-9ea2-8463827edb91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774288077 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dp
e_tl_intg_err.3774288077
Directory /workspace/16.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.3346206996
Short name T44
Test name
Test status
Simulation time 708812044 ps
CPU time 2.85 seconds
Started Jun 08 01:52:48 PM PDT 24
Finished Jun 08 01:52:51 PM PDT 24
Peak memory 204496 kb
Host smart-9d82f1d2-dd0e-4896-b0d5-3480fdf9cb77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346206996 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe
_tl_intg_err.3346206996
Directory /workspace/5.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.954097278
Short name T18
Test name
Test status
Simulation time 640077719 ps
CPU time 4.74 seconds
Started Jun 08 01:53:12 PM PDT 24
Finished Jun 08 01:53:17 PM PDT 24
Peak memory 204448 kb
Host smart-ec64069e-066a-44ba-a0a3-3e997289d02d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954097278 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe
_tl_intg_err.954097278
Directory /workspace/11.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_intg_err.3270516150
Short name T51
Test name
Test status
Simulation time 216784980 ps
CPU time 3.13 seconds
Started Jun 08 01:53:24 PM PDT 24
Finished Jun 08 01:53:28 PM PDT 24
Peak memory 213624 kb
Host smart-37e6e622-55f1-41fa-aa16-c304cd12fc5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270516150 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dp
e_tl_intg_err.3270516150
Directory /workspace/17.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.3578350772
Short name T167
Test name
Test status
Simulation time 46793866 ps
CPU time 0.83 seconds
Started Jun 08 01:52:02 PM PDT 24
Finished Jun 08 01:52:03 PM PDT 24
Peak memory 204340 kb
Host smart-3dae97ba-521f-4bca-bced-996979781a3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578350772 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_intr_test.3
578350772
Directory /workspace/0.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.2148507202
Short name T41
Test name
Test status
Simulation time 179213146 ps
CPU time 3.87 seconds
Started Jun 08 01:52:16 PM PDT 24
Finished Jun 08 01:52:20 PM PDT 24
Peak memory 212664 kb
Host smart-0c41967e-6299-4e72-bae8-94d16eb11543
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148507202 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe
_tl_intg_err.2148507202
Directory /workspace/1.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_intg_err.1564592533
Short name T43
Test name
Test status
Simulation time 224736895 ps
CPU time 3.94 seconds
Started Jun 08 01:53:13 PM PDT 24
Finished Jun 08 01:53:17 PM PDT 24
Peak memory 211932 kb
Host smart-81ff09e3-e25f-4e4d-bdaa-43f09ea5c688
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564592533 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dp
e_tl_intg_err.1564592533
Directory /workspace/12.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.3199903716
Short name T53
Test name
Test status
Simulation time 174029481 ps
CPU time 3.4 seconds
Started Jun 08 01:52:46 PM PDT 24
Finished Jun 08 01:52:50 PM PDT 24
Peak memory 213236 kb
Host smart-947f3b63-87a2-4a5e-8aba-f473dcf3c06c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199903716 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe
_tl_intg_err.3199903716
Directory /workspace/6.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.1340362035
Short name T50
Test name
Test status
Simulation time 494403984 ps
CPU time 3.7 seconds
Started Jun 08 01:53:02 PM PDT 24
Finished Jun 08 01:53:06 PM PDT 24
Peak memory 212724 kb
Host smart-678607aa-f968-49ca-9560-71754140f09c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340362035 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe
_tl_intg_err.1340362035
Directory /workspace/9.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_sec_cm.3064640527
Short name T22
Test name
Test status
Simulation time 1476497840 ps
CPU time 11.98 seconds
Started Jun 08 01:46:37 PM PDT 24
Finished Jun 08 01:46:50 PM PDT 24
Peak memory 229664 kb
Host smart-e176bde1-2cd9-4977-830c-22c2d9135c27
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064640527 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_sec_cm.3064640527
Directory /workspace/0.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.1343129628
Short name T61
Test name
Test status
Simulation time 58176522 ps
CPU time 1.23 seconds
Started Jun 08 01:53:14 PM PDT 24
Finished Jun 08 01:53:16 PM PDT 24
Peak memory 204472 kb
Host smart-2f20311f-0699-410e-8933-c30991ea92fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343129628 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_mem_rw_with_rand_reset.1343129628
Directory /workspace/13.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_dpe_smoke.1811112553
Short name T95
Test name
Test status
Simulation time 5195719425 ps
CPU time 21.58 seconds
Started Jun 08 01:46:45 PM PDT 24
Finished Jun 08 01:47:07 PM PDT 24
Peak memory 207524 kb
Host smart-9a3cb004-ce21-441d-bf9c-807391771fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811112553 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_smoke.1811112553
Directory /workspace/1.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/10.keymgr_dpe_smoke.4176449493
Short name T97
Test name
Test status
Simulation time 2351140597 ps
CPU time 19.36 seconds
Started Jun 08 01:46:46 PM PDT 24
Finished Jun 08 01:47:06 PM PDT 24
Peak memory 208136 kb
Host smart-e88ec201-dcbc-405f-88fc-9e646afff259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176449493 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_smoke.4176449493
Directory /workspace/10.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/11.keymgr_dpe_smoke.1707808468
Short name T69
Test name
Test status
Simulation time 6961878566 ps
CPU time 57.57 seconds
Started Jun 08 01:46:43 PM PDT 24
Finished Jun 08 01:47:41 PM PDT 24
Peak memory 207740 kb
Host smart-107a42f5-0508-4871-963e-81698da53bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707808468 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_smoke.1707808468
Directory /workspace/11.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/12.keymgr_dpe_smoke.3658587351
Short name T11
Test name
Test status
Simulation time 1014187178 ps
CPU time 17.43 seconds
Started Jun 08 01:46:40 PM PDT 24
Finished Jun 08 01:46:58 PM PDT 24
Peak memory 207944 kb
Host smart-a4343f0c-c32a-47f7-ba04-41ed71441b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658587351 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_smoke.3658587351
Directory /workspace/12.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/13.keymgr_dpe_smoke.4215046901
Short name T12
Test name
Test status
Simulation time 4545918430 ps
CPU time 28.83 seconds
Started Jun 08 01:46:41 PM PDT 24
Finished Jun 08 01:47:10 PM PDT 24
Peak memory 207756 kb
Host smart-d53437a3-7e3e-482f-8afc-cd212f1787f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215046901 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_smoke.4215046901
Directory /workspace/13.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/14.keymgr_dpe_smoke.2688162990
Short name T73
Test name
Test status
Simulation time 46576631714 ps
CPU time 331.19 seconds
Started Jun 08 01:46:40 PM PDT 24
Finished Jun 08 01:52:12 PM PDT 24
Peak memory 207516 kb
Host smart-7509f34e-32f9-4af4-b08c-d5a85a15418c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688162990 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_smoke.2688162990
Directory /workspace/14.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/15.keymgr_dpe_smoke.612483681
Short name T138
Test name
Test status
Simulation time 4146809572 ps
CPU time 20.2 seconds
Started Jun 08 01:46:46 PM PDT 24
Finished Jun 08 01:47:06 PM PDT 24
Peak memory 207676 kb
Host smart-b8bb414c-419f-4882-8f8c-9720229a9d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612483681 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_smoke.612483681
Directory /workspace/15.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/16.keymgr_dpe_smoke.1518762858
Short name T93
Test name
Test status
Simulation time 1285900325 ps
CPU time 25.45 seconds
Started Jun 08 01:46:38 PM PDT 24
Finished Jun 08 01:47:03 PM PDT 24
Peak memory 206340 kb
Host smart-f2bcfe6e-5971-4f47-a741-4add58c68f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518762858 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_smoke.1518762858
Directory /workspace/16.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_smoke.3525705084
Short name T90
Test name
Test status
Simulation time 241217662 ps
CPU time 12.42 seconds
Started Jun 08 01:46:39 PM PDT 24
Finished Jun 08 01:46:51 PM PDT 24
Peak memory 208028 kb
Host smart-6e3c1b9b-0284-4fc2-8d4c-aadc79059cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525705084 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_smoke.3525705084
Directory /workspace/2.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/26.keymgr_dpe_smoke.772204951
Short name T71
Test name
Test status
Simulation time 270081804 ps
CPU time 8.8 seconds
Started Jun 08 01:47:02 PM PDT 24
Finished Jun 08 01:47:11 PM PDT 24
Peak memory 206020 kb
Host smart-e550580c-2c48-4eb3-b980-3c629fbc65f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772204951 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_smoke.772204951
Directory /workspace/26.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/27.keymgr_dpe_smoke.802785647
Short name T72
Test name
Test status
Simulation time 974407290 ps
CPU time 10.37 seconds
Started Jun 08 01:46:45 PM PDT 24
Finished Jun 08 01:46:55 PM PDT 24
Peak memory 208652 kb
Host smart-c03100b7-0785-4212-9400-bedadaacab09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802785647 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_smoke.802785647
Directory /workspace/27.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/30.keymgr_dpe_smoke.1238281054
Short name T13
Test name
Test status
Simulation time 2260361049 ps
CPU time 17.66 seconds
Started Jun 08 01:46:44 PM PDT 24
Finished Jun 08 01:47:02 PM PDT 24
Peak memory 207904 kb
Host smart-21175211-c5d0-42a9-a687-5b9c3c16d3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238281054 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_smoke.1238281054
Directory /workspace/30.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/35.keymgr_dpe_smoke.3557429886
Short name T81
Test name
Test status
Simulation time 52113515803 ps
CPU time 411.25 seconds
Started Jun 08 01:46:56 PM PDT 24
Finished Jun 08 01:53:48 PM PDT 24
Peak memory 208376 kb
Host smart-6ab365a4-b8f1-40e9-bea1-f1f56924d558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557429886 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_smoke.3557429886
Directory /workspace/35.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/4.keymgr_dpe_smoke.1130181383
Short name T1
Test name
Test status
Simulation time 26211664310 ps
CPU time 204.28 seconds
Started Jun 08 01:46:38 PM PDT 24
Finished Jun 08 01:50:03 PM PDT 24
Peak memory 207556 kb
Host smart-47c9a5ef-5690-4136-b8d8-06e5bb11159c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130181383 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_smoke.1130181383
Directory /workspace/4.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/41.keymgr_dpe_smoke.2581399501
Short name T91
Test name
Test status
Simulation time 1913315695 ps
CPU time 19.53 seconds
Started Jun 08 01:47:03 PM PDT 24
Finished Jun 08 01:47:23 PM PDT 24
Peak memory 206620 kb
Host smart-371b8692-a646-4a40-abe3-306da22e39e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581399501 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_smoke.2581399501
Directory /workspace/41.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.736434605
Short name T34
Test name
Test status
Simulation time 458886500 ps
CPU time 3.01 seconds
Started Jun 08 01:52:08 PM PDT 24
Finished Jun 08 01:52:11 PM PDT 24
Peak memory 204496 kb
Host smart-ae8b0415-7a0a-43c8-a96f-120215634179
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736434605 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr
_aliasing.736434605
Directory /workspace/0.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.3714894325
Short name T204
Test name
Test status
Simulation time 312508625 ps
CPU time 5.68 seconds
Started Jun 08 01:52:09 PM PDT 24
Finished Jun 08 01:52:15 PM PDT 24
Peak memory 204476 kb
Host smart-7d53e53f-50db-4c9f-989b-a4a57c31fb92
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714894325 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_bit_bash.3714894325
Directory /workspace/0.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_hw_reset.2131432450
Short name T200
Test name
Test status
Simulation time 39932374 ps
CPU time 0.96 seconds
Started Jun 08 01:52:08 PM PDT 24
Finished Jun 08 01:52:09 PM PDT 24
Peak memory 204524 kb
Host smart-00666842-8c7d-4e29-b135-1ad5dfc023ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131432450 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_hw_reset.2131432450
Directory /workspace/0.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.2945988200
Short name T274
Test name
Test status
Simulation time 41540858 ps
CPU time 1.82 seconds
Started Jun 08 01:52:12 PM PDT 24
Finished Jun 08 01:52:14 PM PDT 24
Peak memory 215680 kb
Host smart-f83372ec-f3ff-4d1c-9da8-5d3bcdd6aa91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945988200 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_mem_rw_with_rand_reset.2945988200
Directory /workspace/0.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.2888592124
Short name T66
Test name
Test status
Simulation time 44402718 ps
CPU time 1.13 seconds
Started Jun 08 01:52:08 PM PDT 24
Finished Jun 08 01:52:09 PM PDT 24
Peak memory 204464 kb
Host smart-61a60041-5b44-42c0-b56a-dccd2477d78c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888592124 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_rw.2
888592124
Directory /workspace/0.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.431000224
Short name T169
Test name
Test status
Simulation time 81017824 ps
CPU time 2.15 seconds
Started Jun 08 01:52:11 PM PDT 24
Finished Jun 08 01:52:13 PM PDT 24
Peak memory 204420 kb
Host smart-af2d29f7-9362-4e8e-b6ca-9ad55ffee8dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431000224 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.ke
ymgr_dpe_same_csr_outstanding.431000224
Directory /workspace/0.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors.3455913791
Short name T268
Test name
Test status
Simulation time 171548241 ps
CPU time 4.26 seconds
Started Jun 08 01:52:02 PM PDT 24
Finished Jun 08 01:52:07 PM PDT 24
Peak memory 213004 kb
Host smart-14e2ee3a-0da7-4dd8-80b8-297ed0356c89
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455913791 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keym
gr_dpe_shadow_reg_errors.3455913791
Directory /workspace/0.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors_with_csr_rw.603909458
Short name T196
Test name
Test status
Simulation time 134426630 ps
CPU time 4.78 seconds
Started Jun 08 01:52:05 PM PDT 24
Finished Jun 08 01:52:10 PM PDT 24
Peak memory 218120 kb
Host smart-f512fe3c-e249-40d6-9e95-365d9b57db01
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603909458 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.keymgr_dpe_shadow_reg_errors_with_csr_rw.603909458
Directory /workspace/0.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.4042285485
Short name T203
Test name
Test status
Simulation time 453460929 ps
CPU time 4.42 seconds
Started Jun 08 01:52:05 PM PDT 24
Finished Jun 08 01:52:09 PM PDT 24
Peak memory 212676 kb
Host smart-f9475018-1f79-478c-9f8b-ae6eac3571d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042285485 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_tl_errors.4
042285485
Directory /workspace/0.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.2216603228
Short name T250
Test name
Test status
Simulation time 156137739 ps
CPU time 2.89 seconds
Started Jun 08 01:52:03 PM PDT 24
Finished Jun 08 01:52:06 PM PDT 24
Peak memory 212784 kb
Host smart-dc5fe3c3-329f-4cc4-a34b-3ec692475fcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216603228 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe
_tl_intg_err.2216603228
Directory /workspace/0.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.2409795259
Short name T87
Test name
Test status
Simulation time 1004639640 ps
CPU time 2.98 seconds
Started Jun 08 01:52:27 PM PDT 24
Finished Jun 08 01:52:30 PM PDT 24
Peak memory 204436 kb
Host smart-a765aaf5-7eb6-4c0d-9c79-6a0ceb7169f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409795259 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_aliasing.2409795259
Directory /workspace/1.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.742646505
Short name T214
Test name
Test status
Simulation time 300948898 ps
CPU time 8.91 seconds
Started Jun 08 01:52:31 PM PDT 24
Finished Jun 08 01:52:40 PM PDT 24
Peak memory 204512 kb
Host smart-3e0ddc6e-20e3-4699-b70e-d16c7e0f366c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742646505 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr
_bit_bash.742646505
Directory /workspace/1.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.2296926059
Short name T217
Test name
Test status
Simulation time 55998810 ps
CPU time 0.88 seconds
Started Jun 08 01:52:21 PM PDT 24
Finished Jun 08 01:52:23 PM PDT 24
Peak memory 204364 kb
Host smart-d1511d2f-f99b-4630-aeff-034bc3c09fb6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296926059 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_hw_reset.2296926059
Directory /workspace/1.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.3284337700
Short name T194
Test name
Test status
Simulation time 25941869 ps
CPU time 1.22 seconds
Started Jun 08 01:52:32 PM PDT 24
Finished Jun 08 01:52:34 PM PDT 24
Peak memory 212744 kb
Host smart-cde50e8f-41bc-48ff-93e6-5e604a54b178
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284337700 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_mem_rw_with_rand_reset.3284337700
Directory /workspace/1.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.2624686400
Short name T239
Test name
Test status
Simulation time 45893289 ps
CPU time 1.37 seconds
Started Jun 08 01:52:20 PM PDT 24
Finished Jun 08 01:52:22 PM PDT 24
Peak memory 204540 kb
Host smart-48686150-dbd3-4716-aac3-7d8cd3fe029e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624686400 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_rw.2
624686400
Directory /workspace/1.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.2547574376
Short name T101
Test name
Test status
Simulation time 14082716 ps
CPU time 0.78 seconds
Started Jun 08 01:52:27 PM PDT 24
Finished Jun 08 01:52:28 PM PDT 24
Peak memory 204296 kb
Host smart-e1c0abf2-317a-4823-9c53-8f2fca6c3321
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547574376 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_intr_test.2
547574376
Directory /workspace/1.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.309136830
Short name T240
Test name
Test status
Simulation time 219537298 ps
CPU time 1.56 seconds
Started Jun 08 01:52:32 PM PDT 24
Finished Jun 08 01:52:34 PM PDT 24
Peak memory 204412 kb
Host smart-d1d3b706-fdb3-42a0-955e-23da8190a5a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309136830 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.ke
ymgr_dpe_same_csr_outstanding.309136830
Directory /workspace/1.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors.2308721636
Short name T231
Test name
Test status
Simulation time 133374361 ps
CPU time 1.62 seconds
Started Jun 08 01:52:11 PM PDT 24
Finished Jun 08 01:52:13 PM PDT 24
Peak memory 212872 kb
Host smart-0bacba6a-baaa-40cf-9c7f-8b4e9efbd673
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308721636 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keym
gr_dpe_shadow_reg_errors.2308721636
Directory /workspace/1.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.3533736123
Short name T186
Test name
Test status
Simulation time 559033716 ps
CPU time 3.16 seconds
Started Jun 08 01:52:16 PM PDT 24
Finished Jun 08 01:52:19 PM PDT 24
Peak memory 213072 kb
Host smart-4c76fb7b-5211-48b5-a599-46705d0b85c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533736123 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.keymgr_dpe_shadow_reg_errors_with_csr_rw.3533736123
Directory /workspace/1.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.2185841509
Short name T305
Test name
Test status
Simulation time 29797541 ps
CPU time 1.73 seconds
Started Jun 08 01:53:10 PM PDT 24
Finished Jun 08 01:53:11 PM PDT 24
Peak memory 212808 kb
Host smart-48f15c29-b904-4b2e-85f8-6a83ec1f9344
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185841509 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_mem_rw_with_rand_reset.2185841509
Directory /workspace/10.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.1671774874
Short name T172
Test name
Test status
Simulation time 73210377 ps
CPU time 0.96 seconds
Started Jun 08 01:53:12 PM PDT 24
Finished Jun 08 01:53:13 PM PDT 24
Peak memory 204364 kb
Host smart-35cd5b60-8ea0-4b01-90b3-7211490c8a21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671774874 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_rw.
1671774874
Directory /workspace/10.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.1884357033
Short name T37
Test name
Test status
Simulation time 26057341 ps
CPU time 0.69 seconds
Started Jun 08 01:53:09 PM PDT 24
Finished Jun 08 01:53:10 PM PDT 24
Peak memory 204384 kb
Host smart-d3f845ef-4d04-4716-9a64-97f20020b3e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884357033 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_intr_test.
1884357033
Directory /workspace/10.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.60008697
Short name T174
Test name
Test status
Simulation time 116108995 ps
CPU time 1.86 seconds
Started Jun 08 01:53:09 PM PDT 24
Finished Jun 08 01:53:11 PM PDT 24
Peak memory 204504 kb
Host smart-acf79d10-4865-4ed3-8964-e01869dd1d83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60008697 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=k
eymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ke
ymgr_dpe_same_csr_outstanding.60008697
Directory /workspace/10.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.1385239637
Short name T243
Test name
Test status
Simulation time 554207931 ps
CPU time 4.08 seconds
Started Jun 08 01:53:05 PM PDT 24
Finished Jun 08 01:53:09 PM PDT 24
Peak memory 213040 kb
Host smart-be04994f-3af8-4b18-a8c9-fa6b982628be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385239637 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.key
mgr_dpe_shadow_reg_errors.1385239637
Directory /workspace/10.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.3272183430
Short name T180
Test name
Test status
Simulation time 1401557391 ps
CPU time 6.02 seconds
Started Jun 08 01:53:05 PM PDT 24
Finished Jun 08 01:53:12 PM PDT 24
Peak memory 213024 kb
Host smart-3d3d4467-9f2d-49c6-86a7-5c4799eef7ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272183430 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.keymgr_dpe_shadow_reg_errors_with_csr_rw.3272183430
Directory /workspace/10.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.734520726
Short name T33
Test name
Test status
Simulation time 53503207 ps
CPU time 2.16 seconds
Started Jun 08 01:53:04 PM PDT 24
Finished Jun 08 01:53:07 PM PDT 24
Peak memory 212780 kb
Host smart-423ea4fa-9dd5-4cde-9897-416e81aad492
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734520726 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_tl_errors.734520726
Directory /workspace/10.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.1924278346
Short name T47
Test name
Test status
Simulation time 708821084 ps
CPU time 3.62 seconds
Started Jun 08 01:53:03 PM PDT 24
Finished Jun 08 01:53:07 PM PDT 24
Peak memory 213724 kb
Host smart-e3b724ef-94a8-4e1d-b9f3-310f26af6e29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924278346 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dp
e_tl_intg_err.1924278346
Directory /workspace/10.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.2684037194
Short name T176
Test name
Test status
Simulation time 116820450 ps
CPU time 1.08 seconds
Started Jun 08 01:53:09 PM PDT 24
Finished Jun 08 01:53:11 PM PDT 24
Peak memory 204400 kb
Host smart-1661d817-b3b1-4112-a750-4a741e832c94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684037194 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_mem_rw_with_rand_reset.2684037194
Directory /workspace/11.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.191030927
Short name T199
Test name
Test status
Simulation time 14487600 ps
CPU time 0.87 seconds
Started Jun 08 01:53:10 PM PDT 24
Finished Jun 08 01:53:11 PM PDT 24
Peak memory 204388 kb
Host smart-db947c21-d03a-4ffd-826f-861ca4e1d72f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191030927 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_rw.191030927
Directory /workspace/11.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.1490243431
Short name T216
Test name
Test status
Simulation time 12652741 ps
CPU time 0.74 seconds
Started Jun 08 01:53:09 PM PDT 24
Finished Jun 08 01:53:10 PM PDT 24
Peak memory 204320 kb
Host smart-f4fc5454-457d-4332-8dbd-d45330227ca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490243431 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_intr_test.
1490243431
Directory /workspace/11.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_same_csr_outstanding.2382577080
Short name T225
Test name
Test status
Simulation time 77738584 ps
CPU time 2.12 seconds
Started Jun 08 01:53:13 PM PDT 24
Finished Jun 08 01:53:15 PM PDT 24
Peak memory 203780 kb
Host smart-a5280109-45bb-48ab-b4ef-4fd2694b2a4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382577080 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_dpe_same_csr_outstanding.2382577080
Directory /workspace/11.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.3157991823
Short name T285
Test name
Test status
Simulation time 56366387 ps
CPU time 1.41 seconds
Started Jun 08 01:53:09 PM PDT 24
Finished Jun 08 01:53:10 PM PDT 24
Peak memory 213092 kb
Host smart-2e28705f-a159-43fb-971a-acc6e9899817
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157991823 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.key
mgr_dpe_shadow_reg_errors.3157991823
Directory /workspace/11.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.630008171
Short name T173
Test name
Test status
Simulation time 238979243 ps
CPU time 7.79 seconds
Started Jun 08 01:53:12 PM PDT 24
Finished Jun 08 01:53:20 PM PDT 24
Peak memory 212984 kb
Host smart-ff2cfd97-d95b-443e-a4e1-17883f79234a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630008171 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.keymgr_dpe_shadow_reg_errors_with_csr_rw.630008171
Directory /workspace/11.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.2641801947
Short name T238
Test name
Test status
Simulation time 78039209 ps
CPU time 4.02 seconds
Started Jun 08 01:53:09 PM PDT 24
Finished Jun 08 01:53:13 PM PDT 24
Peak memory 216344 kb
Host smart-253ef0fb-8953-4cf3-aad7-9ca9825a0e33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641801947 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_tl_errors.
2641801947
Directory /workspace/11.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.326363460
Short name T297
Test name
Test status
Simulation time 63553577 ps
CPU time 1.06 seconds
Started Jun 08 01:53:08 PM PDT 24
Finished Jun 08 01:53:10 PM PDT 24
Peak memory 204436 kb
Host smart-d7114fd1-ac71-466a-8637-5428b45d4383
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326363460 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_mem_rw_with_rand_reset.326363460
Directory /workspace/12.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.3563919274
Short name T208
Test name
Test status
Simulation time 36824962 ps
CPU time 0.94 seconds
Started Jun 08 01:53:12 PM PDT 24
Finished Jun 08 01:53:13 PM PDT 24
Peak memory 204340 kb
Host smart-3dd67e17-0844-4f36-8026-e1c1f882e01c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563919274 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_rw.
3563919274
Directory /workspace/12.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_same_csr_outstanding.587502345
Short name T282
Test name
Test status
Simulation time 153385964 ps
CPU time 1.54 seconds
Started Jun 08 01:53:12 PM PDT 24
Finished Jun 08 01:53:14 PM PDT 24
Peak memory 204452 kb
Host smart-106aa12d-f1b7-4cc1-8854-1500e6dce2fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587502345 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.k
eymgr_dpe_same_csr_outstanding.587502345
Directory /workspace/12.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.3359414975
Short name T261
Test name
Test status
Simulation time 353383999 ps
CPU time 5.3 seconds
Started Jun 08 01:53:11 PM PDT 24
Finished Jun 08 01:53:17 PM PDT 24
Peak memory 216984 kb
Host smart-750931af-3bd8-461c-9d9a-99e14382d0c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359414975 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.key
mgr_dpe_shadow_reg_errors.3359414975
Directory /workspace/12.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors_with_csr_rw.3002738338
Short name T220
Test name
Test status
Simulation time 147004941 ps
CPU time 3.98 seconds
Started Jun 08 01:53:09 PM PDT 24
Finished Jun 08 01:53:13 PM PDT 24
Peak memory 212920 kb
Host smart-155e8ee2-73de-4d02-afd7-1084cf793049
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002738338 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.keymgr_dpe_shadow_reg_errors_with_csr_rw.3002738338
Directory /workspace/12.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.3585446074
Short name T80
Test name
Test status
Simulation time 43891131 ps
CPU time 1.32 seconds
Started Jun 08 01:53:13 PM PDT 24
Finished Jun 08 01:53:14 PM PDT 24
Peak memory 204612 kb
Host smart-693a149e-b57c-4e66-9867-ed3dfb974e43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585446074 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_rw.
3585446074
Directory /workspace/13.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.2525897758
Short name T183
Test name
Test status
Simulation time 20683294 ps
CPU time 0.75 seconds
Started Jun 08 01:53:14 PM PDT 24
Finished Jun 08 01:53:15 PM PDT 24
Peak memory 204372 kb
Host smart-cc9a9c35-d1b8-4b08-bee7-7ebf26d609e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525897758 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_intr_test.
2525897758
Directory /workspace/13.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.479959428
Short name T286
Test name
Test status
Simulation time 49625358 ps
CPU time 1.9 seconds
Started Jun 08 01:53:13 PM PDT 24
Finished Jun 08 01:53:15 PM PDT 24
Peak memory 204388 kb
Host smart-7bb8737b-f7d5-4c95-822a-8ccca2c19c24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479959428 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.k
eymgr_dpe_same_csr_outstanding.479959428
Directory /workspace/13.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.2731772127
Short name T255
Test name
Test status
Simulation time 195176508 ps
CPU time 2.41 seconds
Started Jun 08 01:53:13 PM PDT 24
Finished Jun 08 01:53:16 PM PDT 24
Peak memory 212976 kb
Host smart-176977da-3035-42d9-b68b-618775123129
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731772127 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.key
mgr_dpe_shadow_reg_errors.2731772127
Directory /workspace/13.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.2267099354
Short name T233
Test name
Test status
Simulation time 112215650 ps
CPU time 2.08 seconds
Started Jun 08 01:53:14 PM PDT 24
Finished Jun 08 01:53:16 PM PDT 24
Peak memory 221116 kb
Host smart-7f6dfd97-28e8-40f9-84cd-7a7672b3dc3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267099354 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_tl_errors.
2267099354
Directory /workspace/13.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.2958093749
Short name T42
Test name
Test status
Simulation time 75101496 ps
CPU time 3.18 seconds
Started Jun 08 01:53:13 PM PDT 24
Finished Jun 08 01:53:16 PM PDT 24
Peak memory 212720 kb
Host smart-8a0bfe1b-06b0-477c-aa31-c4f27a10c985
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958093749 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dp
e_tl_intg_err.2958093749
Directory /workspace/13.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.3121005898
Short name T202
Test name
Test status
Simulation time 34322601 ps
CPU time 1.09 seconds
Started Jun 08 01:53:16 PM PDT 24
Finished Jun 08 01:53:17 PM PDT 24
Peak memory 204532 kb
Host smart-0e7d0adb-3e52-4a17-b0ec-a34eb1355026
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121005898 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_mem_rw_with_rand_reset.3121005898
Directory /workspace/14.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.2390651181
Short name T260
Test name
Test status
Simulation time 30461608 ps
CPU time 1.42 seconds
Started Jun 08 01:53:17 PM PDT 24
Finished Jun 08 01:53:19 PM PDT 24
Peak memory 204588 kb
Host smart-6868920b-ae25-42b4-93a5-ba3ae8c0a27f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390651181 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_rw.
2390651181
Directory /workspace/14.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.2233746549
Short name T300
Test name
Test status
Simulation time 15977717 ps
CPU time 0.7 seconds
Started Jun 08 01:53:18 PM PDT 24
Finished Jun 08 01:53:19 PM PDT 24
Peak memory 204320 kb
Host smart-07a258e7-dfb8-45fe-9b87-539bdc4ba729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233746549 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_intr_test.
2233746549
Directory /workspace/14.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.3424133322
Short name T287
Test name
Test status
Simulation time 79265651 ps
CPU time 2.9 seconds
Started Jun 08 01:53:21 PM PDT 24
Finished Jun 08 01:53:24 PM PDT 24
Peak memory 204496 kb
Host smart-9204e301-e2e4-4e6e-93c7-f47127298ebf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424133322 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_dpe_same_csr_outstanding.3424133322
Directory /workspace/14.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.1062690017
Short name T207
Test name
Test status
Simulation time 214656902 ps
CPU time 2.14 seconds
Started Jun 08 01:53:15 PM PDT 24
Finished Jun 08 01:53:17 PM PDT 24
Peak memory 213096 kb
Host smart-32b1872e-deca-4ea7-a17a-982951f27bf1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062690017 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.key
mgr_dpe_shadow_reg_errors.1062690017
Directory /workspace/14.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.2344849516
Short name T59
Test name
Test status
Simulation time 175953438 ps
CPU time 2.28 seconds
Started Jun 08 01:53:13 PM PDT 24
Finished Jun 08 01:53:15 PM PDT 24
Peak memory 213028 kb
Host smart-2a73fef5-a4cd-4381-a37a-c8d320e2ed50
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344849516 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.keymgr_dpe_shadow_reg_errors_with_csr_rw.2344849516
Directory /workspace/14.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.1769863583
Short name T246
Test name
Test status
Simulation time 176905710 ps
CPU time 3.83 seconds
Started Jun 08 01:53:12 PM PDT 24
Finished Jun 08 01:53:16 PM PDT 24
Peak memory 215460 kb
Host smart-572601f6-f77f-4cfb-a015-a750a943232e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769863583 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_tl_errors.
1769863583
Directory /workspace/14.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.2648814081
Short name T46
Test name
Test status
Simulation time 137958967 ps
CPU time 3.81 seconds
Started Jun 08 01:53:17 PM PDT 24
Finished Jun 08 01:53:21 PM PDT 24
Peak memory 212940 kb
Host smart-8e5b33e5-91cb-4708-8eb9-226801d56e61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648814081 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dp
e_tl_intg_err.2648814081
Directory /workspace/14.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.2551373184
Short name T19
Test name
Test status
Simulation time 21576499 ps
CPU time 0.94 seconds
Started Jun 08 01:53:22 PM PDT 24
Finished Jun 08 01:53:23 PM PDT 24
Peak memory 204524 kb
Host smart-c44513e5-32ae-4f9a-a76c-34a52c0cd270
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551373184 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_mem_rw_with_rand_reset.2551373184
Directory /workspace/15.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.650871463
Short name T241
Test name
Test status
Simulation time 67410133 ps
CPU time 0.82 seconds
Started Jun 08 01:53:20 PM PDT 24
Finished Jun 08 01:53:21 PM PDT 24
Peak memory 204428 kb
Host smart-284c7c7e-38e2-43b9-a65e-fc08b156d355
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650871463 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_rw.650871463
Directory /workspace/15.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.2621005766
Short name T211
Test name
Test status
Simulation time 11017254 ps
CPU time 0.82 seconds
Started Jun 08 01:53:16 PM PDT 24
Finished Jun 08 01:53:17 PM PDT 24
Peak memory 204344 kb
Host smart-a4bf81aa-f76b-42ce-bbf6-fab2daf2fa91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621005766 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_intr_test.
2621005766
Directory /workspace/15.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.645096461
Short name T284
Test name
Test status
Simulation time 27074081 ps
CPU time 1.5 seconds
Started Jun 08 01:53:22 PM PDT 24
Finished Jun 08 01:53:24 PM PDT 24
Peak memory 204504 kb
Host smart-fd182c9d-a927-46b6-b15c-2d7006bf318d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645096461 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.k
eymgr_dpe_same_csr_outstanding.645096461
Directory /workspace/15.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.345328462
Short name T302
Test name
Test status
Simulation time 293774298 ps
CPU time 2.64 seconds
Started Jun 08 01:53:18 PM PDT 24
Finished Jun 08 01:53:21 PM PDT 24
Peak memory 213048 kb
Host smart-474331db-3d17-44ff-adb7-20535da66914
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345328462 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keym
gr_dpe_shadow_reg_errors.345328462
Directory /workspace/15.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.3944299028
Short name T60
Test name
Test status
Simulation time 531050759 ps
CPU time 3.38 seconds
Started Jun 08 01:53:18 PM PDT 24
Finished Jun 08 01:53:21 PM PDT 24
Peak memory 212948 kb
Host smart-de39cf76-0a55-46e1-895d-49b437f5be2f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944299028 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.keymgr_dpe_shadow_reg_errors_with_csr_rw.3944299028
Directory /workspace/15.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.1536740191
Short name T295
Test name
Test status
Simulation time 462525105 ps
CPU time 1.9 seconds
Started Jun 08 01:53:17 PM PDT 24
Finished Jun 08 01:53:19 PM PDT 24
Peak memory 215876 kb
Host smart-982d9d7d-a5f9-460b-8b15-cd1f5ea0ecf1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536740191 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_tl_errors.
1536740191
Directory /workspace/15.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.46082077
Short name T67
Test name
Test status
Simulation time 139874495 ps
CPU time 2.77 seconds
Started Jun 08 01:53:17 PM PDT 24
Finished Jun 08 01:53:20 PM PDT 24
Peak memory 212684 kb
Host smart-9b92add4-fa55-4de9-b6bf-b0848640ba81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46082077 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_
tl_intg_err.46082077
Directory /workspace/15.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_mem_rw_with_rand_reset.860914367
Short name T89
Test name
Test status
Simulation time 27518859 ps
CPU time 1.21 seconds
Started Jun 08 01:53:24 PM PDT 24
Finished Jun 08 01:53:25 PM PDT 24
Peak memory 212708 kb
Host smart-6b281830-d192-4ed6-a647-a8026aa4824c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860914367 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_mem_rw_with_rand_reset.860914367
Directory /workspace/16.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.1149752016
Short name T78
Test name
Test status
Simulation time 17010984 ps
CPU time 1.1 seconds
Started Jun 08 01:53:25 PM PDT 24
Finished Jun 08 01:53:27 PM PDT 24
Peak memory 204384 kb
Host smart-765931d3-1b35-41d2-993a-67258c98fefd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149752016 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_rw.
1149752016
Directory /workspace/16.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.3084865231
Short name T249
Test name
Test status
Simulation time 51428422 ps
CPU time 0.78 seconds
Started Jun 08 01:53:22 PM PDT 24
Finished Jun 08 01:53:23 PM PDT 24
Peak memory 204384 kb
Host smart-2b6a5a6f-36d9-4fc9-b82f-aa4f6ad56397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084865231 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_intr_test.
3084865231
Directory /workspace/16.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.4071067610
Short name T293
Test name
Test status
Simulation time 171002279 ps
CPU time 1.2 seconds
Started Jun 08 01:53:21 PM PDT 24
Finished Jun 08 01:53:23 PM PDT 24
Peak memory 204584 kb
Host smart-19303966-a9d2-4404-a9ad-9cfab07961af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071067610 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_dpe_same_csr_outstanding.4071067610
Directory /workspace/16.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.355157891
Short name T164
Test name
Test status
Simulation time 45665466 ps
CPU time 1.17 seconds
Started Jun 08 01:53:25 PM PDT 24
Finished Jun 08 01:53:26 PM PDT 24
Peak memory 213020 kb
Host smart-a8c9fc85-eac2-4eea-a121-74d717f87db5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355157891 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keym
gr_dpe_shadow_reg_errors.355157891
Directory /workspace/16.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.2637848372
Short name T201
Test name
Test status
Simulation time 1871069244 ps
CPU time 6.37 seconds
Started Jun 08 01:53:25 PM PDT 24
Finished Jun 08 01:53:31 PM PDT 24
Peak memory 213240 kb
Host smart-da6cbebb-2848-4430-aee4-12d65391ec6d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637848372 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.keymgr_dpe_shadow_reg_errors_with_csr_rw.2637848372
Directory /workspace/16.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.2794623958
Short name T29
Test name
Test status
Simulation time 109595686 ps
CPU time 2.71 seconds
Started Jun 08 01:53:24 PM PDT 24
Finished Jun 08 01:53:27 PM PDT 24
Peak memory 220896 kb
Host smart-2b782962-64a2-4a65-8773-0d77e50879b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794623958 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_tl_errors.
2794623958
Directory /workspace/16.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.2715167360
Short name T259
Test name
Test status
Simulation time 76441800 ps
CPU time 1.94 seconds
Started Jun 08 01:53:24 PM PDT 24
Finished Jun 08 01:53:26 PM PDT 24
Peak memory 212716 kb
Host smart-a6be6317-4d72-4544-918b-4c692f3e64e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715167360 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_mem_rw_with_rand_reset.2715167360
Directory /workspace/17.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.1644749566
Short name T296
Test name
Test status
Simulation time 22020336 ps
CPU time 0.9 seconds
Started Jun 08 01:53:25 PM PDT 24
Finished Jun 08 01:53:26 PM PDT 24
Peak memory 204196 kb
Host smart-f9d54a53-b8bc-4cba-9e7c-b420b9bb2ba5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644749566 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_rw.
1644749566
Directory /workspace/17.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.2954420264
Short name T222
Test name
Test status
Simulation time 29321938 ps
CPU time 0.79 seconds
Started Jun 08 01:53:23 PM PDT 24
Finished Jun 08 01:53:24 PM PDT 24
Peak memory 204368 kb
Host smart-e7857353-aa97-4ea7-a12d-a8827505f243
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954420264 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_intr_test.
2954420264
Directory /workspace/17.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.3239799849
Short name T88
Test name
Test status
Simulation time 264380186 ps
CPU time 3.07 seconds
Started Jun 08 01:53:22 PM PDT 24
Finished Jun 08 01:53:25 PM PDT 24
Peak memory 204608 kb
Host smart-fbb380ec-f2f3-4475-b84e-4ecde01b7588
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239799849 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_dpe_same_csr_outstanding.3239799849
Directory /workspace/17.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.79048737
Short name T262
Test name
Test status
Simulation time 361505472 ps
CPU time 2.28 seconds
Started Jun 08 01:53:21 PM PDT 24
Finished Jun 08 01:53:23 PM PDT 24
Peak memory 213072 kb
Host smart-5ad16449-5ee4-4c24-aaa1-8f242903a2c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79048737 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keym
gr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymg
r_dpe_shadow_reg_errors.79048737
Directory /workspace/17.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.2038714589
Short name T292
Test name
Test status
Simulation time 603561678 ps
CPU time 4.23 seconds
Started Jun 08 01:53:22 PM PDT 24
Finished Jun 08 01:53:26 PM PDT 24
Peak memory 212956 kb
Host smart-ac86d8b3-5122-4dd0-b67c-9a92878365f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038714589 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.keymgr_dpe_shadow_reg_errors_with_csr_rw.2038714589
Directory /workspace/17.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.2700714226
Short name T265
Test name
Test status
Simulation time 151971812 ps
CPU time 1.69 seconds
Started Jun 08 01:53:22 PM PDT 24
Finished Jun 08 01:53:24 PM PDT 24
Peak memory 212796 kb
Host smart-750d5f37-e260-48b1-94cc-0cf5be8d5cab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700714226 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_tl_errors.
2700714226
Directory /workspace/17.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.3593062511
Short name T168
Test name
Test status
Simulation time 26500945 ps
CPU time 1.3 seconds
Started Jun 08 01:53:27 PM PDT 24
Finished Jun 08 01:53:29 PM PDT 24
Peak memory 214036 kb
Host smart-b9d5001f-85e3-4544-b7fc-f7819f37fa53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593062511 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_mem_rw_with_rand_reset.3593062511
Directory /workspace/18.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.2732959159
Short name T197
Test name
Test status
Simulation time 21393398 ps
CPU time 1 seconds
Started Jun 08 01:53:26 PM PDT 24
Finished Jun 08 01:53:27 PM PDT 24
Peak memory 204392 kb
Host smart-87bb1fc8-ea09-4a53-8b89-169c00254867
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732959159 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_rw.
2732959159
Directory /workspace/18.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.1655532226
Short name T160
Test name
Test status
Simulation time 11704503 ps
CPU time 0.79 seconds
Started Jun 08 01:53:22 PM PDT 24
Finished Jun 08 01:53:23 PM PDT 24
Peak memory 204324 kb
Host smart-f427f9ff-d245-4e56-9edb-7a3662187749
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655532226 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_intr_test.
1655532226
Directory /workspace/18.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.677981761
Short name T35
Test name
Test status
Simulation time 101128000 ps
CPU time 1.48 seconds
Started Jun 08 01:53:26 PM PDT 24
Finished Jun 08 01:53:27 PM PDT 24
Peak memory 204516 kb
Host smart-8a8cecf1-a8d3-4569-ab76-ab9d625e7ef2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677981761 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.k
eymgr_dpe_same_csr_outstanding.677981761
Directory /workspace/18.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors.2802005366
Short name T308
Test name
Test status
Simulation time 143754921 ps
CPU time 2.14 seconds
Started Jun 08 01:53:22 PM PDT 24
Finished Jun 08 01:53:24 PM PDT 24
Peak memory 213088 kb
Host smart-cf1889fb-6691-4297-a65d-ba3a99676b74
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802005366 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.key
mgr_dpe_shadow_reg_errors.2802005366
Directory /workspace/18.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.3710074173
Short name T235
Test name
Test status
Simulation time 74795347 ps
CPU time 2.41 seconds
Started Jun 08 01:53:24 PM PDT 24
Finished Jun 08 01:53:26 PM PDT 24
Peak memory 215076 kb
Host smart-bf121b9e-b5b8-4b93-8a28-5e5ac30cf901
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710074173 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_tl_errors.
3710074173
Directory /workspace/18.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.1197199002
Short name T54
Test name
Test status
Simulation time 51298328 ps
CPU time 2.46 seconds
Started Jun 08 01:53:25 PM PDT 24
Finished Jun 08 01:53:27 PM PDT 24
Peak memory 213448 kb
Host smart-90967491-edbc-4e29-8812-5244aa32e475
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197199002 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dp
e_tl_intg_err.1197199002
Directory /workspace/18.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_mem_rw_with_rand_reset.2041324240
Short name T210
Test name
Test status
Simulation time 18353223 ps
CPU time 1.45 seconds
Started Jun 08 01:53:26 PM PDT 24
Finished Jun 08 01:53:28 PM PDT 24
Peak memory 212856 kb
Host smart-b22d8bf5-9730-4644-b1ff-758f2df4a42b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041324240 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_mem_rw_with_rand_reset.2041324240
Directory /workspace/19.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.1779899097
Short name T307
Test name
Test status
Simulation time 17652260 ps
CPU time 0.9 seconds
Started Jun 08 01:53:27 PM PDT 24
Finished Jun 08 01:53:28 PM PDT 24
Peak memory 204400 kb
Host smart-8c95ff80-140c-45b4-9699-c13d1fb7bc2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779899097 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_rw.
1779899097
Directory /workspace/19.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.2531110197
Short name T171
Test name
Test status
Simulation time 28828638 ps
CPU time 0.79 seconds
Started Jun 08 01:53:26 PM PDT 24
Finished Jun 08 01:53:27 PM PDT 24
Peak memory 204340 kb
Host smart-bbe0aaf5-e7fa-49be-9c85-8371ba5ecbf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531110197 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_intr_test.
2531110197
Directory /workspace/19.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.988701226
Short name T177
Test name
Test status
Simulation time 73649867 ps
CPU time 1.39 seconds
Started Jun 08 01:53:29 PM PDT 24
Finished Jun 08 01:53:30 PM PDT 24
Peak memory 204468 kb
Host smart-74e7c059-e255-40d3-ae5a-579c3621e8a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988701226 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.k
eymgr_dpe_same_csr_outstanding.988701226
Directory /workspace/19.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.2216993147
Short name T227
Test name
Test status
Simulation time 113240331 ps
CPU time 2.41 seconds
Started Jun 08 01:53:25 PM PDT 24
Finished Jun 08 01:53:28 PM PDT 24
Peak memory 213112 kb
Host smart-30d31018-fc4e-489d-82d8-8aec30a8b169
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216993147 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.key
mgr_dpe_shadow_reg_errors.2216993147
Directory /workspace/19.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.1183232353
Short name T288
Test name
Test status
Simulation time 167071162 ps
CPU time 3.28 seconds
Started Jun 08 01:53:28 PM PDT 24
Finished Jun 08 01:53:31 PM PDT 24
Peak memory 213276 kb
Host smart-dee5a550-3543-4d5d-97de-87d16914806f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183232353 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.keymgr_dpe_shadow_reg_errors_with_csr_rw.1183232353
Directory /workspace/19.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.1477210086
Short name T269
Test name
Test status
Simulation time 483608330 ps
CPU time 4.67 seconds
Started Jun 08 01:53:26 PM PDT 24
Finished Jun 08 01:53:31 PM PDT 24
Peak memory 212784 kb
Host smart-1379a68d-a349-4793-80b9-60ab38329009
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477210086 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_tl_errors.
1477210086
Directory /workspace/19.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.198720632
Short name T30
Test name
Test status
Simulation time 1316796518 ps
CPU time 7.43 seconds
Started Jun 08 01:53:27 PM PDT 24
Finished Jun 08 01:53:34 PM PDT 24
Peak memory 212732 kb
Host smart-899e2adc-0076-4431-96c2-145b2d0d2057
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198720632 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe
_tl_intg_err.198720632
Directory /workspace/19.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.2989827978
Short name T279
Test name
Test status
Simulation time 403127662 ps
CPU time 3.3 seconds
Started Jun 08 01:52:32 PM PDT 24
Finished Jun 08 01:52:36 PM PDT 24
Peak memory 204532 kb
Host smart-51d79c47-1019-41aa-94cd-d5bf919dc8fd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989827978 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_aliasing.2989827978
Directory /workspace/2.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.3244095858
Short name T65
Test name
Test status
Simulation time 3189159604 ps
CPU time 10.77 seconds
Started Jun 08 01:52:33 PM PDT 24
Finished Jun 08 01:52:44 PM PDT 24
Peak memory 204776 kb
Host smart-9d607f58-249b-44e0-8442-6c3815d4ace3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244095858 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_bit_bash.3244095858
Directory /workspace/2.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.944693430
Short name T86
Test name
Test status
Simulation time 19894744 ps
CPU time 0.87 seconds
Started Jun 08 01:52:29 PM PDT 24
Finished Jun 08 01:52:30 PM PDT 24
Peak memory 204448 kb
Host smart-19e8d20b-dd49-4ff9-8017-cc32ece791c7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944693430 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr
_hw_reset.944693430
Directory /workspace/2.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.1836269450
Short name T263
Test name
Test status
Simulation time 132567073 ps
CPU time 1.86 seconds
Started Jun 08 01:52:33 PM PDT 24
Finished Jun 08 01:52:35 PM PDT 24
Peak memory 212712 kb
Host smart-101255f9-b2fb-413a-ba2f-173a96844375
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836269450 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_mem_rw_with_rand_reset.1836269450
Directory /workspace/2.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.2648228024
Short name T272
Test name
Test status
Simulation time 73379182 ps
CPU time 1.14 seconds
Started Jun 08 01:52:33 PM PDT 24
Finished Jun 08 01:52:35 PM PDT 24
Peak memory 204452 kb
Host smart-eaa28579-d7cf-43b4-b28e-fcd1e6641234
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648228024 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_rw.2
648228024
Directory /workspace/2.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.3360457192
Short name T206
Test name
Test status
Simulation time 39526339 ps
CPU time 0.75 seconds
Started Jun 08 01:52:32 PM PDT 24
Finished Jun 08 01:52:33 PM PDT 24
Peak memory 204300 kb
Host smart-4f85dec6-72a9-40f4-ac46-4a14785adf0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360457192 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_intr_test.3
360457192
Directory /workspace/2.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.2325521095
Short name T280
Test name
Test status
Simulation time 103319637 ps
CPU time 1.64 seconds
Started Jun 08 01:52:33 PM PDT 24
Finished Jun 08 01:52:35 PM PDT 24
Peak memory 204488 kb
Host smart-2f305a2f-5d66-46c8-aad9-951c849be25d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325521095 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_dpe_same_csr_outstanding.2325521095
Directory /workspace/2.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.4160658710
Short name T185
Test name
Test status
Simulation time 1398141808 ps
CPU time 2.25 seconds
Started Jun 08 01:52:28 PM PDT 24
Finished Jun 08 01:52:30 PM PDT 24
Peak memory 212940 kb
Host smart-f47f0719-4b1a-4b61-b996-88779c42d34c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160658710 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keym
gr_dpe_shadow_reg_errors.4160658710
Directory /workspace/2.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.3516990311
Short name T306
Test name
Test status
Simulation time 1334706048 ps
CPU time 5.67 seconds
Started Jun 08 01:52:27 PM PDT 24
Finished Jun 08 01:52:33 PM PDT 24
Peak memory 213064 kb
Host smart-8044ed1e-97f1-4714-9be8-575e1d5842b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516990311 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.keymgr_dpe_shadow_reg_errors_with_csr_rw.3516990311
Directory /workspace/2.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.1473543607
Short name T257
Test name
Test status
Simulation time 309494560 ps
CPU time 3.05 seconds
Started Jun 08 01:52:27 PM PDT 24
Finished Jun 08 01:52:30 PM PDT 24
Peak memory 212744 kb
Host smart-78402697-4d5e-4f56-aa97-1205b8a75a59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473543607 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_tl_errors.1
473543607
Directory /workspace/2.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.1303307474
Short name T40
Test name
Test status
Simulation time 922963772 ps
CPU time 5.2 seconds
Started Jun 08 01:52:28 PM PDT 24
Finished Jun 08 01:52:34 PM PDT 24
Peak memory 212704 kb
Host smart-2bc3d2b4-532d-41a5-a5c1-5ca81b51b651
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303307474 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe
_tl_intg_err.1303307474
Directory /workspace/2.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.2171551365
Short name T36
Test name
Test status
Simulation time 23841297 ps
CPU time 0.75 seconds
Started Jun 08 01:53:29 PM PDT 24
Finished Jun 08 01:53:29 PM PDT 24
Peak memory 204356 kb
Host smart-1349261f-7237-42b4-86b6-2ba975753f72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171551365 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_intr_test.
2171551365
Directory /workspace/20.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.3790604343
Short name T161
Test name
Test status
Simulation time 47648748 ps
CPU time 0.8 seconds
Started Jun 08 01:53:29 PM PDT 24
Finished Jun 08 01:53:30 PM PDT 24
Peak memory 204364 kb
Host smart-f5666cea-5eb7-40af-a3c5-fb2dc4425f15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790604343 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_intr_test.
3790604343
Directory /workspace/21.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.2510003235
Short name T213
Test name
Test status
Simulation time 39953061 ps
CPU time 0.76 seconds
Started Jun 08 01:53:34 PM PDT 24
Finished Jun 08 01:53:35 PM PDT 24
Peak memory 204368 kb
Host smart-d4eca011-c851-476d-9bd1-40fe8ca757b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510003235 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_intr_test.
2510003235
Directory /workspace/22.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.3909862442
Short name T205
Test name
Test status
Simulation time 54032624 ps
CPU time 0.91 seconds
Started Jun 08 01:53:29 PM PDT 24
Finished Jun 08 01:53:30 PM PDT 24
Peak memory 204232 kb
Host smart-1b1eecbb-2f44-46d5-a206-c88baa0a5c4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909862442 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_intr_test.
3909862442
Directory /workspace/23.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.475067098
Short name T166
Test name
Test status
Simulation time 26623217 ps
CPU time 0.7 seconds
Started Jun 08 01:53:32 PM PDT 24
Finished Jun 08 01:53:33 PM PDT 24
Peak memory 204272 kb
Host smart-67c9645b-903d-4016-a713-368d65c63138
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475067098 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_intr_test.475067098
Directory /workspace/24.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.1007118399
Short name T189
Test name
Test status
Simulation time 12491371 ps
CPU time 0.8 seconds
Started Jun 08 01:53:30 PM PDT 24
Finished Jun 08 01:53:30 PM PDT 24
Peak memory 204336 kb
Host smart-b03b538b-0cd3-4448-b394-8c9c723c262a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007118399 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_intr_test.
1007118399
Directory /workspace/25.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.310993234
Short name T290
Test name
Test status
Simulation time 14969065 ps
CPU time 0.74 seconds
Started Jun 08 01:53:29 PM PDT 24
Finished Jun 08 01:53:30 PM PDT 24
Peak memory 204276 kb
Host smart-592cf744-ae4f-4794-a9c2-c89293b0b5aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310993234 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_intr_test.310993234
Directory /workspace/26.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.1441075134
Short name T85
Test name
Test status
Simulation time 13342160 ps
CPU time 0.74 seconds
Started Jun 08 01:53:32 PM PDT 24
Finished Jun 08 01:53:33 PM PDT 24
Peak memory 204324 kb
Host smart-f2bd2385-7ea6-4d44-b1ed-2d0bdad2e1e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441075134 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_intr_test.
1441075134
Directory /workspace/27.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.2316645704
Short name T218
Test name
Test status
Simulation time 24973418 ps
CPU time 0.75 seconds
Started Jun 08 01:53:32 PM PDT 24
Finished Jun 08 01:53:33 PM PDT 24
Peak memory 204280 kb
Host smart-388b84b7-3954-4cfc-92a4-1a97ca25ddcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316645704 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_intr_test.
2316645704
Directory /workspace/28.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_dpe_intr_test.935306193
Short name T191
Test name
Test status
Simulation time 9891663 ps
CPU time 0.83 seconds
Started Jun 08 01:53:33 PM PDT 24
Finished Jun 08 01:53:34 PM PDT 24
Peak memory 204352 kb
Host smart-6eb74937-8549-4f59-bc51-a5e93c093356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935306193 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_intr_test.935306193
Directory /workspace/29.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.4183836980
Short name T256
Test name
Test status
Simulation time 156216309 ps
CPU time 4.77 seconds
Started Jun 08 01:52:40 PM PDT 24
Finished Jun 08 01:52:45 PM PDT 24
Peak memory 204560 kb
Host smart-c32226e7-63db-4963-b259-1cdff56ca529
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183836980 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_aliasing.4183836980
Directory /workspace/3.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.1712377181
Short name T258
Test name
Test status
Simulation time 575742799 ps
CPU time 17.04 seconds
Started Jun 08 01:52:37 PM PDT 24
Finished Jun 08 01:52:55 PM PDT 24
Peak memory 204480 kb
Host smart-d950a41b-3503-4431-a45f-c78aa1cf1747
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712377181 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_bit_bash.1712377181
Directory /workspace/3.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_hw_reset.1260864725
Short name T165
Test name
Test status
Simulation time 42774707 ps
CPU time 0.9 seconds
Started Jun 08 01:52:37 PM PDT 24
Finished Jun 08 01:52:38 PM PDT 24
Peak memory 204468 kb
Host smart-b26157be-715c-4c32-aef7-a431a259c883
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260864725 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_hw_reset.1260864725
Directory /workspace/3.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.560787684
Short name T230
Test name
Test status
Simulation time 75024924 ps
CPU time 1.41 seconds
Started Jun 08 01:52:43 PM PDT 24
Finished Jun 08 01:52:45 PM PDT 24
Peak memory 216068 kb
Host smart-8fcb3dd4-b745-4bd8-904f-d2c41a858ee0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560787684 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_mem_rw_with_rand_reset.560787684
Directory /workspace/3.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.3799943014
Short name T245
Test name
Test status
Simulation time 17674769 ps
CPU time 0.85 seconds
Started Jun 08 01:52:37 PM PDT 24
Finished Jun 08 01:52:38 PM PDT 24
Peak memory 204360 kb
Host smart-db105b02-fe4f-4688-8966-4e107c96955e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799943014 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_rw.3
799943014
Directory /workspace/3.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.3640458204
Short name T236
Test name
Test status
Simulation time 32966506 ps
CPU time 0.7 seconds
Started Jun 08 01:52:39 PM PDT 24
Finished Jun 08 01:52:40 PM PDT 24
Peak memory 204344 kb
Host smart-ff8bcb8c-ea14-41cd-81b9-49fd86847d9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640458204 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_intr_test.3
640458204
Directory /workspace/3.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.413251164
Short name T252
Test name
Test status
Simulation time 845640075 ps
CPU time 2.59 seconds
Started Jun 08 01:52:38 PM PDT 24
Finished Jun 08 01:52:40 PM PDT 24
Peak memory 204524 kb
Host smart-5b78ff43-82d9-4127-abb9-79ae18b86dee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413251164 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.ke
ymgr_dpe_same_csr_outstanding.413251164
Directory /workspace/3.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.3749938494
Short name T234
Test name
Test status
Simulation time 142754340 ps
CPU time 1.73 seconds
Started Jun 08 01:52:34 PM PDT 24
Finished Jun 08 01:52:36 PM PDT 24
Peak memory 213128 kb
Host smart-0b3eb274-f747-4711-af18-1cc1d91ff87f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749938494 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keym
gr_dpe_shadow_reg_errors.3749938494
Directory /workspace/3.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.384677547
Short name T229
Test name
Test status
Simulation time 96871378 ps
CPU time 3.79 seconds
Started Jun 08 01:52:35 PM PDT 24
Finished Jun 08 01:52:39 PM PDT 24
Peak memory 213052 kb
Host smart-e6d35778-b7e4-48ec-8c57-21483a1dd11e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384677547 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.keymgr_dpe_shadow_reg_errors_with_csr_rw.384677547
Directory /workspace/3.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.3523701300
Short name T32
Test name
Test status
Simulation time 27004617 ps
CPU time 1.65 seconds
Started Jun 08 01:52:33 PM PDT 24
Finished Jun 08 01:52:35 PM PDT 24
Peak memory 212784 kb
Host smart-56cfff62-5c20-4c4f-92ad-ea4774020673
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523701300 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_tl_errors.3
523701300
Directory /workspace/3.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.3668795077
Short name T45
Test name
Test status
Simulation time 551619673 ps
CPU time 3.81 seconds
Started Jun 08 01:52:33 PM PDT 24
Finished Jun 08 01:52:37 PM PDT 24
Peak memory 204488 kb
Host smart-5c462477-2250-4c7e-8e88-0752c7d95163
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668795077 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe
_tl_intg_err.3668795077
Directory /workspace/3.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.2887769574
Short name T187
Test name
Test status
Simulation time 24153667 ps
CPU time 0.86 seconds
Started Jun 08 01:53:39 PM PDT 24
Finished Jun 08 01:53:40 PM PDT 24
Peak memory 204248 kb
Host smart-af662fa7-cd9e-4533-8407-b1025555618e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887769574 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_intr_test.
2887769574
Directory /workspace/30.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.3066926087
Short name T38
Test name
Test status
Simulation time 12921786 ps
CPU time 0.74 seconds
Started Jun 08 01:53:36 PM PDT 24
Finished Jun 08 01:53:37 PM PDT 24
Peak memory 204328 kb
Host smart-8663deb0-652c-42c4-aac2-96360fe77f88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066926087 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_intr_test.
3066926087
Directory /workspace/31.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.568927830
Short name T195
Test name
Test status
Simulation time 39454335 ps
CPU time 0.79 seconds
Started Jun 08 01:53:36 PM PDT 24
Finished Jun 08 01:53:37 PM PDT 24
Peak memory 204272 kb
Host smart-fc523472-2f65-43ba-912b-173defc7be04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568927830 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_intr_test.568927830
Directory /workspace/32.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.1094084368
Short name T179
Test name
Test status
Simulation time 139107410 ps
CPU time 0.76 seconds
Started Jun 08 01:53:36 PM PDT 24
Finished Jun 08 01:53:37 PM PDT 24
Peak memory 204336 kb
Host smart-f2750d73-a191-42cf-850a-7b1241e5b93b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094084368 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_intr_test.
1094084368
Directory /workspace/33.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.4119394919
Short name T102
Test name
Test status
Simulation time 16478112 ps
CPU time 0.94 seconds
Started Jun 08 01:53:37 PM PDT 24
Finished Jun 08 01:53:38 PM PDT 24
Peak memory 204448 kb
Host smart-79846a9a-653a-4efc-b16f-ce5e3c871379
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119394919 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_intr_test.
4119394919
Directory /workspace/34.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.1846917955
Short name T182
Test name
Test status
Simulation time 10107097 ps
CPU time 0.83 seconds
Started Jun 08 01:53:37 PM PDT 24
Finished Jun 08 01:53:38 PM PDT 24
Peak memory 204344 kb
Host smart-97a0cf95-39e6-4977-91fe-c4f42edc2be5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846917955 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_intr_test.
1846917955
Directory /workspace/35.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.4204570886
Short name T209
Test name
Test status
Simulation time 39673938 ps
CPU time 0.78 seconds
Started Jun 08 01:53:39 PM PDT 24
Finished Jun 08 01:53:41 PM PDT 24
Peak memory 204248 kb
Host smart-c4d748b4-4806-4a23-a6d6-93d047d35fb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204570886 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_intr_test.
4204570886
Directory /workspace/36.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.520244407
Short name T162
Test name
Test status
Simulation time 18911706 ps
CPU time 0.8 seconds
Started Jun 08 01:53:38 PM PDT 24
Finished Jun 08 01:53:39 PM PDT 24
Peak memory 204332 kb
Host smart-14b5b0e9-8a95-421d-bd70-dfddd1456bfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520244407 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_intr_test.520244407
Directory /workspace/37.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_dpe_intr_test.3349082514
Short name T219
Test name
Test status
Simulation time 50349983 ps
CPU time 0.77 seconds
Started Jun 08 01:53:38 PM PDT 24
Finished Jun 08 01:53:39 PM PDT 24
Peak memory 204396 kb
Host smart-60126ff0-a364-48bc-9bd0-06073d2fa820
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349082514 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_intr_test.
3349082514
Directory /workspace/38.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.3005212349
Short name T275
Test name
Test status
Simulation time 39228947 ps
CPU time 0.88 seconds
Started Jun 08 01:53:40 PM PDT 24
Finished Jun 08 01:53:41 PM PDT 24
Peak memory 204292 kb
Host smart-d76cfd81-c97d-46e3-9b97-eca35c8d0c83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005212349 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_intr_test.
3005212349
Directory /workspace/39.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.2945411897
Short name T273
Test name
Test status
Simulation time 310534132 ps
CPU time 5.44 seconds
Started Jun 08 01:52:43 PM PDT 24
Finished Jun 08 01:52:49 PM PDT 24
Peak memory 204328 kb
Host smart-e34ef3cd-0d6f-4ad2-a3e8-3a1fc1255763
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945411897 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_aliasing.2945411897
Directory /workspace/4.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.508466059
Short name T254
Test name
Test status
Simulation time 179111917 ps
CPU time 9.79 seconds
Started Jun 08 01:52:42 PM PDT 24
Finished Jun 08 01:52:52 PM PDT 24
Peak memory 204528 kb
Host smart-07699a78-acb6-4b16-bae6-6c41afb8e8e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508466059 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr
_bit_bash.508466059
Directory /workspace/4.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.2475062138
Short name T289
Test name
Test status
Simulation time 104192562 ps
CPU time 1.07 seconds
Started Jun 08 01:52:42 PM PDT 24
Finished Jun 08 01:52:43 PM PDT 24
Peak memory 204468 kb
Host smart-7d069629-eac8-49cf-81f5-1d4da0460fcf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475062138 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_hw_reset.2475062138
Directory /workspace/4.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.3533097398
Short name T193
Test name
Test status
Simulation time 91410828 ps
CPU time 1.11 seconds
Started Jun 08 01:52:45 PM PDT 24
Finished Jun 08 01:52:46 PM PDT 24
Peak memory 204528 kb
Host smart-13c0d4c1-f7e8-457d-b1ee-7fe2fba951ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533097398 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_mem_rw_with_rand_reset.3533097398
Directory /workspace/4.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.1463228533
Short name T178
Test name
Test status
Simulation time 82661177 ps
CPU time 1.34 seconds
Started Jun 08 01:52:43 PM PDT 24
Finished Jun 08 01:52:45 PM PDT 24
Peak memory 204544 kb
Host smart-17917fbe-243f-4fb1-843a-79da4d01c3e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463228533 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_rw.1
463228533
Directory /workspace/4.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.3671935302
Short name T264
Test name
Test status
Simulation time 7849552 ps
CPU time 0.81 seconds
Started Jun 08 01:52:45 PM PDT 24
Finished Jun 08 01:52:46 PM PDT 24
Peak memory 204384 kb
Host smart-316dd7fe-34bd-4241-9009-8185dadebec7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671935302 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_intr_test.3
671935302
Directory /workspace/4.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_same_csr_outstanding.4211637151
Short name T188
Test name
Test status
Simulation time 155831992 ps
CPU time 2.06 seconds
Started Jun 08 01:52:45 PM PDT 24
Finished Jun 08 01:52:47 PM PDT 24
Peak memory 204524 kb
Host smart-c3969751-64d9-4146-9960-b055eb875d8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211637151 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_dpe_same_csr_outstanding.4211637151
Directory /workspace/4.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.1765151407
Short name T244
Test name
Test status
Simulation time 237482742 ps
CPU time 3.77 seconds
Started Jun 08 01:52:43 PM PDT 24
Finished Jun 08 01:52:47 PM PDT 24
Peak memory 213012 kb
Host smart-220cd724-e5f5-4386-b266-fc2f45e65a9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765151407 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keym
gr_dpe_shadow_reg_errors.1765151407
Directory /workspace/4.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.357524770
Short name T228
Test name
Test status
Simulation time 990955728 ps
CPU time 8.4 seconds
Started Jun 08 01:52:43 PM PDT 24
Finished Jun 08 01:52:51 PM PDT 24
Peak memory 213040 kb
Host smart-e11d7bc6-ccc2-4c77-9937-5067240fde7f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357524770 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.keymgr_dpe_shadow_reg_errors_with_csr_rw.357524770
Directory /workspace/4.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_errors.3877917122
Short name T63
Test name
Test status
Simulation time 122356002 ps
CPU time 2.92 seconds
Started Jun 08 01:52:43 PM PDT 24
Finished Jun 08 01:52:46 PM PDT 24
Peak memory 220832 kb
Host smart-5efded1b-ec48-420a-a5e7-5edfcb097e62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877917122 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_tl_errors.3
877917122
Directory /workspace/4.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.3641281033
Short name T215
Test name
Test status
Simulation time 20404664 ps
CPU time 0.69 seconds
Started Jun 08 01:53:36 PM PDT 24
Finished Jun 08 01:53:37 PM PDT 24
Peak memory 204388 kb
Host smart-231cc3f7-115d-42ab-b8a3-747192b7bd21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641281033 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_intr_test.
3641281033
Directory /workspace/40.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.2619847540
Short name T237
Test name
Test status
Simulation time 12084498 ps
CPU time 0.84 seconds
Started Jun 08 01:53:38 PM PDT 24
Finished Jun 08 01:53:39 PM PDT 24
Peak memory 204320 kb
Host smart-4b32dbee-7161-4b9f-adbf-a692cefa2d50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619847540 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_intr_test.
2619847540
Directory /workspace/41.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.1128545887
Short name T64
Test name
Test status
Simulation time 31744384 ps
CPU time 0.78 seconds
Started Jun 08 01:53:34 PM PDT 24
Finished Jun 08 01:53:35 PM PDT 24
Peak memory 204352 kb
Host smart-0e684496-28e3-465a-8e76-bd728dc29560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128545887 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_intr_test.
1128545887
Directory /workspace/42.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.2179989451
Short name T226
Test name
Test status
Simulation time 16593614 ps
CPU time 0.72 seconds
Started Jun 08 01:53:39 PM PDT 24
Finished Jun 08 01:53:40 PM PDT 24
Peak memory 204356 kb
Host smart-9da8b84c-88db-48a0-a0e7-7542feee2425
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179989451 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_intr_test.
2179989451
Directory /workspace/43.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.3968714252
Short name T181
Test name
Test status
Simulation time 20390464 ps
CPU time 0.79 seconds
Started Jun 08 01:53:42 PM PDT 24
Finished Jun 08 01:53:43 PM PDT 24
Peak memory 204272 kb
Host smart-59c70994-c216-4cfd-8855-bc44ee52549d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968714252 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_intr_test.
3968714252
Directory /workspace/44.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.202271794
Short name T77
Test name
Test status
Simulation time 12584745 ps
CPU time 0.87 seconds
Started Jun 08 01:53:40 PM PDT 24
Finished Jun 08 01:53:41 PM PDT 24
Peak memory 204360 kb
Host smart-5df739af-c232-4787-9b16-49fcad14953a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202271794 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_intr_test.202271794
Directory /workspace/45.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.2132468711
Short name T99
Test name
Test status
Simulation time 44362840 ps
CPU time 0.71 seconds
Started Jun 08 01:53:40 PM PDT 24
Finished Jun 08 01:53:41 PM PDT 24
Peak memory 204376 kb
Host smart-85806b8c-c76a-4f88-bfa3-ffae11831b7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132468711 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_intr_test.
2132468711
Directory /workspace/46.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.2918372149
Short name T232
Test name
Test status
Simulation time 45502747 ps
CPU time 0.84 seconds
Started Jun 08 01:53:41 PM PDT 24
Finished Jun 08 01:53:42 PM PDT 24
Peak memory 204308 kb
Host smart-23f6d226-80d1-4e9a-a509-7b0f1c1d2c94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918372149 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_intr_test.
2918372149
Directory /workspace/47.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.503919517
Short name T251
Test name
Test status
Simulation time 42721773 ps
CPU time 0.72 seconds
Started Jun 08 01:53:40 PM PDT 24
Finished Jun 08 01:53:41 PM PDT 24
Peak memory 204340 kb
Host smart-8a8f0e05-6148-4fc8-9a12-03fac0d12429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503919517 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_intr_test.503919517
Directory /workspace/48.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.2675869829
Short name T298
Test name
Test status
Simulation time 19535482 ps
CPU time 0.72 seconds
Started Jun 08 01:53:39 PM PDT 24
Finished Jun 08 01:53:40 PM PDT 24
Peak memory 204376 kb
Host smart-e09a3b62-fa8c-4a22-90f3-ec582f7a9e6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675869829 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_intr_test.
2675869829
Directory /workspace/49.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.627055858
Short name T212
Test name
Test status
Simulation time 28334957 ps
CPU time 0.93 seconds
Started Jun 08 01:52:46 PM PDT 24
Finished Jun 08 01:52:48 PM PDT 24
Peak memory 204440 kb
Host smart-af2ba178-8169-4be2-bfaf-d78c11a7d928
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627055858 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_mem_rw_with_rand_reset.627055858
Directory /workspace/5.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.3874077654
Short name T170
Test name
Test status
Simulation time 73055689 ps
CPU time 1.01 seconds
Started Jun 08 01:52:46 PM PDT 24
Finished Jun 08 01:52:48 PM PDT 24
Peak memory 204508 kb
Host smart-42358df5-a611-4967-b0ab-8bb850721a18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874077654 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_rw.3
874077654
Directory /workspace/5.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.3673248838
Short name T184
Test name
Test status
Simulation time 14500326 ps
CPU time 0.89 seconds
Started Jun 08 01:52:48 PM PDT 24
Finished Jun 08 01:52:49 PM PDT 24
Peak memory 204580 kb
Host smart-000d7a5a-6c3f-4a68-8c7d-eff57e2831e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673248838 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_intr_test.3
673248838
Directory /workspace/5.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.3766101002
Short name T301
Test name
Test status
Simulation time 109182706 ps
CPU time 2 seconds
Started Jun 08 01:52:50 PM PDT 24
Finished Jun 08 01:52:52 PM PDT 24
Peak memory 204444 kb
Host smart-929a2339-0efe-4809-8f2c-6879d52cb462
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766101002 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_dpe_same_csr_outstanding.3766101002
Directory /workspace/5.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.28769773
Short name T163
Test name
Test status
Simulation time 83666468 ps
CPU time 1.65 seconds
Started Jun 08 01:52:43 PM PDT 24
Finished Jun 08 01:52:44 PM PDT 24
Peak memory 213020 kb
Host smart-24466b03-bfe3-416c-98c1-8349f5494648
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28769773 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keym
gr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr
_dpe_shadow_reg_errors.28769773
Directory /workspace/5.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.2755265846
Short name T248
Test name
Test status
Simulation time 231191248 ps
CPU time 5.29 seconds
Started Jun 08 01:52:42 PM PDT 24
Finished Jun 08 01:52:47 PM PDT 24
Peak memory 213064 kb
Host smart-ac43bf7f-a2fc-447e-9c7b-a84feb45e0dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755265846 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.keymgr_dpe_shadow_reg_errors_with_csr_rw.2755265846
Directory /workspace/5.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.799293460
Short name T294
Test name
Test status
Simulation time 53927884 ps
CPU time 2.03 seconds
Started Jun 08 01:52:47 PM PDT 24
Finished Jun 08 01:52:49 PM PDT 24
Peak memory 212728 kb
Host smart-f97bdd86-e450-4ecb-ae8c-f4c9a158ab49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799293460 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_tl_errors.799293460
Directory /workspace/5.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.3775777776
Short name T62
Test name
Test status
Simulation time 23654351 ps
CPU time 1.74 seconds
Started Jun 08 01:52:51 PM PDT 24
Finished Jun 08 01:52:53 PM PDT 24
Peak memory 212684 kb
Host smart-fd1912be-a6a7-47c1-a8bf-172552a8b9f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775777776 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_mem_rw_with_rand_reset.3775777776
Directory /workspace/6.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.2480770526
Short name T276
Test name
Test status
Simulation time 40996491 ps
CPU time 1.03 seconds
Started Jun 08 01:52:52 PM PDT 24
Finished Jun 08 01:52:54 PM PDT 24
Peak memory 204488 kb
Host smart-2c4d7597-31e2-45f7-b3b4-d7d2a948e738
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480770526 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_rw.2
480770526
Directory /workspace/6.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.725615330
Short name T277
Test name
Test status
Simulation time 19770778 ps
CPU time 0.79 seconds
Started Jun 08 01:52:52 PM PDT 24
Finished Jun 08 01:52:53 PM PDT 24
Peak memory 204296 kb
Host smart-4be253d7-cdc2-4e15-9f5f-b3c10e5fdd4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725615330 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_intr_test.725615330
Directory /workspace/6.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.3977695238
Short name T76
Test name
Test status
Simulation time 766846797 ps
CPU time 3.31 seconds
Started Jun 08 01:52:50 PM PDT 24
Finished Jun 08 01:52:53 PM PDT 24
Peak memory 204452 kb
Host smart-a574eb2b-507d-4509-b17a-e990a19ad80f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977695238 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_dpe_same_csr_outstanding.3977695238
Directory /workspace/6.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors.4143490006
Short name T291
Test name
Test status
Simulation time 74774791 ps
CPU time 2.43 seconds
Started Jun 08 01:52:47 PM PDT 24
Finished Jun 08 01:52:49 PM PDT 24
Peak memory 213048 kb
Host smart-f21e2c89-ca69-4697-9ddf-42fe233850fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143490006 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keym
gr_dpe_shadow_reg_errors.4143490006
Directory /workspace/6.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.331135721
Short name T224
Test name
Test status
Simulation time 103531325 ps
CPU time 3.98 seconds
Started Jun 08 01:52:47 PM PDT 24
Finished Jun 08 01:52:51 PM PDT 24
Peak memory 213048 kb
Host smart-01a79e67-15c9-4986-9ed1-92f5c83a743e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331135721 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.keymgr_dpe_shadow_reg_errors_with_csr_rw.331135721
Directory /workspace/6.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.2227120429
Short name T242
Test name
Test status
Simulation time 77803914 ps
CPU time 2.89 seconds
Started Jun 08 01:52:46 PM PDT 24
Finished Jun 08 01:52:49 PM PDT 24
Peak memory 212700 kb
Host smart-e67088ba-9086-4205-b551-8ffa7a0ba2c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227120429 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_tl_errors.2
227120429
Directory /workspace/6.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.1303535456
Short name T190
Test name
Test status
Simulation time 41967421 ps
CPU time 1.05 seconds
Started Jun 08 01:52:59 PM PDT 24
Finished Jun 08 01:53:00 PM PDT 24
Peak memory 204368 kb
Host smart-e3481119-8a14-4be5-a9f7-05f162eb9481
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303535456 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_mem_rw_with_rand_reset.1303535456
Directory /workspace/7.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_rw.2734528219
Short name T283
Test name
Test status
Simulation time 57560213 ps
CPU time 1.06 seconds
Started Jun 08 01:52:58 PM PDT 24
Finished Jun 08 01:52:59 PM PDT 24
Peak memory 204372 kb
Host smart-693cf94d-0e2b-42be-9b20-a15912d4acf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734528219 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_rw.2
734528219
Directory /workspace/7.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.913986455
Short name T303
Test name
Test status
Simulation time 15480293 ps
CPU time 0.72 seconds
Started Jun 08 01:52:56 PM PDT 24
Finished Jun 08 01:52:57 PM PDT 24
Peak memory 204340 kb
Host smart-924f0966-caee-4326-8261-e58c73af416c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913986455 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_intr_test.913986455
Directory /workspace/7.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.2430790931
Short name T271
Test name
Test status
Simulation time 81263237 ps
CPU time 1.27 seconds
Started Jun 08 01:52:54 PM PDT 24
Finished Jun 08 01:52:56 PM PDT 24
Peak memory 204508 kb
Host smart-46886ebc-8694-4bee-aaab-8bf7414f3c2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430790931 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_dpe_same_csr_outstanding.2430790931
Directory /workspace/7.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors.1484419250
Short name T56
Test name
Test status
Simulation time 368188030 ps
CPU time 2.08 seconds
Started Jun 08 01:52:51 PM PDT 24
Finished Jun 08 01:52:53 PM PDT 24
Peak memory 212820 kb
Host smart-41b5b8f4-f409-43c4-a49b-06c214d8c94c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484419250 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keym
gr_dpe_shadow_reg_errors.1484419250
Directory /workspace/7.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.2051932008
Short name T58
Test name
Test status
Simulation time 326703029 ps
CPU time 9.48 seconds
Started Jun 08 01:52:55 PM PDT 24
Finished Jun 08 01:53:05 PM PDT 24
Peak memory 213048 kb
Host smart-ad1b2cfe-5031-48b0-8cbe-047164121406
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051932008 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.keymgr_dpe_shadow_reg_errors_with_csr_rw.2051932008
Directory /workspace/7.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.2654673161
Short name T278
Test name
Test status
Simulation time 82776216 ps
CPU time 2.41 seconds
Started Jun 08 01:52:56 PM PDT 24
Finished Jun 08 01:52:58 PM PDT 24
Peak memory 220684 kb
Host smart-611ad385-16e0-4a38-962c-194bdcc71636
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654673161 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_tl_errors.2
654673161
Directory /workspace/7.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.4113014462
Short name T52
Test name
Test status
Simulation time 616091246 ps
CPU time 4.88 seconds
Started Jun 08 01:52:55 PM PDT 24
Finished Jun 08 01:53:00 PM PDT 24
Peak memory 212764 kb
Host smart-2cee1a45-b8db-48cb-99af-329376b4edbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113014462 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe
_tl_intg_err.4113014462
Directory /workspace/7.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.440558962
Short name T270
Test name
Test status
Simulation time 35575797 ps
CPU time 1.6 seconds
Started Jun 08 01:53:02 PM PDT 24
Finished Jun 08 01:53:04 PM PDT 24
Peak memory 212744 kb
Host smart-d5de91c0-b552-480f-b7ad-90a78468f824
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440558962 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_mem_rw_with_rand_reset.440558962
Directory /workspace/8.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.4100756006
Short name T175
Test name
Test status
Simulation time 42198133 ps
CPU time 0.91 seconds
Started Jun 08 01:53:00 PM PDT 24
Finished Jun 08 01:53:01 PM PDT 24
Peak memory 204372 kb
Host smart-0b202ab3-9adc-4b97-9158-9c1944327bd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100756006 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_rw.4
100756006
Directory /workspace/8.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.3972567109
Short name T192
Test name
Test status
Simulation time 13791239 ps
CPU time 0.93 seconds
Started Jun 08 01:52:56 PM PDT 24
Finished Jun 08 01:52:57 PM PDT 24
Peak memory 204408 kb
Host smart-1735a6af-175f-4aca-b521-028b99bf37a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972567109 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_intr_test.3
972567109
Directory /workspace/8.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.109188339
Short name T253
Test name
Test status
Simulation time 111967931 ps
CPU time 1.14 seconds
Started Jun 08 01:53:00 PM PDT 24
Finished Jun 08 01:53:01 PM PDT 24
Peak memory 204528 kb
Host smart-e485eefe-bf90-4243-8cb9-ef60aac8baa9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109188339 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.ke
ymgr_dpe_same_csr_outstanding.109188339
Directory /workspace/8.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.597037453
Short name T304
Test name
Test status
Simulation time 31439010 ps
CPU time 1.21 seconds
Started Jun 08 01:52:54 PM PDT 24
Finished Jun 08 01:52:55 PM PDT 24
Peak memory 212924 kb
Host smart-cf3343cc-96d2-4a52-9cac-e22bcbe4ce96
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597037453 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymg
r_dpe_shadow_reg_errors.597037453
Directory /workspace/8.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.3050027631
Short name T266
Test name
Test status
Simulation time 145156007 ps
CPU time 5.22 seconds
Started Jun 08 01:52:59 PM PDT 24
Finished Jun 08 01:53:05 PM PDT 24
Peak memory 221204 kb
Host smart-60769be0-1c2a-45cf-b830-35c65ea17330
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050027631 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.keymgr_dpe_shadow_reg_errors_with_csr_rw.3050027631
Directory /workspace/8.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.613568558
Short name T39
Test name
Test status
Simulation time 450136299 ps
CPU time 3.66 seconds
Started Jun 08 01:53:00 PM PDT 24
Finished Jun 08 01:53:04 PM PDT 24
Peak memory 212748 kb
Host smart-36d34f26-0454-40c5-b132-0c5fe861a56b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613568558 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_tl_errors.613568558
Directory /workspace/8.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_intg_err.310443023
Short name T49
Test name
Test status
Simulation time 137087900 ps
CPU time 4.53 seconds
Started Jun 08 01:52:57 PM PDT 24
Finished Jun 08 01:53:01 PM PDT 24
Peak memory 213600 kb
Host smart-a8e276de-3f0a-4775-9226-b12275f50b49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310443023 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_
tl_intg_err.310443023
Directory /workspace/8.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.2297436615
Short name T267
Test name
Test status
Simulation time 40032966 ps
CPU time 0.97 seconds
Started Jun 08 01:53:06 PM PDT 24
Finished Jun 08 01:53:07 PM PDT 24
Peak memory 204416 kb
Host smart-632d8e0a-7116-4fca-9d54-f7289f4e2e27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297436615 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_mem_rw_with_rand_reset.2297436615
Directory /workspace/9.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.1201283927
Short name T79
Test name
Test status
Simulation time 26410229 ps
CPU time 1.11 seconds
Started Jun 08 01:53:05 PM PDT 24
Finished Jun 08 01:53:06 PM PDT 24
Peak memory 204428 kb
Host smart-5a11b7b5-937c-43dc-9576-4af5c807b66c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201283927 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_rw.1
201283927
Directory /workspace/9.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.2537741397
Short name T221
Test name
Test status
Simulation time 82652876 ps
CPU time 0.79 seconds
Started Jun 08 01:53:00 PM PDT 24
Finished Jun 08 01:53:01 PM PDT 24
Peak memory 204552 kb
Host smart-f01cd865-7596-47a2-9de1-2c1be090f018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537741397 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_intr_test.2
537741397
Directory /workspace/9.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.1377725700
Short name T247
Test name
Test status
Simulation time 18930520 ps
CPU time 1.4 seconds
Started Jun 08 01:53:02 PM PDT 24
Finished Jun 08 01:53:03 PM PDT 24
Peak memory 204444 kb
Host smart-bdd9d44b-a283-4485-b3ec-6b74ae820021
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377725700 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_dpe_same_csr_outstanding.1377725700
Directory /workspace/9.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.1212181410
Short name T198
Test name
Test status
Simulation time 62531122 ps
CPU time 1.19 seconds
Started Jun 08 01:52:59 PM PDT 24
Finished Jun 08 01:53:01 PM PDT 24
Peak memory 213036 kb
Host smart-d5500884-1262-4f61-aa3d-db81edff5730
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212181410 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keym
gr_dpe_shadow_reg_errors.1212181410
Directory /workspace/9.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.328476660
Short name T281
Test name
Test status
Simulation time 116392869 ps
CPU time 3.58 seconds
Started Jun 08 01:53:01 PM PDT 24
Finished Jun 08 01:53:05 PM PDT 24
Peak memory 213040 kb
Host smart-a876eb11-6b82-43d0-950c-80313b713778
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328476660 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.keymgr_dpe_shadow_reg_errors_with_csr_rw.328476660
Directory /workspace/9.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.512761110
Short name T299
Test name
Test status
Simulation time 211873283 ps
CPU time 1.67 seconds
Started Jun 08 01:53:01 PM PDT 24
Finished Jun 08 01:53:03 PM PDT 24
Peak memory 212688 kb
Host smart-dfe06d91-fc39-4001-9287-0db5a7a074b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512761110 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_tl_errors.512761110
Directory /workspace/9.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_dpe_alert_test.2812624433
Short name T68
Test name
Test status
Simulation time 14247612 ps
CPU time 0.94 seconds
Started Jun 08 01:46:39 PM PDT 24
Finished Jun 08 01:46:40 PM PDT 24
Peak memory 205596 kb
Host smart-1b890ffa-a215-40ab-b0c5-5acba55989a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812624433 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_alert_test.2
812624433
Directory /workspace/0.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_dpe_smoke.2050935057
Short name T27
Test name
Test status
Simulation time 2035493702 ps
CPU time 18.8 seconds
Started Jun 08 01:46:44 PM PDT 24
Finished Jun 08 01:47:04 PM PDT 24
Peak memory 208244 kb
Host smart-82e50989-a4f8-4aad-b45e-ed86cf30c1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050935057 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_smoke.2050935057
Directory /workspace/0.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/1.keymgr_dpe_alert_test.1892786395
Short name T126
Test name
Test status
Simulation time 10257584 ps
CPU time 0.74 seconds
Started Jun 08 01:46:43 PM PDT 24
Finished Jun 08 01:46:44 PM PDT 24
Peak memory 205488 kb
Host smart-8f7d84fa-bde3-488d-93b1-e1836bcf44ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892786395 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_alert_test.1
892786395
Directory /workspace/1.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_dpe_sec_cm.3932112503
Short name T21
Test name
Test status
Simulation time 2024495170 ps
CPU time 15.08 seconds
Started Jun 08 01:46:41 PM PDT 24
Finished Jun 08 01:46:56 PM PDT 24
Peak memory 230960 kb
Host smart-5a2f46ea-ef82-4fbe-b042-d7c69be7bf08
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932112503 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_sec_cm.3932112503
Directory /workspace/1.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/10.keymgr_dpe_alert_test.3673023701
Short name T23
Test name
Test status
Simulation time 9627793 ps
CPU time 0.69 seconds
Started Jun 08 01:46:43 PM PDT 24
Finished Jun 08 01:46:44 PM PDT 24
Peak memory 205448 kb
Host smart-da1d26d0-ba78-4e9b-b559-f15dd273a7db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673023701 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_alert_test.
3673023701
Directory /workspace/10.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_dpe_alert_test.2299455472
Short name T108
Test name
Test status
Simulation time 21366904 ps
CPU time 0.73 seconds
Started Jun 08 01:46:39 PM PDT 24
Finished Jun 08 01:46:40 PM PDT 24
Peak memory 205436 kb
Host smart-43664bee-2e13-4dd1-8c0a-a6f4184a98f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299455472 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_alert_test.
2299455472
Directory /workspace/11.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_dpe_alert_test.450245739
Short name T133
Test name
Test status
Simulation time 26999287 ps
CPU time 0.74 seconds
Started Jun 08 01:46:44 PM PDT 24
Finished Jun 08 01:46:45 PM PDT 24
Peak memory 205496 kb
Host smart-c13518b4-7afc-4a61-9064-f5968a528a56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450245739 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_alert_test.450245739
Directory /workspace/12.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_dpe_alert_test.1722305222
Short name T110
Test name
Test status
Simulation time 12540756 ps
CPU time 0.67 seconds
Started Jun 08 01:46:47 PM PDT 24
Finished Jun 08 01:46:47 PM PDT 24
Peak memory 205456 kb
Host smart-09e1eb73-505b-4293-8644-d79f7982f812
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722305222 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_alert_test.
1722305222
Directory /workspace/13.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_dpe_alert_test.3046605315
Short name T116
Test name
Test status
Simulation time 11155444 ps
CPU time 0.75 seconds
Started Jun 08 01:46:45 PM PDT 24
Finished Jun 08 01:46:46 PM PDT 24
Peak memory 205544 kb
Host smart-94156265-726f-4c07-bdb1-c620db9fe626
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046605315 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_alert_test.
3046605315
Directory /workspace/14.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_dpe_alert_test.945220774
Short name T121
Test name
Test status
Simulation time 39688271 ps
CPU time 0.75 seconds
Started Jun 08 01:46:45 PM PDT 24
Finished Jun 08 01:46:46 PM PDT 24
Peak memory 205492 kb
Host smart-154c669a-4d9f-44fa-b1ad-eb4a8d1f5614
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945220774 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_alert_test.945220774
Directory /workspace/15.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_dpe_alert_test.1553052691
Short name T15
Test name
Test status
Simulation time 22270045 ps
CPU time 0.88 seconds
Started Jun 08 01:46:44 PM PDT 24
Finished Jun 08 01:46:46 PM PDT 24
Peak memory 205544 kb
Host smart-1de4b010-43d4-494d-bd6c-b70b1d3734e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553052691 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_alert_test.
1553052691
Directory /workspace/16.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_dpe_alert_test.3090159592
Short name T149
Test name
Test status
Simulation time 15453839 ps
CPU time 0.86 seconds
Started Jun 08 01:46:40 PM PDT 24
Finished Jun 08 01:46:41 PM PDT 24
Peak memory 205688 kb
Host smart-4130cd1e-421a-46fc-8302-9e737be3d484
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090159592 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_alert_test.
3090159592
Directory /workspace/17.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_dpe_alert_test.2819972115
Short name T157
Test name
Test status
Simulation time 18160035 ps
CPU time 0.93 seconds
Started Jun 08 01:46:38 PM PDT 24
Finished Jun 08 01:46:39 PM PDT 24
Peak memory 205596 kb
Host smart-bdba44b4-1848-4293-85cc-dbe766e3740c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819972115 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_alert_test.
2819972115
Directory /workspace/18.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_dpe_smoke.3968934398
Short name T4
Test name
Test status
Simulation time 1683517310 ps
CPU time 17.16 seconds
Started Jun 08 01:46:41 PM PDT 24
Finished Jun 08 01:46:59 PM PDT 24
Peak memory 208160 kb
Host smart-a748ac09-c49d-497a-a229-e2f219c131d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968934398 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_smoke.3968934398
Directory /workspace/18.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/19.keymgr_dpe_alert_test.3443139947
Short name T155
Test name
Test status
Simulation time 13942377 ps
CPU time 0.92 seconds
Started Jun 08 01:46:44 PM PDT 24
Finished Jun 08 01:46:46 PM PDT 24
Peak memory 205712 kb
Host smart-1605cf28-1ac2-4267-b2c7-ec0ac2779d6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443139947 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_alert_test.
3443139947
Directory /workspace/19.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_dpe_smoke.3211699609
Short name T75
Test name
Test status
Simulation time 3418311790 ps
CPU time 31.38 seconds
Started Jun 08 01:46:48 PM PDT 24
Finished Jun 08 01:47:19 PM PDT 24
Peak memory 207880 kb
Host smart-fcc99d0b-9cd9-4c6c-8bc4-bcd497532c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211699609 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_smoke.3211699609
Directory /workspace/19.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_alert_test.2828561900
Short name T130
Test name
Test status
Simulation time 110376882 ps
CPU time 0.79 seconds
Started Jun 08 01:46:40 PM PDT 24
Finished Jun 08 01:46:41 PM PDT 24
Peak memory 205452 kb
Host smart-7ac8e758-e798-4314-b80d-1213cf2a9404
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828561900 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_alert_test.2
828561900
Directory /workspace/2.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_dpe_alert_test.3716708607
Short name T153
Test name
Test status
Simulation time 62286076 ps
CPU time 0.71 seconds
Started Jun 08 01:46:45 PM PDT 24
Finished Jun 08 01:46:46 PM PDT 24
Peak memory 205544 kb
Host smart-69289d3c-f32e-44ce-88cb-68d5fec2814f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716708607 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_alert_test.
3716708607
Directory /workspace/20.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_dpe_smoke.2678047443
Short name T154
Test name
Test status
Simulation time 3632311374 ps
CPU time 27.94 seconds
Started Jun 08 01:46:49 PM PDT 24
Finished Jun 08 01:47:17 PM PDT 24
Peak memory 208532 kb
Host smart-bf608f80-3991-46ac-8be4-6374289c4ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678047443 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_smoke.2678047443
Directory /workspace/20.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/21.keymgr_dpe_alert_test.1685012902
Short name T152
Test name
Test status
Simulation time 16145611 ps
CPU time 0.89 seconds
Started Jun 08 01:46:51 PM PDT 24
Finished Jun 08 01:46:52 PM PDT 24
Peak memory 205584 kb
Host smart-52909907-b534-45f1-b751-c2a5109bbc7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685012902 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_alert_test.
1685012902
Directory /workspace/21.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_dpe_smoke.90576121
Short name T137
Test name
Test status
Simulation time 923702792 ps
CPU time 18.2 seconds
Started Jun 08 01:46:54 PM PDT 24
Finished Jun 08 01:47:12 PM PDT 24
Peak memory 206680 kb
Host smart-c6b37857-0d03-4b43-8b3e-04a937ea5071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90576121 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_smoke.90576121
Directory /workspace/21.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/22.keymgr_dpe_smoke.2808371519
Short name T83
Test name
Test status
Simulation time 644184106 ps
CPU time 9.69 seconds
Started Jun 08 01:46:48 PM PDT 24
Finished Jun 08 01:46:58 PM PDT 24
Peak memory 206184 kb
Host smart-c6e4aee5-0cb6-4849-86cd-19299eecef8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808371519 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_smoke.2808371519
Directory /workspace/22.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/23.keymgr_dpe_alert_test.4075932357
Short name T129
Test name
Test status
Simulation time 45091555 ps
CPU time 0.74 seconds
Started Jun 08 01:46:50 PM PDT 24
Finished Jun 08 01:46:51 PM PDT 24
Peak memory 205420 kb
Host smart-70501988-4dbd-4b8d-b3cf-f9ce54ab3784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075932357 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_alert_test.
4075932357
Directory /workspace/23.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_dpe_smoke.3883135138
Short name T150
Test name
Test status
Simulation time 1184160746 ps
CPU time 21.96 seconds
Started Jun 08 01:46:46 PM PDT 24
Finished Jun 08 01:47:08 PM PDT 24
Peak memory 207468 kb
Host smart-0da58988-7a71-429f-8eb6-76f25bee0068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883135138 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_smoke.3883135138
Directory /workspace/23.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/24.keymgr_dpe_alert_test.4222656770
Short name T105
Test name
Test status
Simulation time 27271816 ps
CPU time 0.73 seconds
Started Jun 08 01:46:44 PM PDT 24
Finished Jun 08 01:46:44 PM PDT 24
Peak memory 205468 kb
Host smart-a63fa85d-bf2e-4dcc-90df-09218a64f9be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222656770 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_alert_test.
4222656770
Directory /workspace/24.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_dpe_smoke.51660957
Short name T146
Test name
Test status
Simulation time 415878482 ps
CPU time 13.47 seconds
Started Jun 08 01:46:42 PM PDT 24
Finished Jun 08 01:46:55 PM PDT 24
Peak memory 207860 kb
Host smart-57b4b856-f2a0-40e0-933d-4a60e5e8bab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51660957 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_smoke.51660957
Directory /workspace/24.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/25.keymgr_dpe_alert_test.696660588
Short name T3
Test name
Test status
Simulation time 9901473 ps
CPU time 0.81 seconds
Started Jun 08 01:46:53 PM PDT 24
Finished Jun 08 01:46:54 PM PDT 24
Peak memory 205420 kb
Host smart-9c416a09-a964-4638-ac54-bc60f824a62e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696660588 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_alert_test.696660588
Directory /workspace/25.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_dpe_smoke.2828998810
Short name T139
Test name
Test status
Simulation time 43219578930 ps
CPU time 194.25 seconds
Started Jun 08 01:46:46 PM PDT 24
Finished Jun 08 01:50:01 PM PDT 24
Peak memory 208152 kb
Host smart-c099d83c-7782-46b4-b51b-51be06efc46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828998810 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_smoke.2828998810
Directory /workspace/25.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/26.keymgr_dpe_alert_test.2562517670
Short name T135
Test name
Test status
Simulation time 108241604 ps
CPU time 0.86 seconds
Started Jun 08 01:46:48 PM PDT 24
Finished Jun 08 01:46:49 PM PDT 24
Peak memory 205544 kb
Host smart-01c19e6b-4957-4c02-9773-22a61971732b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562517670 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_alert_test.
2562517670
Directory /workspace/26.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_dpe_alert_test.3839443412
Short name T141
Test name
Test status
Simulation time 35867934 ps
CPU time 0.74 seconds
Started Jun 08 01:46:48 PM PDT 24
Finished Jun 08 01:46:49 PM PDT 24
Peak memory 205464 kb
Host smart-9d3f9841-c8d6-4c18-9ede-ab160b03a5f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839443412 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_alert_test.
3839443412
Directory /workspace/27.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_dpe_alert_test.1096947290
Short name T112
Test name
Test status
Simulation time 9930665 ps
CPU time 0.81 seconds
Started Jun 08 01:46:49 PM PDT 24
Finished Jun 08 01:46:50 PM PDT 24
Peak memory 205512 kb
Host smart-f8f896b3-e97e-429a-af29-a8f40d57610f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096947290 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_alert_test.
1096947290
Directory /workspace/28.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_dpe_alert_test.3314401446
Short name T118
Test name
Test status
Simulation time 22132969 ps
CPU time 0.79 seconds
Started Jun 08 01:46:52 PM PDT 24
Finished Jun 08 01:46:52 PM PDT 24
Peak memory 205468 kb
Host smart-2e814ad6-d33d-4b59-9cf4-f8564e8a70e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314401446 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_alert_test.
3314401446
Directory /workspace/29.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_dpe_smoke.1569942779
Short name T82
Test name
Test status
Simulation time 405843356 ps
CPU time 11.36 seconds
Started Jun 08 01:46:50 PM PDT 24
Finished Jun 08 01:47:02 PM PDT 24
Peak memory 206316 kb
Host smart-e3de8e1c-221f-4a14-8163-edcb2b1b6cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569942779 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_smoke.1569942779
Directory /workspace/29.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/3.keymgr_dpe_alert_test.2985642378
Short name T122
Test name
Test status
Simulation time 29629310 ps
CPU time 0.94 seconds
Started Jun 08 01:46:43 PM PDT 24
Finished Jun 08 01:46:44 PM PDT 24
Peak memory 205648 kb
Host smart-b09fcf27-08c5-4c99-9f57-6804bd0a30a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985642378 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_alert_test.2
985642378
Directory /workspace/3.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_sec_cm.1921309136
Short name T7
Test name
Test status
Simulation time 1277975002 ps
CPU time 13.38 seconds
Started Jun 08 01:46:33 PM PDT 24
Finished Jun 08 01:46:46 PM PDT 24
Peak memory 236124 kb
Host smart-389be496-269b-43b3-ba22-28417ebce0f4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921309136 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_sec_cm.1921309136
Directory /workspace/3.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_dpe_smoke.1413247173
Short name T156
Test name
Test status
Simulation time 9534104149 ps
CPU time 18.21 seconds
Started Jun 08 01:46:45 PM PDT 24
Finished Jun 08 01:47:03 PM PDT 24
Peak memory 206848 kb
Host smart-dc9300ee-08aa-4b90-bc40-139bd58ccc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413247173 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_smoke.1413247173
Directory /workspace/3.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/30.keymgr_dpe_alert_test.1684218310
Short name T134
Test name
Test status
Simulation time 10784076 ps
CPU time 0.85 seconds
Started Jun 08 01:46:56 PM PDT 24
Finished Jun 08 01:46:57 PM PDT 24
Peak memory 205532 kb
Host smart-4dd293cc-970a-4e82-9f4f-83cb2ecc12f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684218310 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_alert_test.
1684218310
Directory /workspace/30.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_dpe_alert_test.1170363808
Short name T114
Test name
Test status
Simulation time 33048428 ps
CPU time 0.76 seconds
Started Jun 08 01:46:48 PM PDT 24
Finished Jun 08 01:46:49 PM PDT 24
Peak memory 205492 kb
Host smart-5b71586d-c2ca-4774-ac77-f22b74e48383
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170363808 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_alert_test.
1170363808
Directory /workspace/31.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_alert_test.3561416291
Short name T24
Test name
Test status
Simulation time 25700566 ps
CPU time 0.83 seconds
Started Jun 08 01:46:55 PM PDT 24
Finished Jun 08 01:46:56 PM PDT 24
Peak memory 205720 kb
Host smart-ae33332d-b184-45d9-a645-58916f7f53c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561416291 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_alert_test.
3561416291
Directory /workspace/32.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_smoke.373027117
Short name T25
Test name
Test status
Simulation time 675693685 ps
CPU time 20.79 seconds
Started Jun 08 01:46:52 PM PDT 24
Finished Jun 08 01:47:13 PM PDT 24
Peak memory 208248 kb
Host smart-e06358a3-455b-49f3-997b-8385d2653c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373027117 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_smoke.373027117
Directory /workspace/32.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/33.keymgr_dpe_alert_test.2789136397
Short name T142
Test name
Test status
Simulation time 14409160 ps
CPU time 0.8 seconds
Started Jun 08 01:46:54 PM PDT 24
Finished Jun 08 01:46:55 PM PDT 24
Peak memory 205540 kb
Host smart-dd48d269-8fdf-4c4b-802c-2917575d1772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789136397 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_alert_test.
2789136397
Directory /workspace/33.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_dpe_alert_test.3915329000
Short name T144
Test name
Test status
Simulation time 11414864 ps
CPU time 0.71 seconds
Started Jun 08 01:46:51 PM PDT 24
Finished Jun 08 01:46:52 PM PDT 24
Peak memory 205540 kb
Host smart-5df87200-46df-4f3a-aaf3-fb7cdfd6006b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915329000 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_alert_test.
3915329000
Directory /workspace/34.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_dpe_smoke.132453452
Short name T151
Test name
Test status
Simulation time 8811843582 ps
CPU time 103.84 seconds
Started Jun 08 01:46:56 PM PDT 24
Finished Jun 08 01:48:40 PM PDT 24
Peak memory 207756 kb
Host smart-c2b05a4a-6b3c-46c3-9486-f222f7825864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132453452 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_smoke.132453452
Directory /workspace/34.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/35.keymgr_dpe_alert_test.1051445395
Short name T125
Test name
Test status
Simulation time 38016090 ps
CPU time 0.82 seconds
Started Jun 08 01:46:49 PM PDT 24
Finished Jun 08 01:46:50 PM PDT 24
Peak memory 205468 kb
Host smart-42474ac7-eeeb-41ab-84d4-c8f4adc4aa8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051445395 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_alert_test.
1051445395
Directory /workspace/35.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_alert_test.81387913
Short name T132
Test name
Test status
Simulation time 111485127 ps
CPU time 0.95 seconds
Started Jun 08 01:46:59 PM PDT 24
Finished Jun 08 01:47:00 PM PDT 24
Peak memory 205544 kb
Host smart-27dcd7dc-26c8-430a-86f6-63e00118d834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81387913 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_alert_test.81387913
Directory /workspace/36.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_smoke.2875765499
Short name T28
Test name
Test status
Simulation time 32515751301 ps
CPU time 149.39 seconds
Started Jun 08 01:46:54 PM PDT 24
Finished Jun 08 01:49:24 PM PDT 24
Peak memory 208012 kb
Host smart-00f863a2-59b5-475b-93c2-da13d1f4c7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875765499 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_smoke.2875765499
Directory /workspace/36.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/37.keymgr_dpe_alert_test.3694284037
Short name T109
Test name
Test status
Simulation time 35905477 ps
CPU time 0.73 seconds
Started Jun 08 01:46:55 PM PDT 24
Finished Jun 08 01:46:56 PM PDT 24
Peak memory 205540 kb
Host smart-a5390e20-bde0-4c8e-939c-379801e23964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694284037 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_alert_test.
3694284037
Directory /workspace/37.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_dpe_smoke.3609423081
Short name T143
Test name
Test status
Simulation time 4909104939 ps
CPU time 65.57 seconds
Started Jun 08 01:46:55 PM PDT 24
Finished Jun 08 01:48:00 PM PDT 24
Peak memory 208500 kb
Host smart-8a0a7dd5-242b-49d5-843f-bf84328ec706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609423081 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_smoke.3609423081
Directory /workspace/37.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/38.keymgr_dpe_alert_test.1278256145
Short name T124
Test name
Test status
Simulation time 60002829 ps
CPU time 0.91 seconds
Started Jun 08 01:46:55 PM PDT 24
Finished Jun 08 01:46:56 PM PDT 24
Peak memory 205564 kb
Host smart-b0f20124-3965-423e-bdd4-c18baaee2455
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278256145 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_alert_test.
1278256145
Directory /workspace/38.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_dpe_smoke.2108894535
Short name T70
Test name
Test status
Simulation time 2440638135 ps
CPU time 34.03 seconds
Started Jun 08 01:47:02 PM PDT 24
Finished Jun 08 01:47:36 PM PDT 24
Peak memory 208580 kb
Host smart-c1ab9fa1-f7ce-436a-a77f-4a5a058bd55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108894535 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_smoke.2108894535
Directory /workspace/38.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/39.keymgr_dpe_alert_test.1649670686
Short name T107
Test name
Test status
Simulation time 64907461 ps
CPU time 0.79 seconds
Started Jun 08 01:46:53 PM PDT 24
Finished Jun 08 01:46:54 PM PDT 24
Peak memory 205548 kb
Host smart-035d1d08-5ce9-4a81-8dcd-c1d0736b1f11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649670686 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_alert_test.
1649670686
Directory /workspace/39.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_dpe_smoke.529402768
Short name T117
Test name
Test status
Simulation time 1009285694 ps
CPU time 16.75 seconds
Started Jun 08 01:46:57 PM PDT 24
Finished Jun 08 01:47:14 PM PDT 24
Peak memory 208136 kb
Host smart-719c7a06-6139-44aa-a043-0f6cd14dc363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529402768 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_smoke.529402768
Directory /workspace/39.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/4.keymgr_dpe_alert_test.2421930157
Short name T111
Test name
Test status
Simulation time 46237431 ps
CPU time 0.9 seconds
Started Jun 08 01:46:44 PM PDT 24
Finished Jun 08 01:46:45 PM PDT 24
Peak memory 205436 kb
Host smart-024a5b7d-5613-4929-9260-c10147abf3ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421930157 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_alert_test.2
421930157
Directory /workspace/4.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_sec_cm.2180554950
Short name T5
Test name
Test status
Simulation time 3180130611 ps
CPU time 22.07 seconds
Started Jun 08 01:46:44 PM PDT 24
Finished Jun 08 01:47:07 PM PDT 24
Peak memory 233124 kb
Host smart-d95466be-c074-4906-9fd2-965015f327dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180554950 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_sec_cm.2180554950
Directory /workspace/4.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/40.keymgr_dpe_alert_test.1099910674
Short name T127
Test name
Test status
Simulation time 21744813 ps
CPU time 0.77 seconds
Started Jun 08 01:46:54 PM PDT 24
Finished Jun 08 01:46:55 PM PDT 24
Peak memory 205444 kb
Host smart-0bfda8e7-558d-4909-badf-b7fd8f69ae67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099910674 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_alert_test.
1099910674
Directory /workspace/40.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_dpe_smoke.1673509319
Short name T159
Test name
Test status
Simulation time 12319074957 ps
CPU time 96.71 seconds
Started Jun 08 01:47:00 PM PDT 24
Finished Jun 08 01:48:37 PM PDT 24
Peak memory 208200 kb
Host smart-b306c1f8-080d-44ae-9d47-4f1919b265d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673509319 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_smoke.1673509319
Directory /workspace/40.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/41.keymgr_dpe_alert_test.38706547
Short name T123
Test name
Test status
Simulation time 22667834 ps
CPU time 0.79 seconds
Started Jun 08 01:46:59 PM PDT 24
Finished Jun 08 01:47:00 PM PDT 24
Peak memory 205540 kb
Host smart-958b4472-1fef-4ad7-b5c0-e480f0bb13d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38706547 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_alert_test.38706547
Directory /workspace/41.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_dpe_alert_test.3794139546
Short name T128
Test name
Test status
Simulation time 69879654 ps
CPU time 0.86 seconds
Started Jun 08 01:47:03 PM PDT 24
Finished Jun 08 01:47:04 PM PDT 24
Peak memory 205496 kb
Host smart-6ba0b4ef-2ccc-42d6-89a9-5fb60c52830d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794139546 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_alert_test.
3794139546
Directory /workspace/42.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_dpe_smoke.1044029569
Short name T94
Test name
Test status
Simulation time 864632786 ps
CPU time 11.45 seconds
Started Jun 08 01:46:56 PM PDT 24
Finished Jun 08 01:47:08 PM PDT 24
Peak memory 208004 kb
Host smart-aaafb289-e04e-41e1-a502-65e623bbd121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044029569 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_smoke.1044029569
Directory /workspace/42.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/43.keymgr_dpe_alert_test.588791335
Short name T115
Test name
Test status
Simulation time 38997399 ps
CPU time 0.73 seconds
Started Jun 08 01:47:01 PM PDT 24
Finished Jun 08 01:47:02 PM PDT 24
Peak memory 205340 kb
Host smart-59d85691-e849-4319-9945-77d15931dbfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588791335 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_alert_test.588791335
Directory /workspace/43.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_dpe_smoke.3277611556
Short name T26
Test name
Test status
Simulation time 2198238229 ps
CPU time 14.74 seconds
Started Jun 08 01:47:04 PM PDT 24
Finished Jun 08 01:47:19 PM PDT 24
Peak memory 208232 kb
Host smart-be5aa3b7-7a1c-4be8-bb83-9ffacb657c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277611556 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_smoke.3277611556
Directory /workspace/43.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/44.keymgr_dpe_alert_test.2398181005
Short name T136
Test name
Test status
Simulation time 90936845 ps
CPU time 0.71 seconds
Started Jun 08 01:46:59 PM PDT 24
Finished Jun 08 01:47:00 PM PDT 24
Peak memory 205660 kb
Host smart-f6520baa-19f1-4755-8f11-8966ea0ad735
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398181005 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_alert_test.
2398181005
Directory /workspace/44.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_dpe_smoke.3859893024
Short name T92
Test name
Test status
Simulation time 707413552 ps
CPU time 14.37 seconds
Started Jun 08 01:47:00 PM PDT 24
Finished Jun 08 01:47:15 PM PDT 24
Peak memory 208052 kb
Host smart-e0c82591-6ab1-4158-b3a9-712b60804e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859893024 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_smoke.3859893024
Directory /workspace/44.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/45.keymgr_dpe_alert_test.3400240964
Short name T106
Test name
Test status
Simulation time 11189908 ps
CPU time 0.74 seconds
Started Jun 08 01:46:59 PM PDT 24
Finished Jun 08 01:47:00 PM PDT 24
Peak memory 205496 kb
Host smart-07df31ae-84f2-4a11-9b65-ccdb5935eb65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400240964 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_alert_test.
3400240964
Directory /workspace/45.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_dpe_smoke.1211024645
Short name T98
Test name
Test status
Simulation time 232355111 ps
CPU time 12.34 seconds
Started Jun 08 01:46:57 PM PDT 24
Finished Jun 08 01:47:10 PM PDT 24
Peak memory 207368 kb
Host smart-698c5a76-f2e4-412a-b73f-0ff039dde947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211024645 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_smoke.1211024645
Directory /workspace/45.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/46.keymgr_dpe_alert_test.3150431732
Short name T120
Test name
Test status
Simulation time 43636581 ps
CPU time 0.7 seconds
Started Jun 08 01:46:58 PM PDT 24
Finished Jun 08 01:46:59 PM PDT 24
Peak memory 205476 kb
Host smart-3d3b0eeb-61b7-4650-96e2-0cbdc2fb1643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150431732 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_alert_test.
3150431732
Directory /workspace/46.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_dpe_smoke.3765813161
Short name T9
Test name
Test status
Simulation time 229465203 ps
CPU time 10.81 seconds
Started Jun 08 01:46:58 PM PDT 24
Finished Jun 08 01:47:09 PM PDT 24
Peak memory 206788 kb
Host smart-a141916a-652d-40df-9346-552e68d9e1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765813161 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_smoke.3765813161
Directory /workspace/46.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/47.keymgr_dpe_alert_test.468994716
Short name T16
Test name
Test status
Simulation time 34596419 ps
CPU time 0.71 seconds
Started Jun 08 01:46:59 PM PDT 24
Finished Jun 08 01:47:00 PM PDT 24
Peak memory 205436 kb
Host smart-30e5fc02-2d37-4023-822b-bc72f32f6b2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468994716 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_alert_test.468994716
Directory /workspace/47.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_dpe_smoke.3421438428
Short name T14
Test name
Test status
Simulation time 241871648 ps
CPU time 8.31 seconds
Started Jun 08 01:47:01 PM PDT 24
Finished Jun 08 01:47:10 PM PDT 24
Peak memory 206716 kb
Host smart-004cfb98-effa-434d-8fa5-9c323d905881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421438428 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_smoke.3421438428
Directory /workspace/47.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/48.keymgr_dpe_alert_test.3610648211
Short name T147
Test name
Test status
Simulation time 44345090 ps
CPU time 0.73 seconds
Started Jun 08 01:47:06 PM PDT 24
Finished Jun 08 01:47:07 PM PDT 24
Peak memory 205384 kb
Host smart-92fad340-07ad-4767-903a-65b3ba45e8b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610648211 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_alert_test.
3610648211
Directory /workspace/48.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_dpe_smoke.215258515
Short name T84
Test name
Test status
Simulation time 840701894 ps
CPU time 14.08 seconds
Started Jun 08 01:47:04 PM PDT 24
Finished Jun 08 01:47:19 PM PDT 24
Peak memory 208492 kb
Host smart-2c444c69-658d-43f7-becf-143d8bf4e625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215258515 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_smoke.215258515
Directory /workspace/48.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/49.keymgr_dpe_alert_test.1816825353
Short name T158
Test name
Test status
Simulation time 13399186 ps
CPU time 0.74 seconds
Started Jun 08 01:47:02 PM PDT 24
Finished Jun 08 01:47:03 PM PDT 24
Peak memory 205408 kb
Host smart-68808789-ae9b-4b0d-a0bb-66fefa9a3096
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816825353 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_alert_test.
1816825353
Directory /workspace/49.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_dpe_smoke.3447903305
Short name T119
Test name
Test status
Simulation time 229320093 ps
CPU time 12.86 seconds
Started Jun 08 01:47:04 PM PDT 24
Finished Jun 08 01:47:17 PM PDT 24
Peak memory 208112 kb
Host smart-a7208171-2afe-40f0-88e7-44c9ce579001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447903305 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_smoke.3447903305
Directory /workspace/49.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/5.keymgr_dpe_alert_test.1086747473
Short name T103
Test name
Test status
Simulation time 8720447 ps
CPU time 0.78 seconds
Started Jun 08 01:46:34 PM PDT 24
Finished Jun 08 01:46:35 PM PDT 24
Peak memory 205528 kb
Host smart-5fad25e1-dcb8-4a55-ba1e-7d1d8a437c81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086747473 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_alert_test.1
086747473
Directory /workspace/5.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_dpe_smoke.1893415777
Short name T145
Test name
Test status
Simulation time 772239614 ps
CPU time 22.07 seconds
Started Jun 08 01:46:40 PM PDT 24
Finished Jun 08 01:47:03 PM PDT 24
Peak memory 206796 kb
Host smart-cef39dd3-2cc6-470e-8f8b-da4b5d30706a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893415777 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_smoke.1893415777
Directory /workspace/5.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/6.keymgr_dpe_alert_test.874623538
Short name T148
Test name
Test status
Simulation time 12741925 ps
CPU time 0.9 seconds
Started Jun 08 01:46:46 PM PDT 24
Finished Jun 08 01:46:47 PM PDT 24
Peak memory 205432 kb
Host smart-1f78be4f-c32e-4938-bc45-dc6ecee93177
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874623538 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_alert_test.874623538
Directory /workspace/6.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_dpe_smoke.4234414286
Short name T74
Test name
Test status
Simulation time 1988757835 ps
CPU time 19.17 seconds
Started Jun 08 01:46:45 PM PDT 24
Finished Jun 08 01:47:04 PM PDT 24
Peak memory 207496 kb
Host smart-b46a21ac-7eea-483c-833a-bd926e4b4d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234414286 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_smoke.4234414286
Directory /workspace/6.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/7.keymgr_dpe_alert_test.4167163275
Short name T17
Test name
Test status
Simulation time 23018589 ps
CPU time 0.75 seconds
Started Jun 08 01:46:39 PM PDT 24
Finished Jun 08 01:46:40 PM PDT 24
Peak memory 205520 kb
Host smart-7bd1a8c0-a82d-4c18-bba0-0a4560da8210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167163275 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_alert_test.4
167163275
Directory /workspace/7.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_dpe_smoke.2812256548
Short name T131
Test name
Test status
Simulation time 1806941878 ps
CPU time 25.73 seconds
Started Jun 08 01:46:45 PM PDT 24
Finished Jun 08 01:47:11 PM PDT 24
Peak memory 206544 kb
Host smart-59bf9a8d-f240-4e76-96f0-0efbca963fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812256548 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_smoke.2812256548
Directory /workspace/7.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/8.keymgr_dpe_alert_test.2689667715
Short name T113
Test name
Test status
Simulation time 13506314 ps
CPU time 0.73 seconds
Started Jun 08 01:46:44 PM PDT 24
Finished Jun 08 01:46:45 PM PDT 24
Peak memory 205504 kb
Host smart-3112340b-f8b2-4b6a-9c1c-8457c51c755a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689667715 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_alert_test.2
689667715
Directory /workspace/8.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_dpe_smoke.2385213337
Short name T96
Test name
Test status
Simulation time 2597578952 ps
CPU time 21.95 seconds
Started Jun 08 01:46:46 PM PDT 24
Finished Jun 08 01:47:09 PM PDT 24
Peak memory 207412 kb
Host smart-73450853-e67a-4357-8818-0495d94b3bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385213337 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_smoke.2385213337
Directory /workspace/8.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/9.keymgr_dpe_alert_test.650687961
Short name T140
Test name
Test status
Simulation time 21781669 ps
CPU time 0.79 seconds
Started Jun 08 01:46:45 PM PDT 24
Finished Jun 08 01:46:46 PM PDT 24
Peak memory 205492 kb
Host smart-cce918c1-7d5a-427b-aa0f-8b818d4eee33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650687961 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_alert_test.650687961
Directory /workspace/9.keymgr_dpe_alert_test/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%