ADC_CTRL Simulation Results

Tuesday May 16 2023 07:02:31 UTC

GitHub Revision: `50278df8b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1341560578

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.320s	5.900ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.840s	903.106us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.920s	543.662us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.914m	52.574ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.250s	1.097ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.090s	498.586us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.920s	543.662us	20	20	100.00
		adc_ctrl_csr_aliasing	4.250s	1.097ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.927m	490.431ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.421m	488.380ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.512m	490.305ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.813m	489.221ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	21.368m	532.745ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	19.386m	491.305ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	19.925m	506.348ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	18.988m	513.531ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.090s	5.607ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.892m	47.569ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.900m	136.918ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	27.721m	645.844ms	47	50	94.00
V2	alert_test	adc_ctrl_alert_test	1.820s	528.208us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.900s	499.771us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.970s	451.196us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.970s	451.196us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.840s	903.106us	5	5	100.00
		adc_ctrl_csr_rw	1.920s	543.662us	20	20	100.00
		adc_ctrl_csr_aliasing	4.250s	1.097ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.070s	5.108ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.840s	903.106us	5	5	100.00
		adc_ctrl_csr_rw	1.920s	543.662us	20	20	100.00
		adc_ctrl_csr_aliasing	4.250s	1.097ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.070s	5.108ms	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	tl_intg_err	adc_ctrl_sec_cm	10.710s	4.502ms	5	5	100.00
		adc_ctrl_tl_intg_err	20.470s	8.362ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	20.470s	8.362ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.008m	870.623ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			897	920	97.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.56	99.01	95.70	100.00	100.00	98.18	98.64	91.37

Failure Buckets

Offending '(wakeup_time == cfg_wakeup_time)' has 20 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 20 failures.
  - 2.adc_ctrl_stress_all_with_rand_reset.1042374733
    Line 452, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 194112047707 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 194112047707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 3.adc_ctrl_stress_all_with_rand_reset.2758729209
    Line 337, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 7827085024 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 7827085024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 18 more failures.

UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state

has 3 failures:

Test adc_ctrl_stress_all has 3 failures.

2.adc_ctrl_stress_all.1477479273
Line 329, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 340781368873 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 340781368873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.adc_ctrl_stress_all.3228277441
Line 354, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 409339144337 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 409339144337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.