Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1169774	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1123273

1

T5

6

T6

45

T1

39

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2011828	1			T5	11		T6	28		T1	31
values[0x0]	140323	1			T5	7		T6	17		T1	18
values[0x1]	140896	1			T5	6		T6	18		T1	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	942341	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1350706

1

T5

9

T6

50

T1

47

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7314	1			T2	18		T3	2		T25	1
valid_sources[0x01]	6722	1			T25	1		T9	5		T31	3
valid_sources[0x02]	7685	1			T6	1		T1	4		T3	2
valid_sources[0x03]	6548	1			T3	2		T25	1		T29	3
valid_sources[0x04]	9711	1			T3	3		T29	2		T9	7
valid_sources[0x05]	7161	1			T6	1		T1	1		T2	4
valid_sources[0x06]	8190	1			T3	1		T7	1		T8	1
valid_sources[0x07]	7450	1			T2	20		T3	1		T25	2
valid_sources[0x08]	6948	1			T3	1		T4	2		T7	1
valid_sources[0x09]	7803	1			T6	1		T3	1		T25	1
valid_sources[0x0a]	6801	1			T3	3		T25	2		T4	7
valid_sources[0x0b]	6920	1			T3	1		T25	3		T7	1
valid_sources[0x0c]	6528	1			T25	2		T26	17		T4	11
valid_sources[0x0d]	7696	1			T6	4		T1	1		T25	2
valid_sources[0x0e]	11576	1			T6	3		T25	1		T4	7
valid_sources[0x0f]	13401	1			T3	1		T26	6		T7	1
valid_sources[0x10]	6809	1			T3	1		T8	1		T29	1
valid_sources[0x11]	6899	1			T3	1		T25	1		T4	8
valid_sources[0x12]	12074	1			T6	2		T29	1		T9	5
valid_sources[0x13]	6614	1			T3	1		T25	1		T4	1
valid_sources[0x14]	9214	1			T3	2		T27	1		T8	1
valid_sources[0x15]	11392	1			T1	1		T4	15		T29	1
valid_sources[0x16]	15469	1			T6	2		T3	1		T4	2
valid_sources[0x17]	6847	1			T29	1		T9	4		T192	1
valid_sources[0x18]	9941	1			T25	3		T27	1		T29	3
valid_sources[0x19]	8421	1			T4	3		T8	1		T29	1
valid_sources[0x1a]	7048	1			T25	6		T4	7		T8	3
valid_sources[0x1b]	7133	1			T3	2		T25	3		T29	2
valid_sources[0x1c]	11841	1			T25	1		T29	1		T9	8
valid_sources[0x1d]	8289	1			T25	1		T8	1		T29	2
valid_sources[0x1e]	6950	1			T6	1		T3	1		T25	3
valid_sources[0x1f]	6782	1			T3	1		T25	1		T29	2
valid_sources[0x20]	19740	1			T3	2		T27	1		T8	2
valid_sources[0x21]	7029	1			T6	1		T3	1		T25	3
valid_sources[0x22]	7056	1			T6	1		T3	1		T25	3
valid_sources[0x23]	7077	1			T3	1		T25	2		T26	34
valid_sources[0x24]	7010	1			T1	3		T3	1		T25	5
valid_sources[0x25]	7083	1			T3	3		T29	1		T9	12
valid_sources[0x26]	6764	1			T3	1		T25	1		T29	1
valid_sources[0x27]	7922	1			T25	1		T27	4		T4	8
valid_sources[0x28]	6940	1			T6	2		T25	1		T4	4
valid_sources[0x29]	6910	1			T1	2		T3	2		T8	1
valid_sources[0x2a]	8538	1			T25	1		T4	5		T8	1
valid_sources[0x2b]	6636	1			T25	2		T29	1		T9	4
valid_sources[0x2c]	7844	1			T25	2		T4	9		T29	1
valid_sources[0x2d]	6933	1			T3	1		T25	2		T29	1
valid_sources[0x2e]	6819	1			T4	19		T29	1		T9	11
valid_sources[0x2f]	10520	1			T3	1		T25	1		T8	2
valid_sources[0x30]	10676	1			T1	1		T3	2		T25	2
valid_sources[0x31]	6741	1			T2	10		T25	1		T4	6
valid_sources[0x32]	6954	1			T3	1		T25	1		T4	18
valid_sources[0x33]	14413	1			T3	1		T7	2		T29	2
valid_sources[0x34]	6719	1			T3	1		T25	1		T4	9
valid_sources[0x35]	7299	1			T3	2		T7	1		T29	2
valid_sources[0x36]	7111	1			T3	2		T4	8		T29	4
valid_sources[0x37]	7258	1			T2	10		T3	2		T4	6
valid_sources[0x38]	21201	1			T7	1		T8	1		T29	2
valid_sources[0x39]	6603	1			T3	1		T25	2		T29	2
valid_sources[0x3a]	15940	1			T3	2		T25	1		T4	16
valid_sources[0x3b]	7675	1			T3	1		T4	1		T29	1
valid_sources[0x3c]	8989	1			T3	2		T7	1		T29	1
valid_sources[0x3d]	7041	1			T25	5		T7	3		T8	4
valid_sources[0x3e]	7207	1			T1	1		T3	1		T4	9
valid_sources[0x3f]	8489	1			T1	1		T3	1		T25	1
valid_sources[0x40]	6343	1			T3	1		T7	1		T8	2
valid_sources[0x41]	6807	1			T3	1		T25	1		T27	2
valid_sources[0x42]	16633	1			T6	1		T1	2		T3	1
valid_sources[0x43]	9327	1			T6	1		T25	2		T4	6
valid_sources[0x44]	8421	1			T25	2		T27	1		T4	1
valid_sources[0x45]	9483	1			T1	1		T3	1		T4	5
valid_sources[0x46]	6813	1			T3	5		T25	1		T4	4
valid_sources[0x47]	6607	1			T3	3		T25	2		T29	1
valid_sources[0x48]	7354	1			T2	4		T25	1		T8	3
valid_sources[0x49]	8379	1			T3	1		T25	3		T8	2
valid_sources[0x4a]	6613	1			T1	1		T25	3		T27	1
valid_sources[0x4b]	7423	1			T3	3		T25	1		T29	1
valid_sources[0x4c]	6628	1			T25	2		T4	11		T9	3
valid_sources[0x4d]	6743	1			T6	1		T2	6		T3	1
valid_sources[0x4e]	11333	1			T6	2		T3	4		T29	1
valid_sources[0x4f]	7076	1			T3	2		T25	1		T29	1
valid_sources[0x50]	6762	1			T27	1		T4	3		T9	8
valid_sources[0x51]	10968	1			T3	1		T4	6		T8	1
valid_sources[0x52]	7107	1			T1	1		T2	12		T25	1
valid_sources[0x53]	7270	1			T6	1		T3	2		T25	1
valid_sources[0x54]	8550	1			T3	3		T25	3		T27	2
valid_sources[0x55]	8058	1			T3	2		T25	4		T8	2
valid_sources[0x56]	7267	1			T6	1		T3	2		T4	3
valid_sources[0x57]	6446	1			T2	1		T25	2		T7	2
valid_sources[0x58]	7555	1			T25	1		T29	3		T9	9
valid_sources[0x59]	11117	1			T6	1		T3	1		T4	18
valid_sources[0x5a]	6489	1			T3	3		T25	6		T4	14
valid_sources[0x5b]	7403	1			T3	1		T4	9		T9	4
valid_sources[0x5c]	13334	1			T3	3		T25	1		T4	5
valid_sources[0x5d]	7444	1			T1	1		T3	1		T25	1
valid_sources[0x5e]	8136	1			T25	3		T9	5		T10	5
valid_sources[0x5f]	6769	1			T3	1		T4	8		T7	1
valid_sources[0x60]	13182	1			T3	1		T25	1		T27	2
valid_sources[0x61]	12314	1			T25	1		T4	1		T29	2
valid_sources[0x62]	8155	1			T3	1		T8	1		T29	3
valid_sources[0x63]	6792	1			T25	2		T29	4		T9	13
valid_sources[0x64]	7773	1			T25	2		T29	1		T9	6
valid_sources[0x65]	11233	1			T25	1		T4	2		T7	1
valid_sources[0x66]	6834	1			T3	1		T4	11		T7	1
valid_sources[0x67]	6699	1			T1	1		T3	2		T8	2
valid_sources[0x68]	7545	1			T6	2		T3	1		T27	2
valid_sources[0x69]	6804	1			T3	1		T25	1		T4	6
valid_sources[0x6a]	8190	1			T3	2		T25	1		T7	1
valid_sources[0x6b]	11985	1			T1	1		T8	5		T29	1
valid_sources[0x6c]	11909	1			T6	1		T3	3		T27	2
valid_sources[0x6d]	9766	1			T25	3		T29	1		T9	1
valid_sources[0x6e]	7367	1			T6	1		T25	1		T7	2
valid_sources[0x6f]	9464	1			T25	3		T8	2		T29	3
valid_sources[0x70]	6898	1			T6	1		T2	1		T8	1
valid_sources[0x71]	15011	1			T3	1		T25	1		T27	1
valid_sources[0x72]	6784	1			T3	1		T4	2		T29	3
valid_sources[0x73]	7187	1			T2	2		T3	2		T25	3
valid_sources[0x74]	8055	1			T3	2		T25	2		T4	2
valid_sources[0x75]	6835	1			T3	3		T25	1		T8	2
valid_sources[0x76]	6752	1			T3	1		T25	2		T29	2
valid_sources[0x77]	16669	1			T6	1		T4	11		T7	3
valid_sources[0x78]	7665	1			T3	2		T25	2		T29	1
valid_sources[0x79]	7423	1			T3	1		T25	3		T9	6
valid_sources[0x7a]	7882	1			T6	1		T25	2		T27	3
valid_sources[0x7b]	19756	1			T3	1		T8	2		T9	9
valid_sources[0x7c]	9998	1			T6	2		T3	2		T25	1
valid_sources[0x7d]	6832	1			T3	1		T26	31		T4	15
valid_sources[0x7e]	13730	1			T1	1		T25	2		T29	1
valid_sources[0x7f]	7142	1			T2	8		T25	1		T4	1
valid_sources[0x80]	6898	1			T4	11		T7	2		T29	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1002606

1

T5

3

T6

17

T1

13

values[0x0]

all_enables

biggest_size

70217

1

T5

1

T6

15

T1

14

values[0x1]

all_enables

biggest_size

50450

1

T5

2

T6

13

T1

12