Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28118	1			T2	58		T3	142		T4	654
auto[PWRUP]	99	1			T22	3		T90	1		T194	2
auto[ONEST_0]	79	1			T22	2		T90	1		T194	1
auto[ONEST_021]	19	1			T179	2		T195	1		T113	1
auto[ONEST_1]	73	1			T194	1		T195	1		T113	2
auto[ONEST_DONE]	3	1			T38	1		T196	1		T197	1
auto[LP_0]	123	1			T22	3		T38	1		T90	3
auto[LP_021]	26	1			T38	1		T90	1		T113	1
auto[LP_1]	99	1			T22	4		T90	2		T194	2
auto[LP_EVAL]	82	1			T194	1		T39	2		T179	1
auto[LP_SLP]	473	1			T22	7		T38	4		T90	9
auto[LP_PWRUP]	24	1			T38	1		T111	1		T198	1
auto[NP_0]	152	1			T22	1		T90	3		T194	2
auto[NP_021]	32	1			T22	1		T111	2		T170	2
auto[NP_1]	135	1			T22	2		T38	1		T90	3
auto[NP_EVAL]	35	1			T194	1		T195	2		T170	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

4

1

T22

1

T111

1

T199

1

min

27617

1

T2

58

T3

142

T4

654

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27631	1			T2	58		T3	142		T4	654
pow[0x1]	8	1			T200	1		T201	1		T202	1
pow[0x2]	10	1			T90	1		T170	1		T203	1
pow[0x3]	38	1			T38	1		T113	4		T204	1
pow[0x4]	58	1			T194	1		T39	1		T195	2
pow[0x5]	122	1			T38	2		T90	2		T194	1
pow[0x6]	237	1			T22	6		T38	1		T90	3
pow[0x7]	493	1			T22	7		T38	4		T90	3

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

199

1

T38

2

T90

1

T194

2

min

27162

1

T2

58

T3

142

T4

654

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27162	1			T2	58		T3	142		T4	654
pow[0x6]	1	1			T205	1		-	-		-	-
pow[0x7]	2	1			T206	1		T207	1		-	-
pow[0x8]	9	1			T22	1		T111	1		T208	1
pow[0x9]	10	1			T209	1		T210	1		T206	1
pow[0xa]	14	1			T179	1		T113	1		T210	1
pow[0xb]	30	1			T22	1		T39	2		T195	1
pow[0xc]	60	1			T22	2		T38	2		T194	1
pow[0xd]	143	1			T22	1		T38	1		T90	4
pow[0xe]	275	1			T22	5		T38	2		T90	6
pow[0xf]	561	1			T22	7		T38	3		T90	9