Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2185	1			T6	1		T1	1		T26	2
auto[PWRUP]	136	1			T45	1		T22	2		T86	1
auto[ONEST_0]	75	1			T22	2		T86	1		T90	1
auto[ONEST_021]	22	1			T111	1		T113	1		T357	1
auto[ONEST_1]	99	1			T86	1		T38	1		T90	1
auto[ONEST_DONE]	4	1			T357	1		T210	1		T300	1
auto[LP_0]	115	1			T22	2		T90	1		T194	1
auto[LP_021]	23	1			T38	1		T170	1		T203	1
auto[LP_1]	135	1			T22	1		T90	3		T194	2
auto[LP_EVAL]	45	1			T38	1		T113	3		T170	2
auto[LP_SLP]	531	1			T22	5		T38	4		T90	7
auto[LP_PWRUP]	37	1			T22	1		T217	1		T111	1
auto[NP_0]	238	1			T22	4		T38	1		T90	1
auto[NP_021]	46	1			T194	1		T39	1		T195	1
auto[NP_1]	232	1			T22	3		T86	5		T90	2
auto[NP_EVAL]	36	1			T22	1		T213	1		T181	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

12

1

T22

1

T358

1

T359

1

min

1887

1

T6

1

T1

1

T26

2

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1898	1			T6	1		T1	1		T26	2
pow[0x1]	4	1			T154	1		T360	1		T300	1
pow[0x2]	21	1			T194	1		T357	1		T359	2
pow[0x3]	40	1			T194	2		T179	1		T195	1
pow[0x4]	59	1			T22	1		T38	1		T195	1
pow[0x5]	114	1			T22	3		T38	2		T90	2
pow[0x6]	282	1			T22	5		T38	1		T90	3
pow[0x7]	495	1			T22	4		T38	4		T90	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

216

1

T22

1

T38

5

T90

8

min

1303

1

T6

1

T1

1

T26

2

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1306	1			T6	1		T1	1		T26	2
pow[0x1]	12	1			T110	2		T255	5		T284	1
pow[0x2]	14	1			T213	2		T39	2		T181	2
pow[0x3]	64	1			T86	5		T214	2		T226	8
pow[0x4]	45	1			T217	1		T215	1		T106	2
pow[0x7]	4	1			T358	1		T361	1		T344	1
pow[0x8]	5	1			T362	1		T363	1		T196	1
pow[0x9]	5	1			T38	1		T358	1		T205	1
pow[0xa]	19	1			T38	1		T198	1		T364	1
pow[0xb]	46	1			T39	1		T113	2		T203	1
pow[0xc]	85	1			T39	2		T195	1		T111	1
pow[0xd]	152	1			T22	1		T38	2		T90	4
pow[0xe]	286	1			T22	7		T38	3		T90	7
pow[0xf]	545	1			T22	8		T38	2		T90	5