Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.70	99.67	98.31		100.00	95.54	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	97.92	100.00	96.84		100.00	92.77	100.00
u_adc_ctrl_intr	95.01	98.67	84.62			96.77	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		61	61	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	199	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	8	8
59	8	8
68	1	1
69	1	1
70	1	1
71	1	1
79	1	1
82	1	1
83	1	1
84	1	1
85	1	1
100	8	8
103	8	8
113	8	8
117	8	8
133	1	1
134	1	1
138	1	1
199	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	284	284	100.00
Logical	284	284	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T13,T16,T37

 LINE       79
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T12,T13,T14

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T14,T20,T21
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T20,T21
0	1	Covered	T14,T20,T21
1	0	Covered	T14,T20,T21

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T18,T20,T21
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T20,T21
0	1	Covered	T18,T21,T22
1	0	Covered	T18,T20,T21

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T12,T14,T15
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T14,T15

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T12,T15,T18
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T17
1	0	Covered	T13,T14,T15
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T15,T18
0	1	Covered	T12,T15,T18
1	0	Covered	T12,T15,T18

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T12,T14,T15
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T17
1	0	Covered	T13,T14,T15
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T14,T15

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T12,T14,T20
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T17
1	0	Covered	T13,T14,T15
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T20
0	1	Covered	T12,T14,T20
1	0	Covered	T12,T14,T20

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T12,T14,T15
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T14,T15

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T14,T17,T20
1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T20
0	1	Covered	T14,T17,T20
1	0	Covered	T14,T17,T20

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T12,T14,T18
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T15,T17
1	0	Covered	T12,T13,T15
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T18
0	1	Covered	T12,T14,T18
1	0	Covered	T12,T14,T18

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T18,T20,T21
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T20,T21
0	1	Covered	T18,T20,T21
1	0	Covered	T18,T20,T21

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T12,T14,T15
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T14,T15

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T12,T15,T18
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T17
1	0	Covered	T13,T14,T15
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T15,T18
0	1	Covered	T12,T15,T18
1	0	Covered	T12,T15,T18

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T12,T14,T15
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T17
1	0	Covered	T13,T14,T15
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T14,T15

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T12,T14,T20
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T17
1	0	Covered	T13,T14,T15
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T20
0	1	Covered	T12,T14,T20
1	0	Covered	T12,T14,T20

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T12,T14,T15
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T14,T15

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T14,T17,T20
1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T20
0	1	Covered	T14,T17,T20
1	0	Covered	T14,T17,T20

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T12,T14,T17
1	1	0	Covered	T14,T17,T18
1	1	1	Covered	T12,T14,T17

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T17
0	1	Covered	T12,T14,T17
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T17
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T14,T17

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T18
0	1	Covered	T14,T17,T18
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T18
1	0	Covered	T12,T13,T14
1	1	Covered	T14,T17,T18

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T12,T14,T15
1	1	0	Covered	T12,T14,T15
1	1	1	Covered	T12,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T14,T17,T18
1	1	0	Covered	T14,T17,T18
1	1	1	Covered	T14,T17,T18

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T18
0	1	Covered	T14,T17,T18
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T18
1	0	Covered	T12,T13,T14
1	1	Covered	T14,T17,T18

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T18
0	1	Covered	T14,T17,T18
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T18
1	0	Covered	T12,T13,T14
1	1	Covered	T14,T17,T18

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T12,T14,T17
1	1	0	Covered	T12,T14,T17
1	1	1	Covered	T12,T14,T17

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T17
0	1	Covered	T12,T14,T17
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T17
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T14,T17

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T17
0	1	Covered	T12,T14,T17
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T17
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T14,T17

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T12,T14,T15
1	1	0	Covered	T12,T14,T15
1	1	1	Covered	T12,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T12,T14,T15
1	1	0	Covered	T12,T14,T15
1	1	1	Covered	T12,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T12,T14,T15
1	1	0	Covered	T12,T14,T15
1	1	1	Covered	T12,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T14,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Covered	T12,T14,T15
1	1	0	Covered	T12,T14,T15
1	1	1	Covered	T12,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T14,T15

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14

 LINE       113
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T17
1	0	Covered	T12,T14,T15
1	1	Covered	T12,T14,T17

 LINE       117
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T14,T15
1	1	Covered	T12,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T18
1	0	Covered	T12,T14,T15
1	1	Covered	T14,T17,T18

 LINE       117
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T17
1	0	Covered	T12,T14,T15
1	1	Covered	T12,T14,T17

 LINE       117
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T14,T15
1	1	Covered	T12,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T14,T15
1	1	Covered	T12,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T14,T15
1	1	Covered	T12,T14,T15

 LINE       117
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T14,T15
1	1	Covered	T12,T14,T15

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	79	3	3	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	79	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T13,T16,T37
0	1	Covered	T12,T13,T14
0	0	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T14,T20,T21

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T14,T18

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T18,T20,T21

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T18,T20,T21

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T14,T15

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T14,T15

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T15,T18

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T15,T18

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T14,T15

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T14,T15

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T14,T20

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T14,T20

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T14,T15

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T14,T15

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T14,T17,T20

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T14,T17,T20

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	31464214	31157381	0	0
gen_filter_match[0].MatchCheck00_A	31464214	10017016	0	0
gen_filter_match[0].MatchCheck01_A	31464214	2475715	0	0
gen_filter_match[0].MatchCheck10_A	31464214	2827915	0	0
gen_filter_match[0].MatchCheck11_A	31464214	15836735	0	0
gen_filter_match[1].MatchCheck00_A	31464214	11180214	0	0
gen_filter_match[1].MatchCheck01_A	31464214	997304	0	0
gen_filter_match[1].MatchCheck10_A	31464214	1426057	0	0
gen_filter_match[1].MatchCheck11_A	31464214	17553806	0	0
gen_filter_match[2].MatchCheck00_A	31464214	11135632	0	0
gen_filter_match[2].MatchCheck01_A	31464214	657076	0	0
gen_filter_match[2].MatchCheck10_A	31464214	661816	0	0
gen_filter_match[2].MatchCheck11_A	31464214	18702857	0	0
gen_filter_match[3].MatchCheck00_A	31464214	11688216	0	0
gen_filter_match[3].MatchCheck01_A	31464214	459853	0	0
gen_filter_match[3].MatchCheck10_A	31464214	331243	0	0
gen_filter_match[3].MatchCheck11_A	31464214	18678069	0	0
gen_filter_match[4].MatchCheck00_A	31464214	12323009	0	0
gen_filter_match[4].MatchCheck01_A	31464214	33368	0	0
gen_filter_match[4].MatchCheck10_A	31464214	36804	0	0
gen_filter_match[4].MatchCheck11_A	31464214	18764200	0	0
gen_filter_match[5].MatchCheck00_A	31464214	11829380	0	0
gen_filter_match[5].MatchCheck01_A	31464214	100890	0	0
gen_filter_match[5].MatchCheck10_A	31464214	33674	0	0
gen_filter_match[5].MatchCheck11_A	31464214	19193437	0	0
gen_filter_match[6].MatchCheck00_A	31464214	13000748	0	0
gen_filter_match[6].MatchCheck01_A	31464214	33128	0	0
gen_filter_match[6].MatchCheck10_A	31464214	97216	0	0
gen_filter_match[6].MatchCheck11_A	31464214	18026289	0	0
gen_filter_match[7].MatchCheck00_A	31464214	11682925	0	0
gen_filter_match[7].MatchCheck01_A	31464214	162995	0	0
gen_filter_match[7].MatchCheck10_A	31464214	134480	0	0
gen_filter_match[7].MatchCheck11_A	31464214	19176981	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	31157381	0	0
T12	64707	64624	0	0
T13	1010	955	0	0
T14	101811	101735	0	0
T15	65755	65680	0	0
T16	1192	1109	0	0
T17	65664	65594	0	0
T18	67295	67237	0	0
T19	6695	6635	0	0
T20	32165	32104	0	0
T21	69563	69229	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	10017016	0	0
T12	64707	32278	0	0
T13	1010	955	0	0
T14	101811	33443	0	0
T15	65755	65680	0	0
T16	1192	1109	0	0
T17	65664	4	0	0
T18	67295	33641	0	0
T19	6695	6635	0	0
T20	32165	3	0	0
T21	69563	37739	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	2475715	0	0
T20	32165	32101	0	0
T21	69563	0	0	0
T22	91227	0	0	0
T23	66707	0	0	0
T24	65274	32884	0	0
T37	1127	0	0	0
T39	0	21128	0	0
T82	132729	33711	0	0
T85	67068	0	0	0
T87	963	0	0	0
T89	0	32852	0	0
T90	0	32749	0	0
T91	0	33193	0	0
T92	0	33030	0	0
T93	0	32215	0	0
T94	0	32136	0	0
T95	65077	0	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	2827915	0	0
T12	64707	32346	0	0
T13	1010	0	0	0
T14	101811	32668	0	0
T15	65755	0	0	0
T16	1192	0	0	0
T17	65664	0	0	0
T18	67295	0	0	0
T19	6695	0	0	0
T20	32165	0	0	0
T21	69563	31490	0	0
T33	0	32440	0	0
T89	0	34041	0	0
T90	0	33022	0	0
T96	0	33212	0	0
T97	0	32373	0	0
T98	0	33115	0	0
T99	0	1	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	15836735	0	0
T14	101811	35624	0	0
T15	65755	0	0	0
T16	1192	0	0	0
T17	65664	65590	0	0
T18	67295	33596	0	0
T19	6695	0	0	0
T20	32165	0	0	0
T21	69563	0	0	0
T22	91227	201	0	0
T23	0	33442	0	0
T33	0	31633	0	0
T34	0	33198	0	0
T37	1127	0	0	0
T82	0	65854	0	0
T85	0	32740	0	0
T86	0	10532	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	11180214	0	0
T12	64707	3	0	0
T13	1010	955	0	0
T14	101811	68296	0	0
T15	65755	3	0	0
T16	1192	1109	0	0
T17	65664	4	0	0
T18	67295	4	0	0
T19	6695	6635	0	0
T20	32165	3	0	0
T21	69563	36752	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	997304	0	0
T47	1614	0	0	0
T52	717	0	0	0
T85	67068	32879	0	0
T95	65077	0	0	0
T100	97292	32555	0	0
T101	0	33828	0	0
T102	0	32820	0	0
T103	0	32642	0	0
T104	0	33479	0	0
T105	0	32118	0	0
T106	0	4880	0	0
T107	0	32917	0	0
T108	0	32636	0	0
T109	1067	0	0	0
T110	15650	0	0	0
T111	59041	0	0	0
T112	99708	0	0	0
T113	20833	0	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	1426057	0	0
T15	65755	32219	0	0
T16	1192	0	0	0
T17	65664	0	0	0
T18	67295	0	0	0
T19	6695	0	0	0
T20	32165	0	0	0
T21	69563	0	0	0
T22	91227	0	0	0
T23	0	33175	0	0
T37	1127	0	0	0
T87	963	0	0	0
T90	0	5	0	0
T99	0	1	0	0
T114	0	2	0	0
T115	0	2	0	0
T116	0	33454	0	0
T117	0	3	0	0
T118	0	32340	0	0
T119	0	32675	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	17553806	0	0
T12	64707	64621	0	0
T13	1010	0	0	0
T14	101811	33439	0	0
T15	65755	33458	0	0
T16	1192	0	0	0
T17	65664	65590	0	0
T18	67295	67233	0	0
T19	6695	0	0	0
T20	32165	32101	0	0
T21	69563	32477	0	0
T22	0	70245	0	0
T23	0	33442	0	0
T82	0	31797	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	11135632	0	0
T12	64707	64624	0	0
T13	1010	955	0	0
T14	101811	32672	0	0
T15	65755	65680	0	0
T16	1192	1109	0	0
T17	65664	4	0	0
T18	67295	4	0	0
T19	6695	6635	0	0
T20	32165	3	0	0
T21	69563	5262	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	657076	0	0
T33	96460	31633	0	0
T34	99916	0	0	0
T42	95	0	0	0
T47	1614	0	0	0
T52	717	0	0	0
T82	132729	31797	0	0
T85	67068	0	0	0
T95	65077	0	0	0
T96	33268	0	0	0
T97	32454	0	0	0
T103	0	31855	0	0
T115	0	2	0	0
T116	0	33697	0	0
T118	0	32342	0	0
T120	0	1	0	0
T121	0	32777	0	0
T122	0	32819	0	0
T123	0	32287	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	661816	0	0
T38	15155	0	0	0
T43	66	0	0	0
T90	97275	2	0	0
T99	65499	1	0	0
T114	0	2	0	0
T115	0	4	0	0
T117	0	3	0	0
T124	0	65040	0	0
T125	0	1	0	0
T126	0	33868	0	0
T127	0	1	0	0
T128	0	33002	0	0
T129	1147	0	0	0
T130	33366	0	0	0
T131	65966	0	0	0
T132	97424	0	0	0
T133	6747	0	0	0
T134	34098	0	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	18702857	0	0
T14	101811	69063	0	0
T15	65755	0	0	0
T16	1192	0	0	0
T17	65664	65590	0	0
T18	67295	67233	0	0
T19	6695	0	0	0
T20	32165	32101	0	0
T21	69563	63967	0	0
T22	91227	37409	0	0
T23	0	33175	0	0
T24	0	65190	0	0
T37	1127	0	0	0
T82	0	99565	0	0
T96	0	33212	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	11688216	0	0
T12	64707	32278	0	0
T13	1010	955	0	0
T14	101811	32672	0	0
T15	65755	65680	0	0
T16	1192	1109	0	0
T17	65664	4	0	0
T18	67295	33641	0	0
T19	6695	6635	0	0
T20	32165	3	0	0
T21	69563	5262	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	459853	0	0
T34	99916	33680	0	0
T86	13769	0	0	0
T88	1153	0	0	0
T98	33169	0	0	0
T99	65499	0	0	0
T100	0	32006	0	0
T107	0	33462	0	0
T115	0	2	0	0
T129	1147	0	0	0
T132	0	1	0	0
T134	0	34013	0	0
T135	0	32399	0	0
T136	0	32569	0	0
T137	0	1	0	0
T138	0	32681	0	0
T139	8393	0	0	0
T140	7299	0	0	0
T141	33066	0	0	0
T142	31723	0	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	331243	0	0
T38	15155	0	0	0
T43	66	0	0	0
T99	65499	1	0	0
T103	0	32354	0	0
T110	0	1	0	0
T114	65982	2	0	0
T115	0	1	0	0
T120	0	2	0	0
T125	0	1	0	0
T129	1147	0	0	0
T130	33366	0	0	0
T131	65966	0	0	0
T132	97424	0	0	0
T133	6747	0	0	0
T135	99143	0	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	33474	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	18678069	0	0
T12	64707	32346	0	0
T13	1010	0	0	0
T14	101811	69063	0	0
T15	65755	0	0	0
T16	1192	0	0	0
T17	65664	65590	0	0
T18	67295	33596	0	0
T19	6695	0	0	0
T20	32165	32101	0	0
T21	69563	63967	0	0
T23	0	33442	0	0
T33	0	63958	0	0
T82	0	33711	0	0
T85	0	32740	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	12323009	0	0
T12	64707	3	0	0
T13	1010	955	0	0
T14	101811	35628	0	0
T15	65755	3	0	0
T16	1192	1109	0	0
T17	65664	4	0	0
T18	67295	33600	0	0
T19	6695	6635	0	0
T20	32165	32104	0	0
T21	69563	36752	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	33368	0	0
T107	98774	1	0	0
T146	98951	2	0	0
T147	66739	1	0	0
T148	0	1	0	0
T149	0	2	0	0
T150	0	33357	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	15671	0	0	0
T155	61	0	0	0
T156	33230	0	0	0
T157	50592	0	0	0
T158	9282	0	0	0
T159	14147	0	0	0
T160	98925	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	36804	0	0
T38	15155	0	0	0
T43	66	0	0	0
T90	97275	3	0	0
T99	65499	1	0	0
T103	0	1	0	0
T110	0	3	0	0
T114	0	1	0	0
T115	0	2	0	0
T117	0	2	0	0
T120	0	1	0	0
T129	1147	0	0	0
T130	33366	0	0	0
T131	65966	0	0	0
T132	97424	0	0	0
T133	6747	0	0	0
T134	34098	0	0	0
T143	0	1	0	0
T161	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	18764200	0	0
T12	64707	64621	0	0
T13	1010	0	0	0
T14	101811	66107	0	0
T15	65755	65677	0	0
T16	1192	0	0	0
T17	65664	65590	0	0
T18	67295	33637	0	0
T19	6695	0	0	0
T20	32165	0	0	0
T21	69563	32477	0	0
T22	0	37409	0	0
T23	0	66617	0	0
T82	0	97651	0	0
T85	0	32740	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	11829380	0	0
T12	64707	32349	0	0
T13	1010	955	0	0
T14	101811	68296	0	0
T15	65755	33461	0	0
T16	1192	1109	0	0
T17	65664	4	0	0
T18	67295	33641	0	0
T19	6695	6635	0	0
T20	32165	3	0	0
T21	69563	69229	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	100890	0	0
T103	96925	2	0	0
T122	32921	0	0	0
T137	0	1	0	0
T144	65924	1	0	0
T145	100161	0	0	0
T146	0	2	0	0
T148	0	1	0	0
T162	0	33291	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	34519	0	0
T166	0	1	0	0
T167	32871	0	0	0
T168	64326	0	0	0
T169	33000	0	0	0
T170	13976	0	0	0
T171	99474	0	0	0
T172	90	0	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	33674	0	0
T38	15155	0	0	0
T43	66	0	0	0
T47	1614	0	0	0
T52	717	0	0	0
T95	65077	1	0	0
T99	65499	2	0	0
T103	0	1	0	0
T114	0	1	0	0
T115	0	2	0	0
T117	0	3	0	0
T120	0	1	0	0
T127	0	1	0	0
T129	1147	0	0	0
T130	33366	0	0	0
T131	65966	0	0	0
T132	97424	0	0	0
T143	0	1	0	0
T161	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	19193437	0	0
T12	64707	32275	0	0
T13	1010	0	0	0
T14	101811	33439	0	0
T15	65755	32219	0	0
T16	1192	0	0	0
T17	65664	65590	0	0
T18	67295	33596	0	0
T19	6695	0	0	0
T20	32165	32101	0	0
T21	69563	0	0	0
T22	0	37409	0	0
T23	0	33175	0	0
T82	0	33124	0	0
T85	0	32879	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	13000748	0	0
T12	64707	32278	0	0
T13	1010	955	0	0
T14	101811	69067	0	0
T15	65755	33461	0	0
T16	1192	1109	0	0
T17	65664	4	0	0
T18	67295	4	0	0
T19	6695	6635	0	0
T20	32165	32104	0	0
T21	69563	69229	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	33128	0	0
T91	65944	0	0	0
T111	0	33121	0	0
T115	97273	3	0	0
T132	97424	1	0	0
T133	6747	0	0	0
T163	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	66513	0	0	0
T176	8872	0	0	0
T177	5845	0	0	0
T178	1168	0	0	0
T179	16341	0	0	0
T180	72	0	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	97216	0	0
T22	91227	1	0	0
T23	66707	0	0	0
T24	65274	0	0	0
T47	1614	0	0	0
T52	717	0	0	0
T82	132729	0	0	0
T85	67068	0	0	0
T87	963	0	0	0
T90	0	2	0	0
T95	65077	1	0	0
T99	65499	1	0	0
T110	0	1	0	0
T114	0	2	0	0
T115	0	2	0	0
T132	0	2	0	0
T143	0	1	0	0
T181	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	18026289	0	0
T12	64707	32346	0	0
T13	1010	0	0	0
T14	101811	32668	0	0
T15	65755	32219	0	0
T16	1192	0	0	0
T17	65664	65590	0	0
T18	67295	67233	0	0
T19	6695	0	0	0
T20	32165	0	0	0
T21	69563	0	0	0
T22	0	70244	0	0
T23	0	33442	0	0
T24	0	32884	0	0
T82	0	33711	0	0
T85	0	32740	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	11682925	0	0
T12	64707	32349	0	0
T13	1010	955	0	0
T14	101811	68296	0	0
T15	65755	3	0	0
T16	1192	1109	0	0
T17	65664	4	0	0
T18	67295	67237	0	0
T19	6695	6635	0	0
T20	32165	32104	0	0
T21	69563	5262	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	162995	0	0
T91	65944	0	0	0
T103	0	1	0	0
T107	0	1	0	0
T115	97273	2	0	0
T120	0	1	0	0
T121	0	32779	0	0
T127	0	32042	0	0
T132	97424	1	0	0
T133	6747	0	0	0
T144	0	1	0	0
T171	0	1	0	0
T175	66513	0	0	0
T176	8872	0	0	0
T177	5845	0	0	0
T178	1168	0	0	0
T179	16341	0	0	0
T180	72	0	0	0
T182	0	33086	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	134480	0	0
T38	15155	0	0	0
T43	66	0	0	0
T47	1614	0	0	0
T52	717	0	0	0
T95	65077	1	0	0
T99	65499	1	0	0
T110	0	2	0	0
T114	0	2	0	0
T115	0	2	0	0
T117	0	2	0	0
T129	1147	0	0	0
T130	33366	0	0	0
T131	65966	0	0	0
T132	97424	2	0	0
T143	0	1	0	0
T181	0	1	0	0
T183	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31464214	19176981	0	0
T12	64707	32275	0	0
T13	1010	0	0	0
T14	101811	33439	0	0
T15	65755	65677	0	0
T16	1192	0	0	0
T17	65664	65590	0	0
T18	67295	0	0	0
T19	6695	0	0	0
T20	32165	0	0	0
T21	69563	63967	0	0
T22	0	32836	0	0
T23	0	66617	0	0
T24	0	32306	0	0
T82	0	65854	0	0
T95	0	65010	0	0