Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	25	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	25	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	6684	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1711	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1429	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1676	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1565	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1758	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1629	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1588	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1760	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1624	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1679	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1641	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1564	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1582	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1668	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1554	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1597	0	0
adc_en_ctl_rd_A	2147483647	1516	0	0
adc_fsm_rst_rd_A	2147483647	1214	0	0
adc_intr_ctl_rd_A	2147483647	1263	0	0
adc_lp_sample_ctl_rd_A	2147483647	1245	0	0
adc_pd_ctl_rd_A	2147483647	1416	0	0
adc_sample_ctl_rd_A	2147483647	1319	0	0
adc_wakeup_ctl_rd_A	2147483647	1256	0	0
intr_enable_rd_A	2147483647	1908	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6684	0	0
T4	46373	0	0	0
T7	19214	0	0	0
T8	4256	0	0	0
T9	843745	0	0	0
T25	14713	204	0	0
T26	54938	0	0	0
T27	29304	1	0	0
T28	36100	0	0	0
T29	35022	343	0	0
T36	13490	0	0	0
T60	0	1	0	0
T61	0	167	0	0
T62	0	24	0	0
T63	0	528	0	0
T64	0	255	0	0
T72	0	1	0	0
T184	0	1	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1711	0	0
T1	6740	4	0	0
T2	54891	0	0	0
T3	39700	0	0	0
T4	46373	0	0	0
T6	44062	3	0	0
T7	19214	24	0	0
T8	0	26	0	0
T25	14713	0	0	0
T26	54938	0	0	0
T27	29304	1	0	0
T28	36100	0	0	0
T29	0	4	0	0
T61	0	10	0	0
T71	0	6	0	0
T185	0	6	0	0
T186	0	59	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1429	0	0
T1	6740	7	0	0
T2	54891	0	0	0
T3	39700	0	0	0
T4	46373	0	0	0
T7	19214	0	0	0
T8	4256	10	0	0
T25	14713	0	0	0
T26	54938	0	0	0
T27	29304	4	0	0
T28	36100	0	0	0
T29	0	23	0	0
T61	0	11	0	0
T185	0	3	0	0
T186	0	20	0	0
T187	0	8	0	0
T188	0	51	0	0
T189	0	2	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1676	0	0
T1	6740	9	0	0
T2	54891	0	0	0
T3	39700	0	0	0
T4	46373	0	0	0
T6	44062	4	0	0
T7	19214	5	0	0
T8	0	20	0	0
T25	14713	0	0	0
T26	54938	0	0	0
T27	29304	6	0	0
T28	36100	0	0	0
T29	0	17	0	0
T61	0	2	0	0
T71	0	8	0	0
T185	0	6	0	0
T186	0	59	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1565	0	0
T1	6740	9	0	0
T2	54891	0	0	0
T3	39700	0	0	0
T4	46373	0	0	0
T6	44062	8	0	0
T7	19214	8	0	0
T8	0	6	0	0
T25	14713	0	0	0
T26	54938	0	0	0
T27	29304	8	0	0
T28	36100	0	0	0
T29	0	7	0	0
T61	0	17	0	0
T71	0	35	0	0
T185	0	3	0	0
T186	0	20	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1758	0	0
T1	6740	5	0	0
T2	54891	0	0	0
T3	39700	0	0	0
T4	46373	0	0	0
T6	44062	9	0	0
T7	19214	6	0	0
T8	0	2	0	0
T25	14713	0	0	0
T26	54938	0	0	0
T27	29304	1	0	0
T28	36100	0	0	0
T29	0	11	0	0
T61	0	12	0	0
T71	0	7	0	0
T185	0	4	0	0
T186	0	65	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1629	0	0
T1	6740	3	0	0
T2	54891	0	0	0
T3	39700	0	0	0
T4	46373	0	0	0
T6	44062	4	0	0
T7	19214	4	0	0
T8	0	20	0	0
T25	14713	0	0	0
T26	54938	0	0	0
T27	29304	3	0	0
T28	36100	0	0	0
T29	0	24	0	0
T61	0	18	0	0
T71	0	8	0	0
T185	0	4	0	0
T186	0	47	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1588	0	0
T1	6740	1	0	0
T2	54891	0	0	0
T3	39700	0	0	0
T4	46373	0	0	0
T6	44062	9	0	0
T7	19214	4	0	0
T8	0	18	0	0
T25	14713	0	0	0
T26	54938	0	0	0
T27	29304	3	0	0
T28	36100	0	0	0
T29	0	11	0	0
T61	0	3	0	0
T71	0	27	0	0
T185	0	1	0	0
T186	0	23	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1760	0	0
T1	6740	14	0	0
T2	54891	0	0	0
T3	39700	0	0	0
T4	46373	0	0	0
T6	44062	6	0	0
T7	19214	17	0	0
T8	0	10	0	0
T25	14713	0	0	0
T26	54938	0	0	0
T27	29304	2	0	0
T28	36100	0	0	0
T29	0	16	0	0
T61	0	16	0	0
T71	0	25	0	0
T186	0	17	0	0
T188	0	40	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1624	0	0
T1	6740	10	0	0
T2	54891	0	0	0
T3	39700	0	0	0
T4	46373	0	0	0
T6	44062	4	0	0
T7	19214	5	0	0
T8	0	18	0	0
T25	14713	0	0	0
T26	54938	0	0	0
T27	29304	1	0	0
T28	36100	0	0	0
T29	0	25	0	0
T61	0	13	0	0
T71	0	21	0	0
T186	0	36	0	0
T187	0	2	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1679	0	0
T4	46373	0	0	0
T7	19214	11	0	0
T8	4256	27	0	0
T9	843745	0	0	0
T10	34650	0	0	0
T11	127593	0	0	0
T27	29304	1	0	0
T28	36100	0	0	0
T29	35022	38	0	0
T36	13490	0	0	0
T71	0	15	0	0
T185	0	8	0	0
T186	0	35	0	0
T187	0	4	0	0
T188	0	79	0	0
T189	0	8	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1641	0	0
T1	6740	2	0	0
T2	54891	0	0	0
T3	39700	0	0	0
T4	46373	0	0	0
T7	19214	14	0	0
T8	4256	23	0	0
T25	14713	0	0	0
T26	54938	0	0	0
T27	29304	4	0	0
T28	36100	0	0	0
T29	0	17	0	0
T71	0	28	0	0
T185	0	6	0	0
T186	0	48	0	0
T187	0	9	0	0
T188	0	28	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1564	0	0
T4	46373	0	0	0
T7	19214	17	0	0
T8	4256	15	0	0
T9	843745	0	0	0
T10	34650	0	0	0
T11	127593	0	0	0
T27	29304	4	0	0
T28	36100	0	0	0
T29	35022	11	0	0
T36	13490	0	0	0
T61	0	5	0	0
T71	0	12	0	0
T185	0	6	0	0
T186	0	48	0	0
T187	0	2	0	0
T188	0	25	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1582	0	0
T1	6740	1	0	0
T2	54891	0	0	0
T3	39700	0	0	0
T4	46373	0	0	0
T7	19214	21	0	0
T8	4256	8	0	0
T25	14713	0	0	0
T26	54938	0	0	0
T27	29304	7	0	0
T28	36100	0	0	0
T29	0	28	0	0
T61	0	8	0	0
T71	0	41	0	0
T185	0	6	0	0
T186	0	21	0	0
T187	0	1	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1668	0	0
T1	6740	2	0	0
T2	54891	0	0	0
T3	39700	0	0	0
T4	46373	0	0	0
T6	44062	4	0	0
T7	19214	5	0	0
T8	0	19	0	0
T25	14713	0	0	0
T26	54938	0	0	0
T27	29304	2	0	0
T28	36100	0	0	0
T29	0	26	0	0
T61	0	7	0	0
T185	0	1	0	0
T186	0	19	0	0
T187	0	6	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1554	0	0
T1	6740	8	0	0
T2	54891	0	0	0
T3	39700	0	0	0
T4	46373	0	0	0
T6	44062	2	0	0
T7	19214	5	0	0
T8	0	29	0	0
T25	14713	0	0	0
T26	54938	0	0	0
T27	29304	5	0	0
T28	36100	0	0	0
T29	0	35	0	0
T61	0	9	0	0
T71	0	36	0	0
T185	0	7	0	0
T186	0	12	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1597	0	0
T1	6740	3	0	0
T2	54891	0	0	0
T3	39700	0	0	0
T4	46373	0	0	0
T6	44062	2	0	0
T7	19214	20	0	0
T8	0	21	0	0
T25	14713	0	0	0
T26	54938	0	0	0
T27	29304	5	0	0
T28	36100	0	0	0
T29	0	17	0	0
T61	0	4	0	0
T71	0	6	0	0
T186	0	41	0	0
T187	0	4	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1516	0	0
T1	6740	8	0	0
T2	54891	0	0	0
T3	39700	0	0	0
T4	46373	0	0	0
T6	44062	9	0	0
T7	19214	0	0	0
T8	0	3	0	0
T25	14713	0	0	0
T26	54938	0	0	0
T27	29304	9	0	0
T28	36100	0	0	0
T29	0	57	0	0
T61	0	13	0	0
T71	0	35	0	0
T185	0	6	0	0
T186	0	39	0	0
T187	0	10	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1214	0	0
T7	19214	4	0	0
T8	4256	0	0	0
T9	843745	0	0	0
T10	34650	0	0	0
T11	127593	0	0	0
T28	36100	0	0	0
T29	35022	36	0	0
T30	71413	0	0	0
T36	13490	0	0	0
T46	12300	0	0	0
T61	0	10	0	0
T185	0	2	0	0
T186	0	35	0	0
T187	0	1	0	0
T188	0	10	0	0
T189	0	10	0	0
T190	0	67	0	0
T191	0	6	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1263	0	0
T1	6740	8	0	0
T2	54891	0	0	0
T3	39700	0	0	0
T4	46373	0	0	0
T6	44062	2	0	0
T7	19214	0	0	0
T25	14713	0	0	0
T26	54938	0	0	0
T27	29304	0	0	0
T28	36100	0	0	0
T29	0	21	0	0
T61	0	1	0	0
T71	0	15	0	0
T185	0	5	0	0
T186	0	10	0	0
T187	0	6	0	0
T188	0	40	0	0
T189	0	10	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1245	0	0
T1	6740	3	0	0
T2	54891	0	0	0
T3	39700	0	0	0
T4	46373	0	0	0
T7	19214	0	0	0
T8	4256	10	0	0
T25	14713	0	0	0
T26	54938	0	0	0
T27	29304	8	0	0
T28	36100	0	0	0
T29	0	6	0	0
T71	0	25	0	0
T185	0	9	0	0
T186	0	32	0	0
T188	0	51	0	0
T189	0	2	0	0
T190	0	47	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1416	0	0
T1	6740	5	0	0
T2	54891	0	0	0
T3	39700	0	0	0
T4	46373	0	0	0
T7	19214	1	0	0
T8	4256	9	0	0
T25	14713	0	0	0
T26	54938	0	0	0
T27	29304	2	0	0
T28	36100	0	0	0
T29	0	15	0	0
T61	0	11	0	0
T71	0	1	0	0
T185	0	17	0	0
T186	0	21	0	0
T187	0	7	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1319	0	0
T1	6740	1	0	0
T2	54891	0	0	0
T3	39700	0	0	0
T4	46373	0	0	0
T6	44062	1	0	0
T7	19214	6	0	0
T8	0	12	0	0
T25	14713	0	0	0
T26	54938	0	0	0
T27	29304	4	0	0
T28	36100	0	0	0
T29	0	31	0	0
T61	0	14	0	0
T71	0	11	0	0
T185	0	5	0	0
T186	0	67	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1256	0	0
T1	6740	9	0	0
T2	54891	0	0	0
T3	39700	0	0	0
T4	46373	0	0	0
T6	44062	6	0	0
T7	19214	4	0	0
T8	0	9	0	0
T25	14713	0	0	0
T26	54938	0	0	0
T27	29304	3	0	0
T28	36100	0	0	0
T29	0	11	0	0
T61	0	12	0	0
T71	0	21	0	0
T185	0	1	0	0
T186	0	58	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1908	0	0
T1	6740	1	0	0
T2	54891	0	0	0
T3	39700	0	0	0
T4	46373	0	0	0
T5	11394	8	0	0
T6	44062	5	0	0
T7	19214	1	0	0
T8	0	14	0	0
T25	14713	0	0	0
T26	54938	0	0	0
T27	29304	3	0	0
T29	0	33	0	0
T61	0	2	0	0
T192	0	13	0	0
T193	0	18	0	0