ADC_CTRL Simulation Results

Sunday December 24 2023 20:02:26 UTC

GitHub Revision: `671f2b57e2`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 96716765175854174075659971574604807242747408006700796360560480210023744343645

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.670s	5.935ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.700s	921.003us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.980s	535.788us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.178m	30.299ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.260s	970.509us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.210s	600.844us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.980s	535.788us	20	20	100.00
		adc_ctrl_csr_aliasing	5.260s	970.509us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.788m	489.892ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.113m	501.933ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.974m	493.342ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.991m	496.019ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	19.599m	500.065ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	20.232m	498.993ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	18.675m	496.925ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	20.217m	486.610ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.360s	5.698ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.802m	44.372ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.767m	144.474ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	32.492m	837.679ms	44	50	88.00
V2	alert_test	adc_ctrl_alert_test	1.790s	484.536us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.780s	504.330us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.260s	508.017us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.260s	508.017us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.700s	921.003us	5	5	100.00
		adc_ctrl_csr_rw	1.980s	535.788us	20	20	100.00
		adc_ctrl_csr_aliasing	5.260s	970.509us	5	5	100.00
		adc_ctrl_same_csr_outstanding	14.980s	4.320ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.700s	921.003us	5	5	100.00
		adc_ctrl_csr_rw	1.980s	535.788us	20	20	100.00
		adc_ctrl_csr_aliasing	5.260s	970.509us	5	5	100.00
		adc_ctrl_same_csr_outstanding	14.980s	4.320ms	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	tl_intg_err	adc_ctrl_sec_cm	19.790s	8.064ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.390s	9.090ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.390s	9.090ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	12.360m	692.900ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			912	920	99.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.54	98.98	95.70	100.00	100.00	98.18	98.64	91.29

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 7 failures:

Test adc_ctrl_stress_all has 6 failures.

3.adc_ctrl_stress_all.89699536720021723621949041317677971212768136585215041788104369253103805643142
Line 391, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 504357766198 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 504357766198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.adc_ctrl_stress_all.113062831051881603032123463815679301962074407102722992535878043003335897253835
Line 361, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 329302852808 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 329302852808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

47.adc_ctrl_stress_all_with_rand_reset.28207363508521157984349255509207969815246168977210991711236084561434172798548
Line 373, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 287210193428 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 287210193428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (adc_ctrl_scoreboard.sv:115) [scoreboard] Check failed m_interrupt == (m_expected_intr_state & intr_en) (* [*] vs * [*]) has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 32.adc_ctrl_stress_all_with_rand_reset.5887456376090281344788332726223646062316072210687138918637727103769639964851
    Line 366, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14303884531 ps: (adc_ctrl_scoreboard.sv:115) [uvm_test_top.env.scoreboard] Check failed m_interrupt == (m_expected_intr_state & intr_en) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 14303884531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```