Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.70	99.67	98.31		100.00	95.54	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	97.92	100.00	96.84		100.00	92.77	100.00
u_adc_ctrl_intr	95.01	98.67	84.62			96.77	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		61	61	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	199	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	8	8
59	8	8
68	1	1
69	1	1
70	1	1
71	1	1
79	1	1
82	1	1
83	1	1
84	1	1
85	1	1
100	8	8
103	8	8
113	8	8
117	8	8
133	1	1
134	1	1
138	1	1
199	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	284	284	100.00
Logical	284	284	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T12,T14,T15

 LINE       79
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T16
1	Covered	T11,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T15,T16
1	0	Covered	T11,T12,T14
1	1	Covered	T11,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T16
0	1	Covered	T13,T14,T16
1	0	Covered	T13,T14,T16

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T11,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T16
1	Covered	T11,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T15
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T16
0	1	Covered	T13,T14,T16
1	0	Covered	T13,T14,T16

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T16
1	Covered	T11,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T16
0	1	Covered	T14,T16,T60
1	0	Covered	T13,T14,T16

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T11,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T15,T19
1	0	Covered	T11,T12,T14
1	1	Covered	T11,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T11,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T16

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T11,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T15,T16
1	0	Covered	T11,T12,T14
1	1	Covered	T11,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       100
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T11,T13,T15
1	Covered	T11,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T11,T12,T13

 LINE       100
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T15
0	1	Covered	T11,T13,T15
1	0	Covered	T11,T13,T15

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T11,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T15,T19
1	0	Covered	T11,T12,T14
1	1	Covered	T11,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T11,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T16
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T16
1	Covered	T11,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T15
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T16
0	1	Covered	T13,T14,T16
1	0	Covered	T13,T14,T16

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T16
1	Covered	T11,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T16
0	1	Covered	T13,T14,T16
1	0	Covered	T13,T14,T16

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T11,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T15,T19
1	0	Covered	T11,T12,T14
1	1	Covered	T11,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T11,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T16

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T11,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T15,T16
1	0	Covered	T11,T12,T14
1	1	Covered	T11,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T11,T13,T14
1	Covered	T11,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T12,T13,T14
1	1	Covered	T11,T12,T13

 LINE       103
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T14
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T11,T13,T14
1	1	0	Covered	T11,T13,T14
1	1	1	Covered	T11,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T14
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13

 LINE       113
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T14
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13

 LINE       113
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T11,T13,T14
1	1	0	Covered	T11,T13,T15
1	1	1	Covered	T11,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T14
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13

 LINE       113
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T15
0	1	Covered	T11,T13,T15
1	0	Covered	T11,T12,T13

 LINE       113
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T15
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T13,T15

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T11,T13,T14
1	1	0	Covered	T11,T13,T14
1	1	1	Covered	T11,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T14
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13

 LINE       113
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T14
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13

 LINE       113
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T11,T13,T19
1	1	0	Covered	T11,T13,T19
1	1	1	Covered	T11,T13,T19

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T19
0	1	Covered	T11,T13,T19
1	0	Covered	T11,T12,T13

 LINE       113
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T19
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T13,T19

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T19
0	1	Covered	T11,T13,T19
1	0	Covered	T11,T12,T13

 LINE       113
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T19
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T13,T19

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T11,T15,T19
1	1	0	Covered	T11,T15,T19
1	1	1	Covered	T11,T15,T19

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T15,T19
0	1	Covered	T11,T15,T19
1	0	Covered	T11,T12,T13

 LINE       113
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T15,T19
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T15,T19

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T15,T19
0	1	Covered	T11,T15,T19
1	0	Covered	T11,T12,T13

 LINE       113
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T15,T19
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T15,T19

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T11,T13,T14
1	1	0	Covered	T11,T13,T14
1	1	1	Covered	T11,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T14
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13

 LINE       113
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T14
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13

 LINE       113
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T11,T13,T14
1	1	0	Covered	T11,T13,T14
1	1	1	Covered	T11,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T14
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13

 LINE       113
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T14
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13

 LINE       113
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T13,T14

 LINE       113
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T11,T13,T14
1	1	0	Covered	T11,T13,T14
1	1	1	Covered	T11,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T14
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13

 LINE       113
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T13,T14

 LINE       113
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T14
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13

 LINE       113
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T13,T14
1	1	Covered	T11,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T13,T14
1	1	Covered	T11,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T13,T14
1	1	Covered	T11,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T19
1	0	Covered	T11,T13,T14
1	1	Covered	T11,T13,T19

 LINE       117
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T11,T15,T19
1	0	Covered	T11,T13,T14
1	1	Covered	T11,T15,T19

 LINE       117
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T13,T14
1	1	Covered	T11,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T13,T14
1	1	Covered	T11,T13,T14

 LINE       117
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T13,T14
1	1	Covered	T11,T13,T14

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	79	3	3	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	103	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	79	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T14,T15
0	1	Covered	T11,T12,T13
0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T13,T14,T16

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T13,T14,T16

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T13,T14,T16

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T13,T14,T16

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T13,T14,T16

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	100	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T13,T15

	LineNo.	Expression
-1-:	103	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T13,T14

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	31731398	31456705	0	0
gen_filter_match[0].MatchCheck00_A	31731398	9424736	0	0
gen_filter_match[0].MatchCheck01_A	31731398	2344487	0	0
gen_filter_match[0].MatchCheck10_A	31731398	1674368	0	0
gen_filter_match[0].MatchCheck11_A	31731398	18013114	0	0
gen_filter_match[1].MatchCheck00_A	31731398	10589671	0	0
gen_filter_match[1].MatchCheck01_A	31731398	1619781	0	0
gen_filter_match[1].MatchCheck10_A	31731398	1663553	0	0
gen_filter_match[1].MatchCheck11_A	31731398	17583700	0	0
gen_filter_match[2].MatchCheck00_A	31731398	10687775	0	0
gen_filter_match[2].MatchCheck01_A	31731398	558712	0	0
gen_filter_match[2].MatchCheck10_A	31731398	660540	0	0
gen_filter_match[2].MatchCheck11_A	31731398	19549678	0	0
gen_filter_match[3].MatchCheck00_A	31731398	12274936	0	0
gen_filter_match[3].MatchCheck01_A	31731398	487199	0	0
gen_filter_match[3].MatchCheck10_A	31731398	174781	0	0
gen_filter_match[3].MatchCheck11_A	31731398	18519789	0	0
gen_filter_match[4].MatchCheck00_A	31731398	12309242	0	0
gen_filter_match[4].MatchCheck01_A	31731398	66674	0	0
gen_filter_match[4].MatchCheck10_A	31731398	39929	0	0
gen_filter_match[4].MatchCheck11_A	31731398	19040860	0	0
gen_filter_match[5].MatchCheck00_A	31731398	12233194	0	0
gen_filter_match[5].MatchCheck01_A	31731398	33555	0	0
gen_filter_match[5].MatchCheck10_A	31731398	76	0	0
gen_filter_match[5].MatchCheck11_A	31731398	19189880	0	0
gen_filter_match[6].MatchCheck00_A	31731398	11734656	0	0
gen_filter_match[6].MatchCheck01_A	31731398	99379	0	0
gen_filter_match[6].MatchCheck10_A	31731398	64995	0	0
gen_filter_match[6].MatchCheck11_A	31731398	19557675	0	0
gen_filter_match[7].MatchCheck00_A	31731398	11865363	0	0
gen_filter_match[7].MatchCheck01_A	31731398	270545	0	0
gen_filter_match[7].MatchCheck10_A	31731398	232894	0	0
gen_filter_match[7].MatchCheck11_A	31731398	19087903	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	31456705	0	0
T11	32116	32033	0	0
T12	817	765	0	0
T13	66537	66472	0	0
T14	94134	91245	0	0
T15	116593	115781	0	0
T16	66060	65960	0	0
T17	1219	1125	0	0
T18	5475	5384	0	0
T19	36654	36568	0	0
T20	97095	97007	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	9424736	0	0
T11	32116	4	0	0
T12	817	765	0	0
T13	66537	33548	0	0
T14	94134	56602	0	0
T15	116593	66060	0	0
T16	66060	33071	0	0
T17	1219	1125	0	0
T18	5475	5384	0	0
T19	36654	3	0	0
T20	97095	3	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	2344487	0	0
T15	116593	49721	0	0
T16	66060	0	0	0
T17	1219	0	0	0
T18	5475	0	0	0
T19	36654	0	0	0
T20	97095	0	0	0
T21	73344	0	0	0
T38	9494	0	0	0
T54	0	32781	0	0
T92	1160	0	0	0
T94	0	66033	0	0
T95	0	32766	0	0
T96	0	1	0	0
T97	0	33420	0	0
T98	0	33877	0	0
T99	0	32190	0	0
T100	0	33076	0	0
T101	0	32826	0	0
T102	8047	0	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	1674368	0	0
T46	865	0	0	0
T51	751	0	0	0
T52	1231	0	0	0
T53	19108	0	0	0
T54	32853	0	0	0
T55	32536	32433	0	0
T91	15011	9537	0	0
T93	21608	0	0	0
T96	0	1	0	0
T97	0	33398	0	0
T103	32871	32784	0	0
T104	0	31871	0	0
T105	0	2	0	0
T106	0	14321	0	0
T107	0	2648	0	0
T108	0	33183	0	0
T109	33651	0	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	18013114	0	0
T11	32116	32029	0	0
T12	817	0	0	0
T13	66537	32924	0	0
T14	94134	34643	0	0
T15	116593	0	0	0
T16	66060	32889	0	0
T17	1219	0	0	0
T18	5475	0	0	0
T19	36654	36565	0	0
T20	97095	97004	0	0
T21	0	64340	0	0
T22	0	456	0	0
T23	0	33183	0	0
T60	0	33015	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	10589671	0	0
T11	32116	4	0	0
T12	817	765	0	0
T13	66537	33548	0	0
T14	94134	56599	0	0
T15	116593	83569	0	0
T16	66060	32893	0	0
T17	1219	1125	0	0
T18	5475	5384	0	0
T19	36654	36568	0	0
T20	97095	3	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	1619781	0	0
T22	18634	8702	0	0
T23	33243	0	0	0
T34	99791	0	0	0
T57	66431	33373	0	0
T58	1115	0	0	0
T59	66995	0	0	0
T60	66892	33015	0	0
T61	33181	0	0	0
T96	0	33079	0	0
T97	0	32717	0	0
T101	0	32210	0	0
T103	32871	0	0	0
T110	0	32513	0	0
T111	0	1	0	0
T112	0	33350	0	0
T113	0	32454	0	0
T114	4776	0	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	1663553	0	0
T14	94134	34646	0	0
T15	116593	0	0	0
T16	66060	0	0	0
T17	1219	0	0	0
T18	5475	0	0	0
T19	36654	0	0	0
T20	97095	0	0	0
T21	73344	0	0	0
T38	9494	0	0	0
T60	0	33799	0	0
T92	1160	0	0	0
T105	0	2	0	0
T111	0	2	0	0
T115	0	33595	0	0
T116	0	3	0	0
T117	0	1	0	0
T118	0	67451	0	0
T119	0	1	0	0
T120	0	1	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	17583700	0	0
T11	32116	32029	0	0
T12	817	0	0	0
T13	66537	32924	0	0
T14	94134	0	0	0
T15	116593	32212	0	0
T16	66060	33067	0	0
T17	1219	0	0	0
T18	5475	0	0	0
T19	36654	0	0	0
T20	97095	97004	0	0
T21	0	32460	0	0
T23	0	33183	0	0
T61	0	33089	0	0
T103	0	32784	0	0
T121	0	65867	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	10687775	0	0
T11	32116	4	0	0
T12	817	765	0	0
T13	66537	32928	0	0
T14	94134	57583	0	0
T15	116593	38975	0	0
T16	66060	65960	0	0
T17	1219	1125	0	0
T18	5475	5384	0	0
T19	36654	36568	0	0
T20	97095	3	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	558712	0	0
T61	33181	33089	0	0
T96	98988	1	0	0
T97	99635	0	0	0
T101	0	2	0	0
T103	32871	0	0	0
T111	0	1	0	0
T114	4776	0	0	0
T120	0	1	0	0
T122	0	35711	0	0
T123	0	32267	0	0
T124	0	33634	0	0
T125	0	27483	0	0
T126	0	1	0	0
T127	65779	0	0	0
T128	7674	0	0	0
T129	65815	0	0	0
T130	118207	0	0	0
T131	1210	0	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	660540	0	0
T95	65405	0	0	0
T96	98988	2	0	0
T101	0	2	0	0
T105	98291	2	0	0
T111	0	2	0	0
T115	33663	0	0	0
T116	0	3	0	0
T117	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T132	0	1	0	0
T133	0	2	0	0
T134	16577	0	0	0
T135	6070	0	0	0
T136	97135	0	0	0
T137	1180	0	0	0
T138	98317	0	0	0
T139	1163	0	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	19549678	0	0
T11	32116	32029	0	0
T12	817	0	0	0
T13	66537	33544	0	0
T14	94134	33662	0	0
T15	116593	76806	0	0
T16	66060	0	0	0
T17	1219	0	0	0
T18	5475	0	0	0
T19	36654	0	0	0
T20	97095	97004	0	0
T21	0	64340	0	0
T23	0	33183	0	0
T91	0	4284	0	0
T121	0	65867	0	0
T140	0	65656	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	12274936	0	0
T11	32116	4	0	0
T12	817	765	0	0
T13	66537	4	0	0
T14	94134	91245	0	0
T15	116593	115781	0	0
T16	66060	65960	0	0
T17	1219	1125	0	0
T18	5475	5384	0	0
T19	36654	3	0	0
T20	97095	3	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	487199	0	0
T96	98988	0	0	0
T97	99635	0	0	0
T98	101965	0	0	0
T111	0	1	0	0
T120	0	65712	0	0
T127	65779	0	0	0
T128	7674	0	0	0
T129	65815	0	0	0
T130	118207	32861	0	0
T131	1210	0	0	0
T141	68901	3	0	0
T142	0	2	0	0
T143	0	33239	0	0
T144	0	32321	0	0
T145	0	33002	0	0
T146	0	32921	0	0
T147	0	31743	0	0
T148	1132	0	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	174781	0	0
T95	65405	0	0	0
T96	0	1	0	0
T105	98291	1	0	0
T111	0	2	0	0
T115	33663	0	0	0
T116	0	2	0	0
T117	0	1	0	0
T119	0	1	0	0
T132	0	1	0	0
T133	0	2	0	0
T134	16577	0	0	0
T135	6070	0	0	0
T136	97135	0	0	0
T137	1180	0	0	0
T138	98317	0	0	0
T139	1163	0	0	0
T141	68901	3	0	0
T149	0	33010	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	18519789	0	0
T11	32116	32029	0	0
T12	817	0	0	0
T13	66537	66468	0	0
T14	94134	0	0	0
T15	116593	0	0	0
T16	66060	0	0	0
T17	1219	0	0	0
T18	5475	0	0	0
T19	36654	36565	0	0
T20	97095	97004	0	0
T21	0	31880	0	0
T22	0	8702	0	0
T23	0	33183	0	0
T60	0	33799	0	0
T121	0	65867	0	0
T140	0	65656	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	12309242	0	0
T11	32116	4	0	0
T12	817	765	0	0
T13	66537	66472	0	0
T14	94134	91245	0	0
T15	116593	98272	0	0
T16	66060	65960	0	0
T17	1219	1125	0	0
T18	5475	5384	0	0
T19	36654	3	0	0
T20	97095	3	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	66674	0	0
T47	965	0	0	0
T101	97371	1	0	0
T126	99904	1	0	0
T150	99550	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	2	0	0
T158	33668	0	0	0
T159	99630	0	0	0
T160	32843	0	0	0
T161	98588	0	0	0
T162	33681	0	0	0
T163	97959	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	39929	0	0
T95	65405	0	0	0
T96	0	2	0	0
T101	0	1	0	0
T105	98291	1	0	0
T115	33663	0	0	0
T116	0	2	0	0
T117	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T132	0	1	0	0
T134	16577	0	0	0
T135	6070	0	0	0
T136	97135	0	0	0
T137	1180	0	0	0
T138	98317	0	0	0
T139	1163	0	0	0
T141	68901	4	0	0
T159	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	19040860	0	0
T11	32116	32029	0	0
T12	817	0	0	0
T13	66537	0	0	0
T14	94134	0	0	0
T15	116593	17509	0	0
T16	66060	0	0	0
T17	1219	0	0	0
T18	5475	0	0	0
T19	36654	36565	0	0
T20	97095	97004	0	0
T21	0	32460	0	0
T22	0	8702	0	0
T23	0	33183	0	0
T60	0	66814	0	0
T121	0	65867	0	0
T140	0	65656	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	12233194	0	0
T11	32116	4	0	0
T12	817	765	0	0
T13	66537	32928	0	0
T14	94134	56599	0	0
T15	116593	83569	0	0
T16	66060	32893	0	0
T17	1219	1125	0	0
T18	5475	5384	0	0
T19	36654	36568	0	0
T20	97095	3	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	33555	0	0
T34	99791	0	0	0
T42	83	0	0	0
T47	965	0	0	0
T59	66995	33541	0	0
T101	97371	1	0	0
T104	31947	0	0	0
T150	0	1	0	0
T151	0	1	0	0
T156	0	1	0	0
T158	33668	0	0	0
T159	99630	0	0	0
T160	32843	0	0	0
T161	98588	0	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	2	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	76	0	0
T95	65405	0	0	0
T96	0	1	0	0
T101	0	1	0	0
T105	98291	2	0	0
T111	0	1	0	0
T115	33663	0	0	0
T116	0	3	0	0
T117	0	1	0	0
T119	0	1	0	0
T132	0	1	0	0
T134	16577	0	0	0
T135	6070	0	0	0
T136	97135	0	0	0
T137	1180	0	0	0
T138	98317	0	0	0
T139	1163	0	0	0
T141	68901	3	0	0
T159	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	19189880	0	0
T11	32116	32029	0	0
T12	817	0	0	0
T13	66537	33544	0	0
T14	94134	34646	0	0
T15	116593	32212	0	0
T16	66060	33067	0	0
T17	1219	0	0	0
T18	5475	0	0	0
T19	36654	0	0	0
T20	97095	97004	0	0
T22	0	8702	0	0
T23	0	33183	0	0
T61	0	33089	0	0
T103	0	32784	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	11734656	0	0
T11	32116	4	0	0
T12	817	765	0	0
T13	66537	4	0	0
T14	94134	56599	0	0
T15	116593	71187	0	0
T16	66060	33071	0	0
T17	1219	1125	0	0
T18	5475	5384	0	0
T19	36654	36568	0	0
T20	97095	3	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	99379	0	0
T47	965	0	0	0
T101	97371	2	0	0
T143	0	1	0	0
T154	0	2	0	0
T155	0	1	0	0
T158	33668	0	0	0
T159	99630	0	0	0
T160	32843	0	0	0
T161	98588	0	0	0
T166	0	1	0	0
T169	96972	32745	0	0
T170	0	32706	0	0
T171	0	33913	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	99122	0	0	0
T175	64964	0	0	0
T176	66989	0	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	64995	0	0
T46	865	0	0	0
T51	751	0	0	0
T52	1231	0	0	0
T53	19108	0	0	0
T54	32853	0	0	0
T55	32536	0	0	0
T56	27247	0	0	0
T57	66431	0	0	0
T93	21608	0	0	0
T96	0	2	0	0
T105	0	2	0	0
T109	33651	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T116	0	3	0	0
T117	0	1	0	0
T132	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	19557675	0	0
T11	32116	32029	0	0
T12	817	0	0	0
T13	66537	66468	0	0
T14	94134	34646	0	0
T15	116593	44594	0	0
T16	66060	32889	0	0
T17	1219	0	0	0
T18	5475	0	0	0
T19	36654	0	0	0
T20	97095	97004	0	0
T21	0	64340	0	0
T22	0	8702	0	0
T23	0	33183	0	0
T60	0	33015	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	11865363	0	0
T11	32116	4	0	0
T12	817	765	0	0
T13	66537	33548	0	0
T14	94134	22937	0	0
T15	116593	53678	0	0
T16	66060	4	0	0
T17	1219	1125	0	0
T18	5475	5384	0	0
T19	36654	3	0	0
T20	97095	3	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	270545	0	0
T21	73344	32460	0	0
T22	18634	0	0	0
T23	33243	0	0	0
T34	99791	33340	0	0
T60	66892	0	0	0
T61	33181	0	0	0
T102	8047	0	0	0
T103	32871	0	0	0
T104	31947	0	0	0
T111	0	1	0	0
T113	0	31960	0	0
T114	4776	0	0	0
T126	0	1	0	0
T141	0	2	0	0
T151	0	1	0	0
T164	0	1	0	0
T174	0	1	0	0
T179	0	32397	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	232894	0	0
T34	0	33197	0	0
T46	865	0	0	0
T51	751	0	0	0
T52	1231	0	0	0
T53	19108	0	0	0
T54	32853	0	0	0
T55	32536	0	0	0
T56	27247	0	0	0
T57	66431	0	0	0
T93	21608	0	0	0
T96	0	34014	0	0
T105	0	2	0	0
T109	33651	1	0	0
T116	0	2	0	0
T117	0	1	0	0
T132	0	1	0	0
T141	0	3	0	0
T178	0	1	0	0
T180	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31731398	19087903	0	0
T11	32116	32029	0	0
T12	817	0	0	0
T13	66537	32924	0	0
T14	94134	68308	0	0
T15	116593	62103	0	0
T16	66060	65956	0	0
T17	1219	0	0	0
T18	5475	0	0	0
T19	36654	36565	0	0
T20	97095	97004	0	0
T22	0	8702	0	0
T23	0	33183	0	0
T60	0	33015	0	0