Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	25	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	25	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	6505	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2043	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2154	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2006	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2454	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2169	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2229	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2132	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2225	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2226	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2185	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2138	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2078	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2096	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2244	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2160	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2141	0	0
adc_en_ctl_rd_A	2147483647	1900	0	0
adc_fsm_rst_rd_A	2147483647	1656	0	0
adc_intr_ctl_rd_A	2147483647	2038	0	0
adc_lp_sample_ctl_rd_A	2147483647	1552	0	0
adc_pd_ctl_rd_A	2147483647	2155	0	0
adc_sample_ctl_rd_A	2147483647	1730	0	0
adc_wakeup_ctl_rd_A	2147483647	1744	0	0
intr_enable_rd_A	2147483647	2802	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6505	0	0
T1	126657	2	0	0
T2	16267	1	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T9	0	1	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	215	0	0
T27	50256	0	0	0
T28	28319	0	0	0
T35	0	2	0	0
T40	0	279	0	0
T41	0	404	0	0
T63	0	136	0	0
T64	0	577	0	0
T79	0	1	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2043	0	0
T1	126657	45	0	0
T2	16267	0	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T6	0	36	0	0
T8	0	25	0	0
T10	0	80	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	27	0	0
T27	50256	0	0	0
T28	28319	0	0	0
T32	0	40	0	0
T35	0	8	0	0
T41	0	42	0	0
T71	0	18	0	0
T181	0	7	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2154	0	0
T1	126657	98	0	0
T2	16267	0	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T6	0	62	0	0
T8	0	6	0	0
T9	0	6	0	0
T10	0	88	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	6	0	0
T27	50256	0	0	0
T28	28319	0	0	0
T32	0	36	0	0
T35	0	14	0	0
T41	0	37	0	0
T71	0	12	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2006	0	0
T1	126657	67	0	0
T2	16267	0	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T6	0	13	0	0
T8	0	21	0	0
T9	0	5	0	0
T10	0	67	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	2	0	0
T27	50256	0	0	0
T28	28319	0	0	0
T32	0	25	0	0
T35	0	15	0	0
T41	0	31	0	0
T71	0	16	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2454	0	0
T1	126657	100	0	0
T2	16267	0	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T6	0	42	0	0
T8	0	41	0	0
T9	0	9	0	0
T10	0	107	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	20	0	0
T27	50256	0	0	0
T28	28319	0	0	0
T32	0	61	0	0
T35	0	6	0	0
T41	0	37	0	0
T71	0	12	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2169	0	0
T1	126657	74	0	0
T2	16267	0	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T6	0	45	0	0
T8	0	8	0	0
T9	0	1	0	0
T10	0	63	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	25	0	0
T27	50256	0	0	0
T28	28319	0	0	0
T32	0	17	0	0
T35	0	7	0	0
T41	0	27	0	0
T71	0	17	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2229	0	0
T1	126657	91	0	0
T2	16267	0	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T6	0	7	0	0
T8	0	29	0	0
T9	0	14	0	0
T10	0	140	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	15	0	0
T27	50256	0	0	0
T28	28319	0	0	0
T32	0	27	0	0
T35	0	8	0	0
T41	0	43	0	0
T71	0	9	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2132	0	0
T1	126657	90	0	0
T2	16267	0	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T6	0	50	0	0
T8	0	5	0	0
T9	0	10	0	0
T10	0	112	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	7	0	0
T27	50256	0	0	0
T28	28319	0	0	0
T32	0	51	0	0
T35	0	6	0	0
T41	0	29	0	0
T71	0	20	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2225	0	0
T1	126657	79	0	0
T2	16267	0	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T6	0	47	0	0
T8	0	15	0	0
T9	0	5	0	0
T10	0	81	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	18	0	0
T27	50256	0	0	0
T28	28319	0	0	0
T32	0	45	0	0
T35	0	12	0	0
T41	0	77	0	0
T71	0	3	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2226	0	0
T1	126657	84	0	0
T2	16267	0	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T6	0	39	0	0
T8	0	20	0	0
T10	0	77	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	5	0	0
T27	50256	0	0	0
T28	28319	0	0	0
T32	0	8	0	0
T35	0	7	0	0
T41	0	12	0	0
T71	0	4	0	0
T181	0	5	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2185	0	0
T1	126657	58	0	0
T2	16267	0	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T6	0	19	0	0
T8	0	15	0	0
T9	0	9	0	0
T10	0	110	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	16	0	0
T27	50256	0	0	0
T28	28319	0	0	0
T32	0	58	0	0
T35	0	6	0	0
T41	0	31	0	0
T71	0	4	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2138	0	0
T1	126657	87	0	0
T2	16267	0	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T6	0	32	0	0
T8	0	5	0	0
T9	0	1	0	0
T10	0	106	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	5	0	0
T27	50256	0	0	0
T28	28319	0	0	0
T32	0	19	0	0
T35	0	7	0	0
T41	0	26	0	0
T71	0	8	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2078	0	0
T1	126657	89	0	0
T2	16267	0	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T6	0	35	0	0
T8	0	13	0	0
T10	0	102	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	5	0	0
T27	50256	0	0	0
T28	28319	0	0	0
T32	0	24	0	0
T35	0	4	0	0
T41	0	58	0	0
T71	0	4	0	0
T181	0	2	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2096	0	0
T1	126657	101	0	0
T2	16267	0	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T6	0	24	0	0
T8	0	18	0	0
T9	0	10	0	0
T10	0	94	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	18	0	0
T27	50256	0	0	0
T28	28319	0	0	0
T32	0	54	0	0
T35	0	9	0	0
T41	0	48	0	0
T71	0	4	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2244	0	0
T1	126657	74	0	0
T2	16267	0	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T6	0	35	0	0
T8	0	21	0	0
T9	0	6	0	0
T10	0	77	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	7	0	0
T27	50256	0	0	0
T28	28319	0	0	0
T32	0	86	0	0
T35	0	11	0	0
T41	0	14	0	0
T71	0	1	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2160	0	0
T1	126657	125	0	0
T2	16267	0	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T6	0	39	0	0
T8	0	8	0	0
T9	0	14	0	0
T10	0	90	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	0	0	0
T27	50256	0	0	0
T28	28319	0	0	0
T32	0	38	0	0
T35	0	15	0	0
T41	0	27	0	0
T71	0	21	0	0
T182	0	26	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2141	0	0
T1	126657	78	0	0
T2	16267	0	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T6	0	59	0	0
T8	0	10	0	0
T9	0	3	0	0
T10	0	78	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	0	0	0
T27	50256	0	0	0
T28	28319	0	0	0
T32	0	65	0	0
T35	0	3	0	0
T41	0	40	0	0
T71	0	2	0	0
T182	0	35	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1900	0	0
T1	126657	34	0	0
T2	16267	0	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T6	0	44	0	0
T8	0	13	0	0
T9	0	11	0	0
T10	0	40	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	4	0	0
T27	50256	0	0	0
T28	28319	0	0	0
T32	0	18	0	0
T35	0	4	0	0
T41	0	30	0	0
T71	0	6	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1656	0	0
T1	126657	36	0	0
T2	16267	0	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T6	0	48	0	0
T8	0	34	0	0
T10	0	49	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	26	0	0
T27	50256	0	0	0
T28	28319	0	0	0
T32	0	41	0	0
T35	0	8	0	0
T41	0	28	0	0
T71	0	4	0	0
T182	0	33	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2038	0	0
T1	126657	39	0	0
T2	16267	0	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T6	0	55	0	0
T8	0	24	0	0
T9	0	4	0	0
T10	0	20	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	8	0	0
T27	50256	0	0	0
T28	28319	0	0	0
T32	0	33	0	0
T35	0	8	0	0
T41	0	34	0	0
T71	0	7	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1552	0	0
T1	126657	31	0	0
T2	16267	0	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T6	0	10	0	0
T8	0	6	0	0
T9	0	7	0	0
T10	0	29	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	3	0	0
T27	50256	0	0	0
T28	28319	0	0	0
T32	0	51	0	0
T35	0	9	0	0
T41	0	9	0	0
T71	0	1	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2155	0	0
T1	126657	94	0	0
T2	16267	0	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T6	0	54	0	0
T8	0	38	0	0
T10	0	99	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	14	0	0
T27	50256	0	0	0
T28	28319	0	0	0
T32	0	36	0	0
T35	0	2	0	0
T41	0	58	0	0
T71	0	8	0	0
T182	0	64	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1730	0	0
T1	126657	29	0	0
T2	16267	0	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T6	0	34	0	0
T8	0	37	0	0
T9	0	5	0	0
T10	0	36	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	7	0	0
T27	50256	0	0	0
T28	28319	0	0	0
T32	0	54	0	0
T35	0	13	0	0
T41	0	29	0	0
T71	0	3	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1744	0	0
T1	126657	37	0	0
T2	16267	0	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T6	0	58	0	0
T8	0	31	0	0
T9	0	3	0	0
T10	0	27	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	15	0	0
T27	50256	0	0	0
T28	28319	0	0	0
T32	0	44	0	0
T35	0	7	0	0
T41	0	48	0	0
T71	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2802	0	0
T1	126657	31	0	0
T2	16267	0	0	0
T3	14091	0	0	0
T4	14582	0	0	0
T5	23916	0	0	0
T6	0	25	0	0
T8	0	16	0	0
T9	0	4	0	0
T10	0	32	0	0
T24	24951	0	0	0
T25	12732	0	0	0
T26	13178	7	0	0
T27	50256	3	0	0
T28	28319	0	0	0
T31	0	12	0	0
T35	0	12	0	0
T41	0	37	0	0