Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1225505	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1181522

1

T1

920

T2

397

T3

431

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2108679	1			T1	1691		T3	824		T4	1763
values[0x0]	148959	1			T1	103		T2	514		T3	52
values[0x1]	149389	1			T1	88		T2	521		T3	48

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	986455	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1420572

1

T1

1086

T2

490

T3

528

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11709	1			T2	4		T3	4		T4	8
valid_sources[0x01]	15245	1			T2	6		T3	3		T4	21
valid_sources[0x02]	11472	1			T2	5		T3	3		T4	8
valid_sources[0x03]	10384	1			T2	2		T3	1		T4	8
valid_sources[0x04]	7327	1			T2	6		T3	1		T4	2
valid_sources[0x05]	7330	1			T2	1		T3	2		T4	11
valid_sources[0x06]	7361	1			T2	3		T3	5		T4	5
valid_sources[0x07]	7235	1			T2	5		T3	2		T4	12
valid_sources[0x08]	7428	1			T2	7		T3	4		T4	6
valid_sources[0x09]	11826	1			T2	5		T3	3		T4	15
valid_sources[0x0a]	7331	1			T2	3		T4	7		T6	33
valid_sources[0x0b]	7075	1			T2	6		T3	5		T4	3
valid_sources[0x0c]	7385	1			T2	5		T3	6		T4	7
valid_sources[0x0d]	11477	1			T2	4		T3	3		T4	7
valid_sources[0x0e]	7190	1			T2	1		T3	3		T4	6
valid_sources[0x0f]	9361	1			T2	8		T3	1		T4	7
valid_sources[0x10]	7698	1			T2	2		T3	2		T4	10
valid_sources[0x11]	18929	1			T2	2		T3	4		T4	11
valid_sources[0x12]	11606	1			T2	5		T3	5		T4	9
valid_sources[0x13]	14006	1			T2	1		T3	2		T4	3
valid_sources[0x14]	7963	1			T2	7		T3	2		T4	7
valid_sources[0x15]	7497	1			T2	6		T3	3		T4	2
valid_sources[0x16]	7301	1			T2	5		T3	3		T4	6
valid_sources[0x17]	13248	1			T2	8		T3	3		T4	6
valid_sources[0x18]	12496	1			T2	1		T3	2		T4	13
valid_sources[0x19]	7270	1			T2	7		T3	5		T4	3
valid_sources[0x1a]	12333	1			T2	8		T3	2		T4	5
valid_sources[0x1b]	7167	1			T2	3		T3	4		T4	8
valid_sources[0x1c]	7120	1			T2	6		T3	5		T4	5
valid_sources[0x1d]	8485	1			T2	4		T3	11		T4	11
valid_sources[0x1e]	7344	1			T2	6		T3	2		T4	9
valid_sources[0x1f]	8216	1			T2	3		T3	3		T4	3
valid_sources[0x20]	7416	1			T2	2		T3	2		T4	8
valid_sources[0x21]	8024	1			T2	2		T4	3		T5	2
valid_sources[0x22]	13383	1			T2	2		T3	1		T4	8
valid_sources[0x23]	8506	1			T2	1		T3	4		T4	5
valid_sources[0x24]	7249	1			T2	1		T3	9		T4	6
valid_sources[0x25]	7408	1			T2	4		T3	1		T4	4
valid_sources[0x26]	15129	1			T2	2		T4	6		T5	2
valid_sources[0x27]	8065	1			T2	1		T3	3		T4	6
valid_sources[0x28]	8272	1			T2	5		T3	1		T4	13
valid_sources[0x29]	7466	1			T2	4		T3	8		T4	5
valid_sources[0x2a]	9104	1			T2	3		T3	2		T4	13
valid_sources[0x2b]	9547	1			T2	3		T3	4		T4	17
valid_sources[0x2c]	7720	1			T2	7		T3	1		T4	10
valid_sources[0x2d]	8728	1			T2	5		T3	3		T4	9
valid_sources[0x2e]	7563	1			T2	4		T3	4		T4	4
valid_sources[0x2f]	7253	1			T2	5		T3	6		T4	8
valid_sources[0x30]	7291	1			T2	3		T3	3		T4	6
valid_sources[0x31]	11377	1			T2	9		T3	4		T4	14
valid_sources[0x32]	10684	1			T2	4		T3	6		T4	9
valid_sources[0x33]	7086	1			T2	6		T3	4		T4	8
valid_sources[0x34]	7704	1			T2	5		T3	4		T4	7
valid_sources[0x35]	8941	1			T2	1		T3	4		T4	4
valid_sources[0x36]	11306	1			T2	5		T3	1		T4	3
valid_sources[0x37]	7127	1			T2	2		T3	3		T4	2
valid_sources[0x38]	9114	1			T1	1882		T2	3		T3	2
valid_sources[0x39]	8741	1			T2	5		T3	2		T4	12
valid_sources[0x3a]	16713	1			T2	8		T3	3		T4	7
valid_sources[0x3b]	8826	1			T2	4		T3	4		T4	7
valid_sources[0x3c]	7193	1			T2	5		T3	2		T4	8
valid_sources[0x3d]	7104	1			T2	1		T3	4		T4	5
valid_sources[0x3e]	12219	1			T2	3		T3	2		T4	7
valid_sources[0x3f]	15454	1			T2	1		T3	4		T4	6
valid_sources[0x40]	6962	1			T2	8		T3	1		T4	6
valid_sources[0x41]	7136	1			T2	10		T3	6		T4	3
valid_sources[0x42]	15784	1			T2	9		T4	1		T5	4
valid_sources[0x43]	10448	1			T2	5		T3	2		T4	7
valid_sources[0x44]	11816	1			T2	2		T3	3		T4	6
valid_sources[0x45]	11436	1			T2	11		T3	2		T4	3
valid_sources[0x46]	11689	1			T2	1		T3	4		T4	11
valid_sources[0x47]	7531	1			T2	3		T3	5		T4	7
valid_sources[0x48]	11326	1			T2	3		T3	2		T4	7
valid_sources[0x49]	7376	1			T2	4		T3	5		T4	16
valid_sources[0x4a]	7251	1			T2	5		T3	3		T4	6
valid_sources[0x4b]	11166	1			T2	4		T4	9		T5	2
valid_sources[0x4c]	6931	1			T2	2		T3	7		T4	6
valid_sources[0x4d]	8300	1			T2	2		T3	2		T4	5
valid_sources[0x4e]	7502	1			T2	5		T3	4		T4	8
valid_sources[0x4f]	12127	1			T2	3		T3	6		T4	10
valid_sources[0x50]	7073	1			T2	3		T3	2		T4	7
valid_sources[0x51]	7727	1			T2	3		T3	4		T4	9
valid_sources[0x52]	15143	1			T2	3		T3	4		T4	11
valid_sources[0x53]	7973	1			T2	5		T3	5		T4	10
valid_sources[0x54]	11476	1			T2	5		T3	2		T4	8
valid_sources[0x55]	7615	1			T2	8		T3	1		T4	6
valid_sources[0x56]	7413	1			T2	5		T3	3		T4	8
valid_sources[0x57]	7668	1			T2	2		T3	4		T4	6
valid_sources[0x58]	8523	1			T2	6		T3	1		T4	8
valid_sources[0x59]	10725	1			T2	3		T3	3		T4	10
valid_sources[0x5a]	8710	1			T3	3		T4	3		T5	2
valid_sources[0x5b]	8428	1			T2	10		T3	2		T4	7
valid_sources[0x5c]	9170	1			T2	6		T3	2		T4	12
valid_sources[0x5d]	7599	1			T2	4		T3	3		T4	6
valid_sources[0x5e]	7547	1			T2	4		T3	4		T4	7
valid_sources[0x5f]	7093	1			T2	3		T3	5		T4	9
valid_sources[0x60]	12317	1			T2	3		T3	4		T4	7
valid_sources[0x61]	7583	1			T2	6		T3	7		T4	8
valid_sources[0x62]	10270	1			T4	4		T5	2		T6	7
valid_sources[0x63]	11220	1			T2	4		T3	4		T4	6
valid_sources[0x64]	7235	1			T2	9		T3	6		T4	18
valid_sources[0x65]	8516	1			T2	5		T3	2		T4	1
valid_sources[0x66]	6881	1			T2	8		T3	4		T4	7
valid_sources[0x67]	11552	1			T2	3		T3	2		T4	4
valid_sources[0x68]	8056	1			T2	1		T3	5		T4	9
valid_sources[0x69]	9125	1			T3	3		T4	5		T6	26
valid_sources[0x6a]	7183	1			T2	6		T3	6		T4	7
valid_sources[0x6b]	7217	1			T2	6		T3	5		T4	6
valid_sources[0x6c]	11442	1			T2	6		T3	4		T4	6
valid_sources[0x6d]	10951	1			T2	5		T3	2		T4	9
valid_sources[0x6e]	22119	1			T2	2		T3	1		T4	2
valid_sources[0x6f]	11524	1			T2	3		T3	2		T4	7
valid_sources[0x70]	7318	1			T2	5		T3	4		T4	2
valid_sources[0x71]	11468	1			T2	1		T3	4		T4	7
valid_sources[0x72]	8302	1			T2	6		T3	1		T4	13
valid_sources[0x73]	11662	1			T2	3		T3	4		T4	12
valid_sources[0x74]	15461	1			T2	3		T3	3		T4	14
valid_sources[0x75]	8243	1			T2	4		T3	5		T4	14
valid_sources[0x76]	15481	1			T2	2		T3	3		T4	14
valid_sources[0x77]	11915	1			T2	3		T3	1		T4	6
valid_sources[0x78]	7030	1			T2	3		T3	3		T4	10
valid_sources[0x79]	7215	1			T2	4		T3	3		T4	6
valid_sources[0x7a]	7480	1			T3	1		T4	9		T5	2
valid_sources[0x7b]	7167	1			T2	2		T3	6		T4	6
valid_sources[0x7c]	10849	1			T2	3		T3	4		T4	2
valid_sources[0x7d]	8059	1			T2	1		T3	2		T4	14
valid_sources[0x7e]	11307	1			T2	2		T3	4		T4	5
valid_sources[0x7f]	11959	1			T2	5		T3	2		T4	14
valid_sources[0x80]	7861	1			T2	3		T3	7		T4	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1050636

1

T1

838

T3

397

T4

877

values[0x0]

all_enables

biggest_size

75901

1

T1

53

T2

220

T3

17

values[0x1]

all_enables

biggest_size

54985

1

T1

29

T2

177

T3

17