Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	29031	1			T1	12		T2	287		T3	5
auto[PWRUP]	109	1			T2	3		T8	1		T9	2
auto[ONEST_0]	72	1			T2	1		T8	1		T22	1
auto[ONEST_021]	12	1			T9	1		T227	1		T228	1
auto[ONEST_1]	82	1			T2	1		T9	1		T22	1
auto[ONEST_DONE]	3	1			T25	1		T57	1		T229	1
auto[LP_0]	111	1			T2	8		T8	1		T9	2
auto[LP_021]	26	1			T2	1		T8	1		T9	2
auto[LP_1]	130	1			T2	2		T8	1		T9	2
auto[LP_EVAL]	81	1			T9	1		T22	1		T23	1
auto[LP_SLP]	496	1			T2	5		T8	3		T9	4
auto[LP_PWRUP]	33	1			T14	1		T22	1		T19	1
auto[NP_0]	148	1			T2	2		T8	2		T9	1
auto[NP_021]	39	1			T8	1		T9	2		T22	2
auto[NP_1]	170	1			T2	4		T8	2		T14	2
auto[NP_EVAL]	41	1			T8	1		T14	1		T23	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T212

1

T230

1

T231

1

min

28503

1

T1

12

T2

284

T3

5

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28513	1			T1	12		T2	284		T3	5
pow[0x1]	4	1			T22	1		T232	1		T229	1
pow[0x2]	17	1			T23	1		T31	1		T127	1
pow[0x3]	37	1			T2	1		T8	1		T22	1
pow[0x4]	64	1			T14	1		T22	1		T31	1
pow[0x5]	141	1			T2	2		T14	2		T22	3
pow[0x6]	292	1			T2	5		T8	6		T9	12
pow[0x7]	519	1			T2	7		T8	3		T9	3

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

205

1

T2

3

T8

2

T9

3

min

28036

1

T1

12

T2

279

T3

5

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28036	1			T1	12		T2	279		T3	5
pow[0x6]	2	1			T26	1		T233	1		-	-
pow[0x7]	1	1			T25	1		-	-		-	-
pow[0x8]	8	1			T234	1		T212	1		T26	1
pow[0x9]	7	1			T235	1		T206	1		T127	1
pow[0xa]	9	1			T31	1		T234	1		T236	1
pow[0xb]	31	1			T2	1		T8	2		T22	1
pow[0xc]	67	1			T2	1		T14	1		T22	1
pow[0xd]	155	1			T2	1		T8	2		T9	2
pow[0xe]	293	1			T2	2		T8	3		T9	1
pow[0xf]	564	1			T2	7		T8	3		T9	9