Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2299	1			T2	16		T8	16		T9	22
auto[PWRUP]	151	1			T2	2		T14	1		T22	3
auto[ONEST_0]	72	1			T9	1		T22	1		T23	1
auto[ONEST_021]	16	1			T2	1		T22	2		T19	1
auto[ONEST_1]	83	1			T2	1		T9	2		T14	1
auto[ONEST_DONE]	2	1			T358	1		T359	1		-	-
auto[LP_0]	133	1			T2	3		T9	1		T14	4
auto[LP_021]	26	1			T8	1		T9	1		T235	1
auto[LP_1]	144	1			T2	1		T8	2		T14	2
auto[LP_EVAL]	75	1			T9	1		T14	2		T16	1
auto[LP_SLP]	530	1			T2	7		T8	7		T9	4
auto[LP_PWRUP]	30	1			T14	1		T23	2		T227	1
auto[NP_0]	249	1			T2	2		T8	2		T9	2
auto[NP_021]	55	1			T8	1		T14	2		T22	2
auto[NP_1]	267	1			T2	1		T8	2		T9	6
auto[NP_EVAL]	32	1			T2	1		T9	1		T14	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

11

1

T16

1

T360

1

T216

1

min

2040

1

T2

10

T8

9

T9

27

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2046	1			T2	10		T8	9		T9	27
pow[0x1]	12	1			T23	1		T218	1		T228	1
pow[0x2]	17	1			T22	2		T206	1		T361	1
pow[0x3]	39	1			T9	1		T14	1		T16	1
pow[0x4]	63	1			T23	2		T19	1		T31	1
pow[0x5]	134	1			T2	1		T8	1		T9	2
pow[0x6]	268	1			T2	4		T8	3		T9	2
pow[0x7]	526	1			T2	2		T8	11		T9	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

207

1

T2

3

T8

1

T9

3

min

1425

1

T2

1

T8

2

T9

18

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1431	1			T2	1		T8	2		T9	18
pow[0x1]	18	1			T54	1		T209	1		T211	3
pow[0x2]	44	1			T16	1		T24	6		T54	3
pow[0x3]	60	1			T14	6		T16	1		T218	1
pow[0x4]	53	1			T9	5		T31	2		T218	1
pow[0x5]	2	1			T362	1		T35	1		-	-
pow[0x7]	4	1			T67	1		T230	1		T363	2
pow[0x8]	7	1			T232	1		T236	1		T216	2
pow[0x9]	6	1			T364	1		T270	1		T365	1
pow[0xa]	25	1			T14	1		T228	1		T170	1
pow[0xb]	32	1			T8	1		T14	1		T22	1
pow[0xc]	79	1			T8	1		T14	1		T22	1
pow[0xd]	149	1			T2	2		T8	3		T9	1
pow[0xe]	297	1			T2	8		T8	4		T9	2
pow[0xf]	605	1			T2	7		T8	5		T9	8