Unified Coverage Report :: Module :: adc_ctrl_fsm_sva

Module : adc_ctrl_fsm_sva

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_sva_0.1/adc_ctrl_fsm_sva.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva	100.00						100.00

---

Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	96.84		100.00	92.77	100.00	u_adc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_fsm_sva

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FsmStateHwReset_A	1196	1196	0	0
FsmStateSwReset_A	29891262	6578	0	0
LpSampleCntHwReset_A	1196	1196	0	0
LpSampleCntSwReset_A	29891262	6578	0	0
NpSampleCntHwReset_A	1196	1196	0	0
NpSampleCntSwReset_A	29891262	6578	0	0
PwrupTimerCntHwReset_A	1196	1196	0	0
PwrupTimerCntSwReset_A	29891262	6578	0	0
WakeupTimerCntHwReset_A	1196	1196	0	0
WakeupTimerCntSwReset_A	29891262	6578	0	0

FsmStateHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196	1196	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	3	3	0	0
T9	11	11	0	0
T10	4	4	0	0

FsmStateSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29891262	6578	0	0
T1	66091	12	0	0
T2	84	0	0	0
T3	32240	5	0	0
T4	31626	4	0	0
T5	32881	10	0	0
T6	63875	12	0	0
T7	32009	7	0	0
T8	4904	0	0	0
T9	70812	6	0	0
T10	39358	8	0	0
T11	0	22	0	0
T12	0	5	0	0

LpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196	1196	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	3	3	0	0
T9	11	11	0	0
T10	4	4	0	0

LpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29891262	6578	0	0
T1	66091	12	0	0
T2	84	0	0	0
T3	32240	5	0	0
T4	31626	4	0	0
T5	32881	10	0	0
T6	63875	12	0	0
T7	32009	7	0	0
T8	4904	0	0	0
T9	70812	6	0	0
T10	39358	8	0	0
T11	0	22	0	0
T12	0	5	0	0

NpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196	1196	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	3	3	0	0
T9	11	11	0	0
T10	4	4	0	0

NpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29891262	6578	0	0
T1	66091	12	0	0
T2	84	0	0	0
T3	32240	5	0	0
T4	31626	4	0	0
T5	32881	10	0	0
T6	63875	12	0	0
T7	32009	7	0	0
T8	4904	0	0	0
T9	70812	6	0	0
T10	39358	8	0	0
T11	0	22	0	0
T12	0	5	0	0

PwrupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196	1196	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	3	3	0	0
T9	11	11	0	0
T10	4	4	0	0

PwrupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29891262	6578	0	0
T1	66091	12	0	0
T2	84	0	0	0
T3	32240	5	0	0
T4	31626	4	0	0
T5	32881	10	0	0
T6	63875	12	0	0
T7	32009	7	0	0
T8	4904	0	0	0
T9	70812	6	0	0
T10	39358	8	0	0
T11	0	22	0	0
T12	0	5	0	0

WakeupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196	1196	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	3	3	0	0
T9	11	11	0	0
T10	4	4	0	0

WakeupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29891262	6578	0	0
T1	66091	12	0	0
T2	84	0	0	0
T3	32240	5	0	0
T4	31626	4	0	0
T5	32881	10	0	0
T6	63875	12	0	0
T7	32009	7	0	0
T8	4904	0	0	0
T9	70812	6	0	0
T10	39358	8	0	0
T11	0	22	0	0
T12	0	5	0	0