Unified Coverage Report :: Module :: adc_ctrl_intr

Module : adc_ctrl_intr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.46	95.00	87.50			88.89

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_intr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr	90.46	95.00	87.50			88.89

---

Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.46	95.00	87.50			88.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.01	98.67	84.62			96.77	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_adc_ctrl_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
i_adc_ctrl_intr_o	100.00	100.00	100.00			100.00	100.00
u_match_sync	87.50	100.00	50.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_intr

	Line No.	Total	Covered	Percent
TOTAL		20	19	95.00
ALWAYS	40	8	7	87.50
CONT_ASSIGN	55	1	1	100.00
ALWAYS	59	6	6	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	99	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_intr.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_intr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	1	1
41	1	1
42	1	1
43	0	1
44	1	1
45	1	1
46	1	1
47	1	1
			MISSING_ELSE
55	1	1
59	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
88	1	1
91	1	1
92	1	1
96	1	1
99	1	1

---

Cond Coverage for Module : adc_ctrl_intr

	Total	Covered	Percent
Conditions	8	7	87.50
Logical	8	7	87.50
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (aon_ld_req && ((|aon_filter_match_i)))
             -----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       55
 EXPRESSION ((aon_req_hold == '0) & ((|staging_filter_match)))
             ----------1---------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       55
 SUB-EXPRESSION (aon_req_hold == '0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : adc_ctrl_intr

	Line No.	Total	Covered	Percent
Branches		9	8	88.89
IF	40	5	4	80.00
IF	59	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_intr.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_intr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	40	if ((!rst_aon_ni))
-2-:	42	if ((aon_ld_req && (|aon_filter_match_i)))
-3-:	44	if (aon_ld_req)
-4-:	46	if ((|aon_filter_match_i))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Covered	T1,T3,T4
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	59	if ((!rst_aon_ni))
-2-:	61	if (aon_ld_req)
-3-:	63	if (aon_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3