Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	25	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	25	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	6031	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1782	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1888	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1990	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1967	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1827	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1774	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1901	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1760	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1773	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1895	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1778	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1838	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1813	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1724	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1857	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1813	0	0
adc_en_ctl_rd_A	2147483647	1547	0	0
adc_fsm_rst_rd_A	2147483647	1405	0	0
adc_intr_ctl_rd_A	2147483647	1384	0	0
adc_lp_sample_ctl_rd_A	2147483647	1355	0	0
adc_pd_ctl_rd_A	2147483647	1733	0	0
adc_sample_ctl_rd_A	2147483647	1178	0	0
adc_wakeup_ctl_rd_A	2147483647	1404	0	0
intr_enable_rd_A	2147483647	1848	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6031	0	0
T46	0	1	0	0
T54	304160	2	0	0
T55	0	2	0	0
T61	165722	0	0	0
T62	393992	0	0	0
T63	147160	0	0	0
T64	485673	0	0	0
T189	0	1	0	0
T208	243545	1	0	0
T209	0	1	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	0	1	0	0
T213	0	1	0	0
T214	805906	0	0	0
T215	106613	0	0	0
T216	809393	0	0	0
T217	157034	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1782	0	0
T9	417014	27	0	0
T10	314959	0	0	0
T11	454221	0	0	0
T12	118063	0	0	0
T14	870191	0	0	0
T15	319089	0	0	0
T20	303789	0	0	0
T21	672239	0	0	0
T24	0	26	0	0
T37	30866	0	0	0
T53	0	33	0	0
T70	295361	0	0	0
T189	0	41	0	0
T218	0	25	0	0
T219	0	19	0	0
T220	0	5	0	0
T221	0	46	0	0
T222	0	19	0	0
T223	0	24	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1888	0	0
T9	417014	33	0	0
T10	314959	0	0	0
T11	454221	0	0	0
T12	118063	0	0	0
T14	870191	0	0	0
T15	319089	0	0	0
T20	303789	0	0	0
T21	672239	0	0	0
T24	0	24	0	0
T37	30866	0	0	0
T53	0	25	0	0
T70	295361	0	0	0
T189	0	42	0	0
T218	0	38	0	0
T219	0	24	0	0
T220	0	26	0	0
T221	0	32	0	0
T222	0	24	0	0
T223	0	42	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1990	0	0
T9	417014	31	0	0
T10	314959	0	0	0
T11	454221	0	0	0
T12	118063	0	0	0
T14	870191	0	0	0
T15	319089	0	0	0
T20	303789	0	0	0
T21	672239	0	0	0
T24	0	27	0	0
T37	30866	0	0	0
T53	0	17	0	0
T70	295361	0	0	0
T189	0	55	0	0
T218	0	28	0	0
T219	0	43	0	0
T220	0	5	0	0
T221	0	39	0	0
T222	0	41	0	0
T223	0	43	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1967	0	0
T9	417014	22	0	0
T10	314959	0	0	0
T11	454221	0	0	0
T12	118063	0	0	0
T14	870191	0	0	0
T15	319089	0	0	0
T20	303789	0	0	0
T21	672239	0	0	0
T24	0	14	0	0
T37	30866	0	0	0
T53	0	24	0	0
T70	295361	0	0	0
T189	0	65	0	0
T218	0	33	0	0
T219	0	40	0	0
T220	0	6	0	0
T221	0	40	0	0
T222	0	44	0	0
T223	0	31	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1827	0	0
T9	417014	47	0	0
T10	314959	0	0	0
T11	454221	0	0	0
T12	118063	0	0	0
T14	870191	0	0	0
T15	319089	0	0	0
T20	303789	0	0	0
T21	672239	0	0	0
T24	0	32	0	0
T37	30866	0	0	0
T53	0	23	0	0
T70	295361	0	0	0
T189	0	44	0	0
T218	0	37	0	0
T219	0	22	0	0
T220	0	18	0	0
T221	0	34	0	0
T222	0	8	0	0
T223	0	29	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1774	0	0
T9	417014	18	0	0
T10	314959	0	0	0
T11	454221	0	0	0
T12	118063	0	0	0
T14	870191	0	0	0
T15	319089	0	0	0
T20	303789	0	0	0
T21	672239	0	0	0
T24	0	15	0	0
T37	30866	0	0	0
T53	0	19	0	0
T70	295361	0	0	0
T189	0	38	0	0
T218	0	23	0	0
T219	0	20	0	0
T220	0	23	0	0
T221	0	36	0	0
T222	0	13	0	0
T223	0	35	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1901	0	0
T9	417014	27	0	0
T10	314959	0	0	0
T11	454221	0	0	0
T12	118063	0	0	0
T14	870191	0	0	0
T15	319089	0	0	0
T20	303789	0	0	0
T21	672239	0	0	0
T24	0	33	0	0
T37	30866	0	0	0
T53	0	25	0	0
T70	295361	0	0	0
T189	0	62	0	0
T218	0	47	0	0
T219	0	14	0	0
T220	0	18	0	0
T221	0	41	0	0
T222	0	23	0	0
T223	0	36	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1760	0	0
T9	417014	30	0	0
T10	314959	0	0	0
T11	454221	0	0	0
T12	118063	0	0	0
T14	870191	0	0	0
T15	319089	0	0	0
T20	303789	0	0	0
T21	672239	0	0	0
T24	0	31	0	0
T37	30866	0	0	0
T53	0	15	0	0
T70	295361	0	0	0
T189	0	19	0	0
T218	0	55	0	0
T219	0	23	0	0
T220	0	9	0	0
T221	0	39	0	0
T222	0	31	0	0
T223	0	34	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1773	0	0
T9	417014	33	0	0
T10	314959	0	0	0
T11	454221	0	0	0
T12	118063	0	0	0
T14	870191	0	0	0
T15	319089	0	0	0
T20	303789	0	0	0
T21	672239	0	0	0
T24	0	8	0	0
T37	30866	0	0	0
T53	0	24	0	0
T70	295361	0	0	0
T189	0	47	0	0
T218	0	18	0	0
T219	0	17	0	0
T220	0	19	0	0
T221	0	50	0	0
T222	0	20	0	0
T223	0	28	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1895	0	0
T9	417014	37	0	0
T10	314959	0	0	0
T11	454221	0	0	0
T12	118063	0	0	0
T14	870191	0	0	0
T15	319089	0	0	0
T20	303789	0	0	0
T21	672239	0	0	0
T24	0	20	0	0
T37	30866	0	0	0
T53	0	26	0	0
T70	295361	0	0	0
T189	0	32	0	0
T218	0	33	0	0
T219	0	10	0	0
T220	0	8	0	0
T221	0	35	0	0
T222	0	35	0	0
T223	0	28	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1778	0	0
T9	417014	26	0	0
T10	314959	0	0	0
T11	454221	0	0	0
T12	118063	0	0	0
T14	870191	0	0	0
T15	319089	0	0	0
T20	303789	0	0	0
T21	672239	0	0	0
T24	0	9	0	0
T37	30866	0	0	0
T53	0	18	0	0
T70	295361	0	0	0
T189	0	44	0	0
T218	0	35	0	0
T219	0	17	0	0
T220	0	19	0	0
T221	0	42	0	0
T222	0	26	0	0
T223	0	50	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1838	0	0
T9	417014	26	0	0
T10	314959	0	0	0
T11	454221	0	0	0
T12	118063	0	0	0
T14	870191	0	0	0
T15	319089	0	0	0
T20	303789	0	0	0
T21	672239	0	0	0
T24	0	11	0	0
T37	30866	0	0	0
T53	0	14	0	0
T70	295361	0	0	0
T189	0	26	0	0
T218	0	40	0	0
T219	0	14	0	0
T220	0	10	0	0
T221	0	32	0	0
T222	0	31	0	0
T223	0	41	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1813	0	0
T9	417014	20	0	0
T10	314959	0	0	0
T11	454221	0	0	0
T12	118063	0	0	0
T14	870191	0	0	0
T15	319089	0	0	0
T20	303789	0	0	0
T21	672239	0	0	0
T24	0	11	0	0
T37	30866	0	0	0
T53	0	16	0	0
T70	295361	0	0	0
T189	0	34	0	0
T218	0	25	0	0
T219	0	18	0	0
T220	0	7	0	0
T221	0	47	0	0
T222	0	34	0	0
T223	0	28	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1724	0	0
T9	417014	23	0	0
T10	314959	0	0	0
T11	454221	0	0	0
T12	118063	0	0	0
T14	870191	0	0	0
T15	319089	0	0	0
T20	303789	0	0	0
T21	672239	0	0	0
T24	0	31	0	0
T37	30866	0	0	0
T53	0	21	0	0
T70	295361	0	0	0
T189	0	31	0	0
T218	0	23	0	0
T219	0	21	0	0
T220	0	9	0	0
T221	0	49	0	0
T222	0	22	0	0
T223	0	25	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1857	0	0
T9	417014	28	0	0
T10	314959	0	0	0
T11	454221	0	0	0
T12	118063	0	0	0
T14	870191	0	0	0
T15	319089	0	0	0
T20	303789	0	0	0
T21	672239	0	0	0
T24	0	33	0	0
T37	30866	0	0	0
T53	0	30	0	0
T70	295361	0	0	0
T189	0	45	0	0
T218	0	41	0	0
T219	0	21	0	0
T220	0	17	0	0
T221	0	52	0	0
T222	0	25	0	0
T223	0	31	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1813	0	0
T9	417014	34	0	0
T10	314959	0	0	0
T11	454221	0	0	0
T12	118063	0	0	0
T14	870191	0	0	0
T15	319089	0	0	0
T20	303789	0	0	0
T21	672239	0	0	0
T24	0	28	0	0
T37	30866	0	0	0
T53	0	30	0	0
T70	295361	0	0	0
T189	0	32	0	0
T218	0	43	0	0
T219	0	12	0	0
T220	0	19	0	0
T221	0	48	0	0
T222	0	25	0	0
T223	0	56	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1547	0	0
T9	417014	27	0	0
T10	314959	0	0	0
T11	454221	0	0	0
T12	118063	0	0	0
T14	870191	0	0	0
T15	319089	0	0	0
T20	303789	0	0	0
T21	672239	0	0	0
T24	0	36	0	0
T37	30866	0	0	0
T53	0	16	0	0
T70	295361	0	0	0
T189	0	52	0	0
T218	0	42	0	0
T219	0	17	0	0
T220	0	10	0	0
T221	0	47	0	0
T222	0	39	0	0
T223	0	30	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1405	0	0
T9	417014	32	0	0
T10	314959	0	0	0
T11	454221	0	0	0
T12	118063	0	0	0
T14	870191	0	0	0
T15	319089	0	0	0
T20	303789	0	0	0
T21	672239	0	0	0
T24	0	25	0	0
T37	30866	0	0	0
T53	0	20	0	0
T70	295361	0	0	0
T189	0	40	0	0
T218	0	33	0	0
T219	0	22	0	0
T220	0	13	0	0
T221	0	38	0	0
T222	0	13	0	0
T223	0	50	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1384	0	0
T9	417014	32	0	0
T10	314959	0	0	0
T11	454221	0	0	0
T12	118063	0	0	0
T14	870191	0	0	0
T15	319089	0	0	0
T20	303789	0	0	0
T21	672239	0	0	0
T24	0	23	0	0
T37	30866	0	0	0
T53	0	30	0	0
T70	295361	0	0	0
T189	0	46	0	0
T218	0	27	0	0
T219	0	30	0	0
T220	0	5	0	0
T221	0	46	0	0
T222	0	18	0	0
T223	0	53	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1355	0	0
T9	417014	34	0	0
T10	314959	0	0	0
T11	454221	0	0	0
T12	118063	0	0	0
T14	870191	0	0	0
T15	319089	0	0	0
T20	303789	0	0	0
T21	672239	0	0	0
T24	0	30	0	0
T37	30866	0	0	0
T53	0	25	0	0
T70	295361	0	0	0
T189	0	43	0	0
T218	0	32	0	0
T219	0	17	0	0
T220	0	11	0	0
T221	0	55	0	0
T222	0	31	0	0
T223	0	40	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1733	0	0
T9	417014	49	0	0
T10	314959	0	0	0
T11	454221	0	0	0
T12	118063	0	0	0
T14	870191	0	0	0
T15	319089	0	0	0
T20	303789	0	0	0
T21	672239	0	0	0
T24	0	30	0	0
T37	30866	0	0	0
T53	0	25	0	0
T70	295361	0	0	0
T189	0	58	0	0
T218	0	45	0	0
T219	0	18	0	0
T220	0	10	0	0
T221	0	37	0	0
T222	0	31	0	0
T223	0	39	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1178	0	0
T9	417014	14	0	0
T10	314959	0	0	0
T11	454221	0	0	0
T12	118063	0	0	0
T14	870191	0	0	0
T15	319089	0	0	0
T20	303789	0	0	0
T21	672239	0	0	0
T24	0	10	0	0
T37	30866	0	0	0
T53	0	16	0	0
T70	295361	0	0	0
T189	0	31	0	0
T218	0	36	0	0
T219	0	11	0	0
T220	0	12	0	0
T221	0	40	0	0
T222	0	30	0	0
T223	0	29	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1404	0	0
T9	417014	18	0	0
T10	314959	0	0	0
T11	454221	0	0	0
T12	118063	0	0	0
T14	870191	0	0	0
T15	319089	0	0	0
T20	303789	0	0	0
T21	672239	0	0	0
T24	0	16	0	0
T37	30866	0	0	0
T53	0	16	0	0
T70	295361	0	0	0
T189	0	33	0	0
T218	0	57	0	0
T219	0	12	0	0
T220	0	8	0	0
T221	0	38	0	0
T222	0	21	0	0
T223	0	61	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1848	0	0
T9	417014	66	0	0
T10	314959	0	0	0
T11	454221	0	0	0
T12	118063	0	0	0
T14	870191	0	0	0
T15	319089	0	0	0
T20	303789	0	0	0
T21	672239	0	0	0
T24	0	36	0	0
T37	30866	0	0	0
T53	0	32	0	0
T70	295361	0	0	0
T189	0	70	0	0
T218	0	76	0	0
T219	0	36	0	0
T220	0	19	0	0
T221	0	88	0	0
T222	0	29	0	0
T224	0	9	0	0