Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7024	1			T1	15		T2	57		T5	34
testmodes[AdcCtrlTestmodeNormal]	5438	1			T1	12		T2	88		T5	48
testmodes[AdcCtrlTestmodeLowpower]	5620	1			T1	5		T2	62		T3	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3848	1			T1	8		T2	11		T5	11
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1777	1			T1	6		T2	30		T5	16
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1292	1			T1	1		T2	16		T5	6
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1748	1			T1	6		T2	28		T5	14
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1958	1			T1	3		T2	34		T5	17
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1391	1			T1	3		T2	26		T5	17
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1312	1			T1	1		T2	17		T5	8
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1369	1			T1	2		T2	24		T5	15
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2694	1			T1	1		T2	20		T3	2