---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.adc_ctrl_csr_assert.TlulOOBAddrErr_A	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.BusySrcReqChk_A	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.SrcAckBusyChk_A	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	0	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.BusySrcReqChk_A	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.SrcAckBusyChk_A	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	0	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	33777685	0	0	913

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AdcKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.AlertsKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	2147483647	100	0	0
tb.dut.IntrKnown	0	0	2147483647	2147483647	0	0
tb.dut.TlOAReadyKnown	0	0	2147483647	2147483647	0	0
tb.dut.TlODValidKnown	0	0	2147483647	2147483647	0	0
tb.dut.WakeKnown	0	0	2147483647	2147483647	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_0_rd_A	0	0	2147483647	2209	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_1_rd_A	0	0	2147483647	2501	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_2_rd_A	0	0	2147483647	2362	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_3_rd_A	0	0	2147483647	2371	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_4_rd_A	0	0	2147483647	2346	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_5_rd_A	0	0	2147483647	2201	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_6_rd_A	0	0	2147483647	2404	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_7_rd_A	0	0	2147483647	2466	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_0_rd_A	0	0	2147483647	2410	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_1_rd_A	0	0	2147483647	2275	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_2_rd_A	0	0	2147483647	2350	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_3_rd_A	0	0	2147483647	2488	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_4_rd_A	0	0	2147483647	2311	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_5_rd_A	0	0	2147483647	2282	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_6_rd_A	0	0	2147483647	2288	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_7_rd_A	0	0	2147483647	2413	0	0
tb.dut.adc_ctrl_csr_assert.adc_en_ctl_rd_A	0	0	2147483647	1888	0	0
tb.dut.adc_ctrl_csr_assert.adc_fsm_rst_rd_A	0	0	2147483647	1664	0	0
tb.dut.adc_ctrl_csr_assert.adc_intr_ctl_rd_A	0	0	2147483647	2253	0	0
tb.dut.adc_ctrl_csr_assert.adc_lp_sample_ctl_rd_A	0	0	2147483647	1765	0	0
tb.dut.adc_ctrl_csr_assert.adc_pd_ctl_rd_A	0	0	2147483647	2070	0	0
tb.dut.adc_ctrl_csr_assert.adc_sample_ctl_rd_A	0	0	2147483647	1880	0	0
tb.dut.adc_ctrl_csr_assert.adc_wakeup_ctl_rd_A	0	0	2147483647	2040	0	0
tb.dut.adc_ctrl_csr_assert.intr_enable_rd_A	0	0	2147483647	2263	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	2147483647	30094879	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	2147483647	2147483647	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	2147483647	4721835	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	2147483647	2147483647	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[221].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[222].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[223].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[224].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[225].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	2147483647	18803028	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	2147483647	3100	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	2147483647	19354081	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	2147483647	3877413	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	2147483647	2881	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	2147483647	30094982	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	2147483647	4721895	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	2147483647	30094982	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	2147483647	4721895	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	2147483647	4721895	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	2147483647	4721895	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	2147483647	2713	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	2147483647	3242	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	913	913	0	0
tb.dut.u_adc_ctrl_core.MaxFilters_A	0	0	33693994	33384566	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck00_A	0	0	33693994	10116710	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck01_A	0	0	33693994	2569439	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck10_A	0	0	33693994	2692418	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck11_A	0	0	33693994	18005999	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck00_A	0	0	33693994	11823933	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck01_A	0	0	33693994	1823649	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck10_A	0	0	33693994	1350695	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck11_A	0	0	33693994	18386289	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck00_A	0	0	33693994	11928490	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck01_A	0	0	33693994	400557	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck10_A	0	0	33693994	445953	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck11_A	0	0	33693994	20609566	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck00_A	0	0	33693994	12973894	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck01_A	0	0	33693994	307665	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck10_A	0	0	33693994	354189	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck11_A	0	0	33693994	19748818	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck00_A	0	0	33693994	11978565	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck01_A	0	0	33693994	9	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck10_A	0	0	33693994	93	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck11_A	0	0	33693994	21405899	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck00_A	0	0	33693994	12954041	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck01_A	0	0	33693994	12	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck10_A	0	0	33693994	17139	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck11_A	0	0	33693994	20413374	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck00_A	0	0	33693994	12897706	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck01_A	0	0	33693994	32704	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck10_A	0	0	33693994	283139	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck11_A	0	0	33693994	20171017	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck00_A	0	0	33693994	12482659	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck01_A	0	0	33693994	44877	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck10_A	0	0	33693994	186325	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck11_A	0	0	33693994	20670705	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.LpSampleCntCfg_M	0	0	31088250	31009734	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrMisMatch_A	0	0	31088250	160757	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrPwrDn_A	0	0	31088250	92441	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpSampleCntCfg_M	0	0	31088250	31009734	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.FsmDebugOut_A	0	0	31088250	31009734	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.FsmStateHwReset_A	0	0	1111	1111	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.FsmStateSwReset_A	0	0	31088250	6436	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.LpSampleCntHwReset_A	0	0	1111	1111	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.LpSampleCntSwReset_A	0	0	31088250	6436	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.NpSampleCntHwReset_A	0	0	1111	1111	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.NpSampleCntSwReset_A	0	0	31088250	6436	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.PwrupTimerCntHwReset_A	0	0	1111	1111	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.PwrupTimerCntSwReset_A	0	0	31088250	6436	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.WakeupTimerCntHwReset_A	0	0	1111	1111	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.WakeupTimerCntSwReset_A	0	0	31088250	6436	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.i_adc_ctrl_intr_o.IntrTKind_A	0	0	748	748	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync.SyncReqAckAckNeedsReq	0	0	2147483647	17133	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync.SyncReqAckHoldReq	0	0	33693994	17132	0	0
tb.dut.u_adc_ctrl_core.u_oneshot_done_sync.DstPulseCheck_A	0	0	2147483647	6591	0	0
tb.dut.u_adc_ctrl_core.u_oneshot_done_sync.SrcPulseCheck_M	0	0	33693994	6592	0	0
tb.dut.u_reg.en2addrHit	0	0	2147483647	2406003	0	0
tb.dut.u_reg.reAfterRv	0	0	2147483647	2406003	0	0
tb.dut.u_reg.rePulse	0	0	2147483647	2116131	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.BusySrcReqChk_A	0	0	2147483647	1989512	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.SrcAckBusyChk_A	0	0	2147483647	2050	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2050	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	33777685	2050	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	1959	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2060	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.BusySrcReqChk_A	0	0	2147483647	1941023	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.SrcAckBusyChk_A	0	0	2147483647	1994	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1994	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	33777685	1994	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	1903	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2006	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.BusySrcReqChk_A	0	0	2147483647	1871597	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.SrcAckBusyChk_A	0	0	2147483647	1949	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1949	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	33777685	1949	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	1855	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1958	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.BusySrcReqChk_A	0	0	2147483647	1874287	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.SrcAckBusyChk_A	0	0	2147483647	1952	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1952	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	33777685	1952	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	1864	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1962	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.BusySrcReqChk_A	0	0	2147483647	1906978	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.SrcAckBusyChk_A	0	0	2147483647	1977	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1977	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	33777685	1977	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	1887	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1987	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.BusySrcReqChk_A	0	0	2147483647	1906011	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.SrcAckBusyChk_A	0	0	2147483647	1976	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1976	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	33777685	1976	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	1881	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1988	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.BusySrcReqChk_A	0	0	2147483647	1887423	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.SrcAckBusyChk_A	0	0	2147483647	1958	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1958	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	33777685	1958	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	1868	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1966	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.BusySrcReqChk_A	0	0	2147483647	1876353	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.SrcAckBusyChk_A	0	0	2147483647	1981	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1981	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	33777685	1981	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	1888	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1989	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.BusySrcReqChk_A	0	0	2147483647	1961037	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.SrcAckBusyChk_A	0	0	2147483647	2041	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2041	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	33777685	2041	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	1949	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2050	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.BusySrcReqChk_A	0	0	2147483647	1840716	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.SrcAckBusyChk_A	0	0	2147483647	1950	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1950	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	33777685	1950	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	1858	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1960	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.BusySrcReqChk_A	0	0	2147483647	1853404	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.SrcAckBusyChk_A	0	0	2147483647	1958	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1958	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	33777685	1958	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	1867	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1965	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.BusySrcReqChk_A	0	0	2147483647	1828375	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.SrcAckBusyChk_A	0	0	2147483647	1941	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1941	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	33777685	1941	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	1851	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1951	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.BusySrcReqChk_A	0	0	2147483647	1846388	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.SrcAckBusyChk_A	0	0	2147483647	1960	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1960	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	33777685	1960	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	1869	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1973	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.BusySrcReqChk_A	0	0	2147483647	1829257	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.SrcAckBusyChk_A	0	0	2147483647	1946	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1946	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	33777685	1946	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	1857	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1956	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.BusySrcReqChk_A	0	0	2147483647	1905400	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.SrcAckBusyChk_A	0	0	2147483647	1983	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1983	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	33777685	1983	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	1890	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1991	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.BusySrcReqChk_A	0	0	2147483647	1843858	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.SrcAckBusyChk_A	0	0	2147483647	1968	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1968	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	33777685	1968	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	1884	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1979	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	33777685	637048	0	913
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	33777685	637228	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	2147483647	637231	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	33777685	636943	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	33777685	621748	0	913
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	33777685	629515	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	2147483647	629518	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	33777685	619187	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	37796730	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	38255	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	38255	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	33777685	38269	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	38167	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	38303	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.BusySrcReqChk_A	0	0	2147483647	21103810	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.SrcAckBusyChk_A	0	0	2147483647	19779	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	19779	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	33777685	19779	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	19687	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	19790	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.BusySrcReqChk_A	0	0	2147483647	84768	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.SrcAckBusyChk_A	0	0	2147483647	82	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	33777685	3221687	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	2147483647	3221797	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	33777685	1678453	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	77	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	368	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	14649172	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	14090	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	14090	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	33777685	14091	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	13984	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	14131	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	17701608	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	17911	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	17911	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	33777685	17911	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	17823	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	17923	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	14763435	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	14126	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	14126	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	33777685	14127	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	14015	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	14167	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	1423012	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	1452	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1452	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	33777685	1452	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	1359	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1461	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	913	913	0	0
tb.dut.u_reg.u_filter_status_cdc.BusySrcReqChk_A	0	0	2147483647	60639365	0	0
tb.dut.u_reg.u_filter_status_cdc.DstReqKnown_A	0	0	33777685	33433479	0	0
tb.dut.u_reg.u_filter_status_cdc.SrcAckBusyChk_A	0	0	2147483647	66957	0	0
tb.dut.u_reg.u_filter_status_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	33777685	15271	0	913
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	33777685	15347	0	0
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	2147483647	82304	0	0
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	33777685	81380	0	0
tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	33777685	66866	0	0
tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	66969	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	913	913	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	913	913	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	913	913	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	913	913	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	913	913	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	913	913	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	913	913	0	0
tb.dut.u_reg.wePulse	0	0	2147483647	289872	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	33777685	637048	0	913
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	33777685	621748	0	913
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	33777685	0	0	913
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	33777685	15271	0	913

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2147483647	1799151	1799151	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	2147483647	1526	1526	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2147483647	3283	3283	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	2147483647	2031	2031	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2147483647	2835	2835	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	2147483647	1635	1635	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2147483647	801	801	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2147483647	3989	3989	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2147483647	9878	9878	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2147483647	1371611	1371611	845

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2147483647	1799151	1799151	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	2147483647	1526	1526	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2147483647	3283	3283	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	2147483647	2031	2031	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2147483647	2835	2835	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	2147483647	1635	1635	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2147483647	801	801	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2147483647	3989	3989	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2147483647	9878	9878	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2147483647	1371611	1371611	845