| | | | | | | |
tb |
98.83 |
99.10 |
96.68 |
100.00 |
100.00 |
98.88 |
98.33 |
| dut |
98.83 |
99.10 |
96.68 |
100.00 |
100.00 |
98.88 |
98.33 |
| adc_ctrl_csr_assert |
96.00 |
|
|
|
|
|
96.00 |
| gen_alert_tx[0].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
| tlul_assert_device |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
| u_adc_ctrl_core |
99.58 |
99.68 |
99.52 |
|
100.00 |
98.69 |
100.00 |
u_adc_ctrl_fsm |
99.75 |
100.00 |
100.00 |
|
100.00 |
98.73 |
100.00 |
| u_adc_ctrl_fsm_sva |
100.00 |
|
|
|
|
|
100.00 |
| u_adc_ctrl_intr |
96.79 |
98.70 |
91.67 |
|
|
96.77 |
100.00 |
| i_adc_ctrl_intr_o |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| u_match_sync |
93.75 |
100.00 |
75.00 |
|
|
100.00 |
100.00 |
| gen_nrz_hs_protocol.ack_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_nrz_hs_protocol.req_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_oneshot_done_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_reg |
98.02 |
99.04 |
96.09 |
100.00 |
|
98.90 |
96.05 |
| subtree... |
|
|
|
|
|
|
|