Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26731

1

T1

37

T2

207

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20796

1

T1

37

T2

207

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

5935

1

T3

19

T4

47

T7

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20207

1

T1

34

T2

207

T3

8

auto[1]

6524

1

T1

3

T3

23

T4

47

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22404

1

T1

33

T2

207

T3

31

auto[1]

4327

1

T1

4

T6

2

T7

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	8	1			T34	8		-	-		-	-
values[0]	76	1			T132	17		T200	26		T85	4
values[1]	712	1			T101	1		T127	24		T129	9
values[2]	864	1			T40	11		T127	20		T131	1
values[3]	685	1			T1	3		T26	15		T102	3
values[4]	703	1			T136	16		T173	1		T133	1
values[5]	808	1			T3	12		T11	2		T15	11
values[6]	693	1			T3	11		T9	1		T13	7
values[7]	584	1			T9	1		T26	3		T127	21
values[8]	677	1			T3	8		T8	16		T138	12
values[9]	3744	1			T4	47		T6	3		T7	19
minimum	17177	1			T1	34		T2	207		T5	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	971	1			T101	1		T127	44		T131	1
values[1]	3076	1			T1	3		T4	47		T7	19
values[2]	809	1			T102	3		T14	8		T135	11
values[3]	639	1			T11	1		T125	24		T136	16
values[4]	709	1			T3	12		T11	1		T13	7
values[5]	788	1			T3	11		T9	2		T138	14
values[6]	621	1			T8	16		T26	3		T138	12
values[7]	652	1			T3	8		T40	15		T130	6
values[8]	1009	1			T6	3		T11	1		T201	10
values[9]	280	1			T126	27		T70	1		T74	1
minimum	17177	1			T1	34		T2	207		T5	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

4322

1

T1

1

T3

28

T4

44

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T101	1		T127	25		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T132	10		T129	8		T202	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T1	2		T40	11		T125	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1637	1			T4	47		T7	2		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T102	1		T14	3		T126	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T135	7		T34	2		T203	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T136	16		T173	1		T126	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	1		T125	11		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T3	12		T11	1		T13	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T131	1		T33	14		T35	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T9	1		T138	1		T39	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T3	11		T9	1		T132	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T8	12		T26	1		T130	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T138	2		T127	10		T129	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T125	10		T173	14		T139	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	8		T40	15		T130	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T6	3		T201	1		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T11	1		T128	1		T134	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T70	1		T74	1		T204	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T126	10		T205	27		T206	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17036	1			T1	31		T2	207		T5	115
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T127	19		T207	13		T208	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T132	7		T129	1		T200	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T1	1		T125	5		T209	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1084	1			T7	17		T26	14		T210	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T102	2		T14	5		T126	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T135	4		T17	10		T211	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T126	4		T212	2		T144	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T125	13		T137	10		T149	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T13	4		T15	4		T139	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T131	11		T33	13		T35	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T138	13		T35	1		T141	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T132	11		T73	2		T213	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	4		T26	2		T212	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T138	10		T127	11		T129	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T125	14		T139	7		T140	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T132	6		T204	9		T214	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T201	9		T131	4		T135	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T34	2		T16	5		T167	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T204	13		T215	1		T169	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T126	17		T206	9		T28	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	3		T6	2		T32	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T34	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T216	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T132	10		T200	12		T85	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T101	1		T127	14		T207	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T129	8		T202	1		T195	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T40	11		T127	11		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T135	7		T212	3		T217	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	2		T102	1		T14	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T26	1		T40	9		T15	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T136	16		T173	1		T212	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T133	1		T139	7		T218	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	12		T11	1		T15	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T11	1		T131	1		T125	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T13	3		T138	1		T39	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	11		T9	1		T132	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T9	1		T26	1		T130	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T127	10		T129	13		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T8	12		T125	10		T173	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	8		T138	2		T40	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	379	1			T6	3		T201	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1787	1			T4	47		T7	2		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17036	1			T1	31		T2	207		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T34	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T132	7		T200	14		T219	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T127	10		T207	13		T208	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T129	1		T220	3		T221	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T127	9		T209	15		T149	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T135	4		T212	10		T206	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T1	1		T102	2		T14	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T26	14		T15	6		T204	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T212	2		T200	2		T213	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T149	5		T18	1		T222	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T15	4		T126	4		T141	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T131	11		T125	13		T33	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	4		T138	13		T139	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T132	11		T73	2		T35	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T26	2		T223	15		T18	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T127	11		T129	18		T137	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T8	4		T125	14		T139	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T138	10		T132	6		T204	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T201	9		T131	4		T135	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1227	1			T7	17		T210	12		T126	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	3		T6	2		T32	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T101	1		T127	21		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T132	8		T129	2		T202	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	2		T40	1		T125	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1405	1			T4	3		T7	19		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T102	3		T14	6		T126	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T135	5		T34	2		T203	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T136	1		T173	1		T126	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T11	1		T125	14		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	1		T11	1		T13	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T131	12		T33	21		T35	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T9	1		T138	14		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	1		T9	1		T132	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T8	5		T26	3		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T138	12		T127	12		T129	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T125	15		T173	1		T139	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T3	1		T40	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T6	3		T201	10		T131	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T11	1		T128	1		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T70	1		T74	1		T204	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T126	18		T205	1		T206	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17177	1			T1	34		T2	207		T5	115
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T127	23		T208	11		T224	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T132	9		T129	7		T200	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	1		T40	10		T125	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1316	1			T4	44		T25	29		T38	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T14	2		T126	5		T35	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T135	6		T17	7		T211	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T136	15		T126	10		T212	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T125	10		T139	6		T137	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T3	11		T13	2		T15	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T33	6		T35	1		T225	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T39	9		T130	12		T226	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	10		T132	7		T73	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T8	11		T130	6		T212	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T127	9		T129	12		T137	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T125	9		T173	13		T139	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T3	7		T40	14		T130	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T135	1		T140	2		T36	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T134	12		T34	1		T16	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T204	13		T215	1		T227	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T126	9		T205	26		T28	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T34	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T216	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T132	8		T200	15		T85	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T101	1		T127	11		T207	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T129	2		T202	1		T195	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T40	1		T127	10		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T135	5		T212	11		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	2		T102	3		T14	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T26	15		T40	1		T15	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T136	1		T173	1		T212	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T133	1		T139	1		T218	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	1		T11	1		T15	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T11	1		T131	12		T125	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T13	5		T138	14		T39	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	1		T9	1		T132	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T9	1		T26	3		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T127	12		T129	19		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T8	5		T125	15		T173	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	1		T138	12		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	419	1			T6	3		T201	10		T131	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1586	1			T4	3		T7	19		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17177	1			T1	34		T2	207		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T34	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T132	9		T200	11		T85	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T127	13		T208	11		T224	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T129	7		T220	11		T228	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T40	10		T127	10		T209	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T135	6		T212	2		T217	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	1		T14	2		T125	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T40	8		T15	4		T204	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T136	15		T212	11		T200	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T139	6		T18	2		T222	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	11		T15	2		T126	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T125	10		T33	6		T137	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	2		T39	9		T130	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T3	10		T132	7		T73	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T130	6		T205	17		T18	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T127	9		T129	12		T137	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	11		T125	9		T173	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T3	7		T40	14		T132	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T135	1		T204	13		T36	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1428	1			T4	44		T25	29		T38	27

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

auto[0]

4322

1

T1

1

T3

28

T4

44

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26731

1

T1

37

T2

207

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23105

1

T1

34

T2

207

T3

23

auto[ADC_CTRL_FILTER_COND_OUT]

3626

1

T1

3

T3

8

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20117

1

T1

33

T2

202

T3

12

auto[1]

6614

1

T1

4

T2

5

T3

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22404

1

T1

33

T2

207

T3

31

auto[1]

4327

1

T1

4

T6

2

T7

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	470	1			T1	4		T2	5		T5	5
values[0]	53	1			T229	11		T230	1		T231	6
values[1]	840	1			T3	20		T102	3		T39	10
values[2]	3002	1			T4	47		T7	19		T9	1
values[3]	745	1			T8	16		T9	1		T101	1
values[4]	685	1			T6	3		T125	10		T132	19
values[5]	690	1			T3	11		T40	9		T201	10
values[6]	875	1			T138	8		T130	13		T131	12
values[7]	693	1			T1	3		T11	2		T138	4
values[8]	790	1			T11	1		T26	15		T14	8
values[9]	1148	1			T26	3		T40	11		T127	45
minimum	16740	1			T1	30		T2	202		T5	110

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1080	1			T3	20		T102	3		T39	10
values[1]	2958	1			T4	47		T7	19		T8	16
values[2]	787	1			T6	3		T9	1		T101	1
values[3]	574	1			T173	1		T133	1		T70	1
values[4]	922	1			T3	11		T138	8		T40	9
values[5]	608	1			T1	3		T11	1		T127	20
values[6]	879	1			T11	2		T138	4		T14	8
values[7]	721	1			T26	15		T40	11		T127	24
values[8]	831	1			T26	3		T15	23		T173	14
values[9]	193	1			T127	21		T33	27		T129	9
minimum	17178	1			T1	34		T2	207		T5	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

4322

1

T1

1

T3

28

T4

44

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T3	12		T102	1		T130	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T3	8		T39	10		T76	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1647	1			T4	47		T7	2		T8	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T9	1		T125	11		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T6	3		T9	1		T101	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T130	6		T136	16		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T173	1		T133	1		T137	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T70	1		T73	4		T74	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	11		T138	1		T40	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T130	13		T135	2		T125	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T11	1		T127	11		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T1	2		T141	1		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T138	1		T139	9		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T11	2		T14	3		T40	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T127	14		T131	1		T132	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T26	1		T40	11		T233	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T26	1		T173	14		T134	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T15	13		T133	1		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T127	10		T129	8		T212	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T33	14		T36	8		T234	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17037	1			T1	31		T2	207		T5	115
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T102	2		T125	14		T35	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T140	13		T137	8		T149	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1007	1			T7	17		T8	4		T13	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T125	13		T149	9		T235	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T132	18		T126	4		T144	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T223	9		T159	9		T236	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T137	10		T237	11		T222	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T73	2		T211	12		T238	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T138	7		T201	9		T207	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T135	13		T125	5		T139	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T127	9		T131	11		T27	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T1	1		T141	13		T232	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T138	3		T139	7		T35	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T14	5		T131	4		T135	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T127	10		T132	6		T126	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T26	14		T212	15		T149	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T26	2		T16	5		T36	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T15	10		T35	4		T204	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T127	11		T129	1		T212	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T33	13		T36	6		T239	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	3		T6	2		T32	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	457	1			T1	4		T2	5		T5	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T229	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T230	1		T231	1		T240	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T3	12		T102	1		T125	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	8		T39	10		T76	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1674	1			T4	47		T7	2		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T9	1		T125	11		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T8	12		T9	1		T101	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T130	6		T136	16		T71	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	3		T132	8		T137	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T125	5		T133	1		T70	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T3	11		T40	9		T201	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T135	2		T139	1		T73	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T138	1		T131	1		T76	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T130	13		T141	1		T209	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T11	1		T138	1		T127	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	2		T11	1		T40	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T132	7		T139	9		T140	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T11	1		T26	1		T14	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	354	1			T26	1		T127	24		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T40	11		T15	13		T33	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16599	1			T1	27		T2	202		T5	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T129	1		T241	1		T242	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T229	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T231	5		T243	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T102	2		T125	14		T35	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T140	13		T149	5		T142	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1035	1			T7	17		T13	4		T210	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T125	13		T137	8		T149	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T8	4		T132	7		T126	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T236	7		T244	13		T245	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T132	11		T137	10		T222	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T125	5		T223	9		T211	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T201	9		T207	13		T237	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T135	13		T139	1		T73	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T138	7		T131	11		T34	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T141	13		T209	15		T195	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T138	3		T127	9		T126	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	1		T135	4		T204	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T132	6		T139	7		T140	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T26	14		T14	5		T131	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T26	2		T127	21		T212	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T15	10		T33	13		T35	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	3		T6	2		T32	4