Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26731

1

T1

37

T2

207

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23050

1

T1

34

T2

207

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3681

1

T1

3

T3

20

T6

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20371

1

T1

34

T2

207

T3

31

auto[1]

6360

1

T1

3

T4

47

T7

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22404

1

T1

33

T2

207

T3

31

auto[1]

4327

1

T1

4

T6

2

T7

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	374	1			T3	11		T138	14		T14	8
values[0]	28	1			T203	1		T276	1		T275	1
values[1]	737	1			T3	8		T6	3		T101	1
values[2]	726	1			T8	16		T11	1		T127	20
values[3]	534	1			T3	12		T13	7		T40	11
values[4]	3178	1			T4	47		T7	19		T12	1
values[5]	750	1			T9	1		T127	21		T125	24
values[6]	487	1			T39	10		T126	7		T128	1
values[7]	778	1			T11	1		T102	3		T15	11
values[8]	817	1			T1	3		T11	1		T138	8
values[9]	1145	1			T9	1		T26	18		T138	4
minimum	17177	1			T1	34		T2	207		T5	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	702	1			T3	8		T6	3		T101	1
values[1]	738	1			T8	16		T11	1		T127	20
values[2]	557	1			T3	12		T13	7		T40	20
values[3]	3112	1			T4	47		T7	19		T12	1
values[4]	730	1			T9	1		T127	21		T125	24
values[5]	580	1			T39	10		T15	11		T126	7
values[6]	735	1			T11	2		T102	3		T130	19
values[7]	813	1			T1	3		T26	18		T138	8
values[8]	1135	1			T3	11		T9	1		T138	18
values[9]	198	1			T14	8		T131	1		T73	6
minimum	17431	1			T1	34		T2	207		T5	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

4322

1

T1

1

T3

28

T4

44

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T101	1		T139	1		T35	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T3	8		T6	3		T201	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	1		T127	11		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	12		T27	1		T18	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T132	8		T133	1		T208	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T3	12		T13	3		T40	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1670	1			T4	47		T7	2		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T128	1		T129	13		T74	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T9	1		T127	10		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T125	11		T132	10		T134	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T76	1		T226	16		T204	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T39	10		T15	7		T126	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T11	1		T130	6		T135	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T11	1		T102	1		T130	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T26	2		T138	1		T127	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	2		T130	7		T132	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T3	11		T138	2		T40	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T9	1		T15	6		T136	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T73	4		T270	11		T271	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T14	3		T131	1		T224	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17109	1			T1	31		T2	207		T5	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T173	1		T212	3		T203	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T139	1		T35	1		T140	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T201	9		T131	11		T125	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T127	9		T195	2		T206	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	4		T27	10		T18	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T132	11		T208	14		T144	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	4		T131	4		T207	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1049	1			T7	17		T210	12		T272	37
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T129	18		T35	3		T204	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T127	11		T167	12		T204	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T125	13		T132	7		T213	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T204	9		T36	6		T178	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T15	4		T126	1		T222	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T135	4		T126	4		T248	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T102	2		T35	4		T237	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T26	16		T138	7		T127	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T1	1		T132	6		T149	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T138	16		T135	13		T140	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T15	6		T139	7		T141	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T73	2		T270	15		T271	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T14	5		T159	9		T245	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	3		T6	2		T32	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T212	10		T301	6		T147	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T3	11		T138	1		T226	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T14	3		T136	16		T224	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T275	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T203	1		T276	1		T278	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T101	1		T125	5		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T3	8		T6	3		T201	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T11	1		T127	11		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	12		T125	10		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T132	8		T208	12		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T3	12		T13	3		T40	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1623	1			T4	47		T7	2		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T40	9		T131	1		T129	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T9	1		T127	10		T71	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T125	11		T132	10		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T128	1		T76	1		T226	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T39	10		T126	6		T205	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	1		T130	6		T135	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T102	1		T15	7		T130	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T138	1		T127	14		T129	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	2		T11	1		T130	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T26	2		T138	1		T40	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T9	1		T15	6		T131	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17036	1			T1	31		T2	207		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T138	13		T29	9		T267	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T14	5		T159	9		T296	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T278	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T125	5		T139	1		T140	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T201	9		T131	11		T33	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T127	9		T35	1		T200	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T8	4		T125	14		T27	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T132	11		T208	14		T144	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T13	4		T207	13		T280	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1038	1			T7	17		T210	12		T272	37
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T131	4		T129	18		T137	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T127	11		T212	2		T167	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T125	13		T132	7		T35	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T214	16		T178	6		T273	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T126	1		T17	10		T222	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T135	4		T126	4		T204	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T102	2		T15	4		T35	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T138	7		T127	10		T129	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T1	1		T149	5		T223	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T26	16		T138	3		T135	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T15	6		T132	6		T139	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	3		T6	2		T32	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T101	1		T139	2		T35	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T3	1		T6	3		T201	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	1		T127	10		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T8	5		T27	11		T18	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T132	12		T133	1		T208	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T3	1		T13	5		T40	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T4	3		T7	19		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T128	1		T129	19		T74	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T9	1		T127	12		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T125	14		T132	8		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T76	1		T226	1		T204	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T39	1		T15	9		T126	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	1		T130	1		T135	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	1		T102	3		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T26	18		T138	8		T127	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	2		T130	1		T132	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T3	1		T138	18		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T9	1		T15	8		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T73	3		T270	16		T271	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T14	6		T131	1		T224	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17265	1			T1	34		T2	207		T5	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T173	1		T212	11		T203	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T140	2		T279	1		T200	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	7		T125	9		T33	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T127	10		T225	8		T262	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T8	11		T18	5		T258	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T132	7		T208	11		T200	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	11		T13	2		T40	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T4	44		T25	29		T38	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T129	12		T35	1		T225	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T127	9		T167	13		T204	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T125	10		T132	9		T134	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T226	15		T204	8		T36	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T39	9		T15	2		T126	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T130	5		T135	6		T126	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T130	12		T35	10		T222	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T127	13		T126	9		T129	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T1	1		T130	6		T132	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T3	10		T40	14		T135	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T15	4		T136	15		T134	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T73	3		T270	10		T271	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T14	2		T224	14		T159	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T125	4		T222	13		T258	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T212	2		T292	16		T302	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T3	1		T138	14		T226	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T14	6		T136	1		T224	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T275	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T203	1		T276	1		T278	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T101	1		T125	6		T139	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	1		T6	3		T201	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T11	1		T127	10		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T8	5		T125	15		T27	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T132	12		T208	15		T144	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	1		T13	5		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1364	1			T4	3		T7	19		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T40	1		T131	5		T129	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	1		T127	12		T71	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T125	14		T132	8		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T128	1		T76	1		T226	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T39	1		T126	2		T205	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T11	1		T130	1		T135	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T102	3		T15	9		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T138	8		T127	11		T129	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	2		T11	1		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T26	18		T138	4		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T9	1		T15	8		T131	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17177	1			T1	34		T2	207		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T3	10		T226	8		T29	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T14	2		T136	15		T224	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T278	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T125	4		T140	2		T279	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	7		T33	6		T212	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T127	10		T225	8		T200	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T8	11		T125	9		T18	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T132	7		T208	11		T200	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T3	11		T13	2		T40	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T4	44		T25	29		T38	27
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T40	8		T129	12		T137	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T127	9		T212	11		T167	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T125	10		T132	9		T134	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T226	15		T214	12		T178	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T39	9		T126	5		T205	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T130	5		T135	6		T126	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T15	2		T130	12		T35	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T127	13		T129	7		T140	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	1		T130	6		T139	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T40	14		T135	1		T173	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T15	4		T132	6		T134	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

auto[0]

4322

1

T1

1

T3

28

T4

44