Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26731

1

T1

37

T2

207

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20769

1

T1

37

T2

207

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

5962

1

T3

19

T4

47

T7

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20106

1

T1

34

T2

207

T3

8

auto[1]

6625

1

T1

3

T3

23

T4

47

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22404

1

T1

33

T2

207

T3

31

auto[1]

4327

1

T1

4

T6

2

T7

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	339	1			T6	3		T131	5		T126	27
values[0]	44	1			T132	17		T200	26		T216	1
values[1]	734	1			T101	1		T127	24		T129	9
values[2]	833	1			T40	11		T127	20		T131	1
values[3]	748	1			T1	3		T26	15		T102	3
values[4]	674	1			T14	8		T136	16		T173	1
values[5]	783	1			T3	12		T11	2		T15	11
values[6]	784	1			T3	11		T9	1		T13	7
values[7]	554	1			T8	16		T9	1		T26	3
values[8]	651	1			T3	8		T138	12		T40	15
values[9]	3410	1			T4	47		T7	19		T11	1
minimum	17177	1			T1	34		T2	207		T5	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	662	1			T101	1		T127	44		T131	1
values[1]	3231	1			T1	3		T4	47		T7	19
values[2]	693	1			T102	3		T14	8		T126	7
values[3]	627	1			T3	12		T11	1		T136	16
values[4]	809	1			T11	1		T13	7		T15	11
values[5]	673	1			T3	11		T9	2		T138	14
values[6]	655	1			T8	16		T26	3		T127	21
values[7]	657	1			T3	8		T138	12		T40	15
values[8]	1153	1			T6	3		T11	1		T201	10
values[9]	127	1			T70	1		T74	1		T205	27
minimum	17444	1			T1	34		T2	207		T5	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

4322

1

T1

1

T3

28

T4

44

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T101	1		T127	25		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T129	8		T195	1		T220	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T1	2		T40	11		T125	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1708	1			T4	47		T7	2		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T102	1		T14	3		T126	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T34	2		T203	1		T226	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T3	12		T136	16		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	1		T133	1		T139	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T11	1		T13	3		T15	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T131	1		T125	11		T33	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T9	1		T138	1		T39	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	11		T9	1		T132	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	12		T26	1		T130	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T127	10		T129	13		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T125	10		T173	14		T139	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	8		T138	2		T40	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T6	3		T201	1		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T11	1		T126	10		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T70	1		T74	1		T169	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T205	27		T28	14		T303	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17108	1			T1	31		T2	207		T5	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T132	10		T202	1		T200	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T127	19		T207	13		T223	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T129	1		T220	3		T300	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	1		T125	5		T35	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1159	1			T7	17		T26	14		T210	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T102	2		T14	5		T126	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T17	10		T211	16		T174	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T212	2		T144	7		T200	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T137	10		T149	17		T18	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	4		T15	4		T126	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T131	11		T125	13		T33	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T138	13		T35	1		T141	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T132	11		T73	2		T213	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T8	4		T26	2		T212	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T127	11		T129	18		T137	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T125	14		T139	7		T140	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T138	10		T132	6		T204	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T201	9		T131	4		T135	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T126	17		T34	2		T16	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T169	20		T304	5		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T28	3		T305	16		T306	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	3		T6	2		T32	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T132	7		T200	14		T221	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T6	3		T131	1		T70	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T126	10		T34	6		T85	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T216	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T132	10		T200	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T101	1		T127	14		T207	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T129	8		T202	1		T195	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T40	11		T127	11		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T135	7		T212	3		T217	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	2		T102	1		T125	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T26	1		T40	9		T15	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T14	3		T136	16		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T133	1		T139	7		T137	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	12		T11	1		T15	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	1		T131	1		T125	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	3		T138	1		T39	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	11		T9	1		T132	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T8	12		T9	1		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T127	10		T129	13		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T125	10		T173	14		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	8		T138	2		T40	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T201	1		T135	2		T140	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1695	1			T4	47		T7	2		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17036	1			T1	31		T2	207		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T131	4		T141	13		T247	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T126	17		T34	2		T244	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T132	7		T200	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T127	10		T207	13		T208	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T129	1		T220	3		T221	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T127	9		T209	15		T149	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T135	4		T212	10		T159	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T1	1		T102	2		T125	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T26	14		T15	6		T204	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T14	5		T212	2		T200	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T137	10		T149	5		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	4		T126	4		T141	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T131	11		T125	13		T33	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	4		T138	13		T139	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T132	11		T73	2		T35	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T8	4		T26	2		T223	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T127	11		T129	18		T137	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T125	14		T139	7		T212	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T138	10		T132	6		T204	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T201	9		T135	13		T140	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1144	1			T7	17		T210	12		T272	37
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	3		T6	2		T32	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T101	1		T127	21		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T129	2		T195	1		T220	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T1	2		T40	1		T125	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1484	1			T4	3		T7	19		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T102	3		T14	6		T126	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T34	2		T203	1		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	1		T136	1		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	1		T133	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	1		T13	5		T15	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T131	12		T125	14		T33	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T9	1		T138	14		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	1		T9	1		T132	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	5		T26	3		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T127	12		T129	19		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T125	15		T173	1		T139	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T3	1		T138	12		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T6	3		T201	10		T131	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T11	1		T126	18		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T70	1		T74	1		T169	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T205	1		T28	4		T303	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17244	1			T1	34		T2	207		T5	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T132	8		T202	1		T200	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T127	23		T224	2		T255	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T129	7		T220	11		T228	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T1	1		T40	10		T125	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1383	1			T4	44		T25	29		T38	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T14	2		T126	5		T222	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T226	15		T17	7		T211	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	11		T136	15		T212	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T139	6		T137	11		T18	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	2		T15	2		T126	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T125	10		T33	6		T35	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T39	9		T130	12		T226	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T3	10		T132	7		T73	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T8	11		T130	6		T212	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T127	9		T129	12		T137	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T125	9		T173	13		T139	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T3	7		T40	14		T130	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T135	1		T204	13		T36	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T126	9		T134	12		T34	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T169	13		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T205	26		T28	13		T305	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T208	11		T37	6		T280	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T132	9		T200	11		T85	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T6	3		T131	5		T70	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T126	18		T34	7		T85	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T216	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T132	8		T200	15		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T101	1		T127	11		T207	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T129	2		T202	1		T195	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T40	1		T127	10		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T135	5		T212	11		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	2		T102	3		T125	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T26	15		T40	1		T15	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T14	6		T136	1		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T133	1		T139	1		T137	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	1		T11	1		T15	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T11	1		T131	12		T125	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T13	5		T138	14		T39	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T3	1		T9	1		T132	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T8	5		T9	1		T26	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T127	12		T129	19		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T125	15		T173	1		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T3	1		T138	12		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T201	10		T135	14		T140	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1484	1			T4	3		T7	19		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17177	1			T1	34		T2	207		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T262	1		T246	11		T247	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T126	9		T34	1		T85	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T132	9		T200	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T127	13		T208	11		T224	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T129	7		T220	11		T85	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T40	10		T127	10		T209	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T135	6		T212	2		T217	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T125	4		T126	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T40	8		T15	4		T226	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T14	2		T136	15		T212	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T139	6		T137	11		T18	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	11		T15	2		T126	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T125	10		T33	6		T225	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	2		T39	9		T130	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	10		T132	7		T73	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T8	11		T130	6		T205	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T127	9		T129	12		T137	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T125	9		T173	13		T139	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T3	7		T40	14		T132	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T135	1		T140	2		T204	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1355	1			T4	44		T25	29		T38	27

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

auto[0]

4322

1

T1

1

T3

28

T4

44