Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26731

1

T1

37

T2

207

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23293

1

T1

34

T2

207

T3

31

auto[ADC_CTRL_FILTER_COND_OUT]

3438

1

T1

3

T9

2

T11

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20788

1

T1

37

T2

207

T3

31

auto[1]

5943

1

T4

47

T7

19

T8

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22404

1

T1

33

T2

207

T3

31

auto[1]

4327

1

T1

4

T6

2

T7

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	237	1			T6	3		T11	1		T26	15
values[0]	32	1			T70	1		T186	5		T307	1
values[1]	676	1			T11	1		T127	44		T135	11
values[2]	763	1			T8	16		T101	1		T138	14
values[3]	673	1			T1	3		T9	1		T201	10
values[4]	598	1			T26	3		T138	4		T40	11
values[5]	3089	1			T4	47		T7	19		T9	1
values[6]	979	1			T3	11		T13	7		T15	12
values[7]	804	1			T40	9		T130	7		T125	24
values[8]	698	1			T3	12		T11	1		T102	3
values[9]	1005	1			T3	8		T40	15		T125	24
minimum	17177	1			T1	34		T2	207		T5	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	591	1			T11	1		T127	24		T135	11
values[1]	877	1			T1	3		T8	16		T101	1
values[2]	575	1			T9	1		T201	10		T131	1
values[3]	3001	1			T4	47		T7	19		T9	1
values[4]	796	1			T39	10		T14	8		T15	11
values[5]	916	1			T3	11		T15	12		T130	7
values[6]	858	1			T3	12		T13	7		T40	9
values[7]	609	1			T11	1		T102	3		T131	5
values[8]	953	1			T3	8		T6	3		T11	1
values[9]	149	1			T127	21		T133	1		T248	12
minimum	17406	1			T1	34		T2	207		T5	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

4322

1

T1

1

T3

28

T4

44

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T127	14		T135	7		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T11	1		T133	1		T134	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T8	12		T101	1		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T1	2		T138	1		T130	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T201	1		T131	1		T173	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T9	1		T133	1		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1583	1			T4	47		T7	2		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T9	1		T132	7		T35	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T131	1		T33	14		T218	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T39	10		T14	3		T15	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T3	11		T15	6		T130	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T132	10		T205	18		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T3	12		T134	6		T129	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	3		T40	9		T130	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T102	1		T136	16		T126	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T11	1		T131	1		T70	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	8		T6	3		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T26	1		T138	1		T125	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T133	1		T264	14		T266	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T127	10		T248	3		T308	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17097	1			T1	31		T2	207		T5	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T127	11		T309	1		T222	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T127	10		T135	4		T139	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T208	14		T223	9		T195	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T8	4		T212	13		T16	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	1		T138	13		T125	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T201	9		T140	2		T222	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T207	13		T137	8		T232	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1005	1			T7	17		T26	2		T210	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T132	6		T35	1		T137	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T131	11		T33	13		T18	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T14	5		T15	4		T135	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T15	6		T34	2		T214	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T132	7		T285	5		T232	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T129	1		T73	2		T237	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	4		T125	14		T255	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T102	2		T126	1		T139	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T131	4		T141	13		T37	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T126	17		T141	12		T200	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T26	14		T138	7		T125	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T264	14		T263	9		T281	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T127	11		T248	9		T163	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	3		T6	2		T32	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T127	9		T222	2		T241	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T6	3		T11	1		T264	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T26	1		T138	1		T127	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T70	1		T186	1		T100	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T307	1		T267	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T127	14		T135	7		T126	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T11	1		T127	11		T208	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T8	12		T101	1		T76	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T138	1		T130	13		T132	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T201	1		T173	14		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T1	2		T9	1		T125	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T26	1		T138	1		T40	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T132	7		T133	1		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1654	1			T4	47		T7	2		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T9	1		T39	10		T14	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T3	11		T15	6		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T13	3		T139	7		T35	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T130	7		T134	6		T73	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T40	9		T125	10		T132	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	12		T102	1		T126	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T11	1		T130	6		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T3	8		T40	15		T136	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T125	11		T34	2		T35	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17036	1			T1	31		T2	207		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T264	14		T260	2		T310	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T26	14		T138	7		T127	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T186	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T267	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T127	10		T135	4		T126	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T127	9		T208	14		T223	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	4		T212	13		T16	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T138	13		T132	11		T248	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T201	9		T140	2		T17	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T1	1		T125	5		T207	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T26	2		T138	3		T200	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T132	6		T35	1		T142	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1056	1			T7	17		T210	12		T131	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T14	5		T15	4		T135	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T15	6		T34	2		T214	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	4		T35	4		T285	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T73	2		T237	11		T236	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T125	14		T132	7		T255	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T102	2		T126	1		T139	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T131	4		T141	13		T220	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T126	17		T141	18		T178	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T125	13		T35	3		T167	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	3		T6	2		T32	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T127	11		T135	5		T139	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	1		T133	1		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T8	5		T101	1		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T1	2		T138	14		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T201	10		T131	1		T173	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T9	1		T133	1		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T4	3		T7	19		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T9	1		T132	7		T35	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T131	12		T33	21		T218	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T39	1		T14	6		T15	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T3	1		T15	8		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T132	8		T205	1		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T3	1		T134	1		T129	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T13	5		T40	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T102	3		T136	1		T126	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T11	1		T131	5		T70	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T3	1		T6	3		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T26	15		T138	8		T125	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T133	1		T264	15		T266	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T127	12		T248	10		T308	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17268	1			T1	34		T2	207		T5	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T127	10		T309	1		T222	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T127	13		T135	6		T36	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T134	12		T205	26		T208	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T8	11		T212	17		T16	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T1	1		T130	12		T125	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T173	13		T140	2		T222	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T137	1		T217	14		T28	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T4	44		T25	29		T38	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T132	6		T137	14		T246	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T33	6		T18	5		T211	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T39	9		T14	2		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	10		T15	4		T130	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T132	9		T205	17		T285	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T3	11		T134	5		T129	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T13	2		T40	8		T130	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T136	15		T126	5		T139	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T37	6		T174	12		T99	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	7		T40	14		T126	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T125	10		T35	1		T167	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T264	13		T311	23		T281	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T127	9		T248	2		T308	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T126	10		T212	2		T36	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T127	10		T222	13		T241	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T6	3		T11	1		T264	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T26	15		T138	8		T127	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T70	1		T186	5		T100	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T307	1		T267	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T127	11		T135	5		T126	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	1		T127	10		T208	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T8	5		T101	1		T76	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T138	14		T130	1		T132	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T201	10		T173	1		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T1	2		T9	1		T125	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T26	3		T138	4		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T132	7		T133	1		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1384	1			T4	3		T7	19		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	1		T39	1		T14	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T3	1		T15	8		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	5		T139	1		T35	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T130	1		T134	1		T73	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T40	1		T125	15		T132	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T3	1		T102	3		T126	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T11	1		T130	1		T131	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T3	1		T40	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T125	14		T34	2		T35	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17177	1			T1	34		T2	207		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T264	13		T312	4		T260	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T127	9		T77	3		T308	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T267	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T127	13		T135	6		T126	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T127	10		T208	11		T195	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T8	11		T212	17		T16	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T130	12		T132	7		T134	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T173	13		T140	2		T17	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T1	1		T125	4		T137	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T40	10		T200	11		T222	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T132	6		T217	14		T246	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T4	44		T25	29		T38	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T39	9		T14	2		T15	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T3	10		T15	4		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T13	2		T139	6		T35	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T130	6		T134	5		T73	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T40	8		T125	9		T132	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	11		T126	5		T139	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T130	5		T220	8		T174	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	7		T40	14		T136	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T125	10		T35	1		T167	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

auto[0]

4322

1

T1

1

T3

28

T4

44