Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26731

1

T1

37

T2

207

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22903

1

T1

34

T2

207

T3

19

auto[ADC_CTRL_FILTER_COND_OUT]

3828

1

T1

3

T3

12

T6

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20194

1

T1

34

T2

207

T3

19

auto[1]

6537

1

T1

3

T3

12

T4

47

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22404

1

T1

33

T2

207

T3

31

auto[1]

4327

1

T1

4

T6

2

T7

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	356	1			T233	1		T35	1		T212	13
values[0]	39	1			T162	9		T299	27		T284	3
values[1]	787	1			T26	15		T102	3		T40	11
values[2]	714	1			T127	21		T136	16		T33	27
values[3]	799	1			T9	1		T138	4		T130	6
values[4]	502	1			T138	8		T40	9		T135	11
values[5]	566	1			T15	11		T125	10		T71	1
values[6]	742	1			T3	11		T9	1		T11	1
values[7]	731	1			T3	8		T11	2		T125	24
values[8]	849	1			T8	16		T26	3		T13	7
values[9]	3469	1			T1	3		T3	12		T4	47
minimum	17177	1			T1	34		T2	207		T5	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	679	1			T26	15		T40	11		T127	21
values[1]	732	1			T130	6		T136	16		T133	1
values[2]	774	1			T9	1		T138	12		T131	12
values[3]	548	1			T40	9		T15	11		T135	11
values[4]	557	1			T9	1		T39	10		T15	12
values[5]	723	1			T3	11		T11	1		T101	1
values[6]	3162	1			T3	8		T4	47		T7	19
values[7]	766	1			T8	16		T13	7		T40	15
values[8]	1156	1			T1	3		T3	12		T6	3
values[9]	145	1			T222	45		T220	12		T228	12
minimum	17489	1			T1	34		T2	207		T5	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

4322

1

T1

1

T3

28

T4

44

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T26	1		T40	11		T33	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T127	10		T130	13		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T133	1		T129	8		T140	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T130	6		T136	16		T129	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T9	1		T138	2		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T212	18		T203	1		T205	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T132	7		T126	10		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T40	9		T15	7		T135	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T9	1		T15	6		T125	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T39	10		T71	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	11		T11	1		T139	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T101	1		T131	1		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1616	1			T3	8		T4	47		T7	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T11	1		T125	11		T132	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	3		T131	1		T207	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T8	12		T40	15		T127	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	365	1			T127	14		T201	1		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T1	2		T3	12		T6	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T228	12		T31	1		T162	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T222	25		T220	9		T259	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17138	1			T1	31		T2	207		T5	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T134	13		T137	15		T203	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T26	14		T33	13		T36	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T127	11		T16	5		T36	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T129	1		T140	13		T204	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T129	18		T35	3		T204	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T138	10		T131	11		T132	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T212	13		T208	14		T223	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T132	6		T126	17		T212	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T15	4		T135	4		T126	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T15	6		T125	5		T137	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T144	7		T213	15		T206	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T139	7		T34	2		T35	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T285	5		T206	9		T29	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1022	1			T7	17		T26	2		T210	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T125	13		T132	11		T237	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T13	4		T131	4		T207	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T8	4		T127	9		T125	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T127	10		T201	9		T141	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T1	1		T135	13		T126	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T257	3		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T222	20		T220	3		T259	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T1	3		T6	2		T32	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T137	14		T241	9		T265	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T35	1		T141	1		T167	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T233	1		T212	3		T211	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T162	9		T284	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T299	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T26	1		T102	1		T40	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T130	13		T134	13		T16	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T33	14		T133	1		T129	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T127	10		T136	16		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	1		T138	1		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T130	6		T212	18		T203	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T138	1		T132	7		T126	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T40	9		T135	7		T126	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T125	5		T214	13		T178	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T15	7		T71	1		T225	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	11		T9	1		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T101	1		T39	10		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T3	8		T11	1		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T11	1		T125	11		T173	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T26	1		T13	3		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T8	12		T40	15		T127	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1714	1			T4	47		T7	2		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T1	2		T3	12		T6	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17036	1			T1	31		T2	207		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T141	6		T167	12		T247	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T212	10		T211	16		T316	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T284	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T299	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T26	14		T102	2		T204	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T16	5		T137	14		T241	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T33	13		T129	1		T140	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T127	11		T129	18		T35	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T138	3		T131	11		T132	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T212	13		T208	14		T223	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T138	7		T132	6		T126	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T135	4		T126	1		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T125	5		T214	16		T178	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T15	4		T213	15		T249	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	6		T139	7		T34	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T144	7		T206	24		T29	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T35	1		T140	2		T186	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T125	13		T237	11		T285	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T26	2		T13	4		T138	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T8	4		T127	9		T132	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1147	1			T7	17		T210	12		T127	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T1	1		T135	13		T125	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	3		T6	2		T32	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T26	15		T40	1		T33	21
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T127	12		T130	1		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T133	1		T129	2		T140	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T130	1		T136	1		T129	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T9	1		T138	12		T131	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T212	14		T203	1		T205	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T132	7		T126	18		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T40	1		T15	9		T135	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	1		T15	8		T125	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T39	1		T71	1		T144	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	1		T11	1		T139	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T101	1		T131	1		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1344	1			T3	1		T4	3		T7	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T11	1		T125	14		T132	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T13	5		T131	5		T207	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T8	5		T40	1		T127	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	416	1			T127	11		T201	10		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T1	2		T3	1		T6	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T228	1		T31	1		T162	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T222	21		T220	4		T259	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17281	1			T1	34		T2	207		T5	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T134	1		T137	15		T203	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T40	10		T33	6		T36	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T127	9		T130	12		T16	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T129	7		T140	17		T225	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T130	5		T136	15		T129	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T132	9		T35	10		T137	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T212	17		T205	17		T208	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T132	6		T126	9		T212	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T40	8		T15	2		T135	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T15	4		T125	4		T137	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T39	9		T213	12		T249	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T3	10		T139	8		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T285	5		T286	19		T312	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T3	7		T4	44		T25	29
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T125	10		T132	7		T173	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T13	2		T209	12		T200	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	11		T40	14		T127	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T127	13		T167	13		T37	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	1		T3	11		T135	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T228	11		T162	12		T158	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T222	24		T220	8		T259	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T177	4		T168	8		T162	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T134	12		T137	14		T317	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T35	1		T141	7		T167	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T233	1		T212	11		T211	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T162	1		T284	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T299	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T26	15		T102	3		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T130	1		T134	1		T16	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T33	21		T133	1		T129	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T127	12		T136	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T9	1		T138	4		T131	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T130	1		T212	14		T203	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T138	8		T132	7		T126	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T40	1		T135	5		T126	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T125	6		T214	17		T178	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T15	9		T71	1		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	1		T9	1		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T101	1		T39	1		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	1		T11	1		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T11	1		T125	14		T173	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T26	3		T13	5		T138	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T8	5		T40	1		T127	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1484	1			T4	3		T7	19		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T1	2		T3	1		T6	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17177	1			T1	34		T2	207		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T167	13		T247	14		T268	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T212	2		T211	13		T227	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T162	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T299	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T40	10		T204	9		T36	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T130	12		T134	12		T16	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T33	6		T129	7		T140	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T127	9		T136	15		T129	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T132	9		T35	10		T225	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T130	5		T212	17		T208	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T132	6		T126	9		T212	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T40	8		T135	6		T126	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T125	4		T214	12		T178	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T15	2		T225	10		T213	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T3	10		T15	4		T139	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T39	9		T312	19		T29	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	7		T140	2		T226	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T125	10		T173	13		T285	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T13	2		T14	2		T130	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	11		T40	14		T127	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T4	44		T25	29		T38	27
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T1	1		T3	11		T135	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

auto[0]

4322

1

T1

1

T3

28

T4

44