Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26731

1

T1

37

T2

207

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23321

1

T1

34

T2

207

T3

8

auto[ADC_CTRL_FILTER_COND_OUT]

3410

1

T1

3

T3

23

T6

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20706

1

T1

37

T2

207

T3

19

auto[1]

6025

1

T3

12

T4

47

T7

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22404

1

T1

33

T2

207

T3

31

auto[1]

4327

1

T1

4

T6

2

T7

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	208	1			T14	8		T141	7		T36	14
values[0]	65	1			T140	5		T253	5		T318	12
values[1]	881	1			T11	1		T40	26		T127	20
values[2]	876	1			T3	8		T8	16		T9	1
values[3]	1006	1			T26	15		T138	4		T39	10
values[4]	605	1			T1	3		T11	1		T132	17
values[5]	595	1			T15	12		T33	27		T207	14
values[6]	729	1			T6	3		T125	10		T132	19
values[7]	604	1			T3	11		T9	1		T101	1
values[8]	3160	1			T3	12		T4	47		T7	19
values[9]	825	1			T26	3		T138	22		T127	21
minimum	17177	1			T1	34		T2	207		T5	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	993	1			T11	1		T127	20		T130	13
values[1]	820	1			T3	8		T8	16		T9	1
values[2]	856	1			T138	4		T39	10		T15	11
values[3]	646	1			T1	3		T11	1		T15	12
values[4]	522	1			T6	3		T132	17		T126	27
values[5]	790	1			T40	9		T131	5		T125	10
values[6]	2981	1			T3	11		T4	47		T7	19
values[7]	752	1			T3	12		T26	3		T135	11
values[8]	816	1			T138	22		T14	8		T127	21
values[9]	88	1			T239	31		T98	11		T319	5
minimum	17467	1			T1	34		T2	207		T5	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

4322

1

T1

1

T3

28

T4

44

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T130	7		T74	1		T233	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T11	1		T127	11		T130	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T3	8		T8	12		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	3		T102	1		T127	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T39	10		T201	1		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T138	1		T15	7		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T15	6		T129	13		T34	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	2		T11	1		T139	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T126	10		T74	1		T76	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T6	3		T132	10		T33	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T131	1		T125	5		T132	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T40	9		T133	1		T212	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1598	1			T4	47		T7	2		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	11		T9	1		T130	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T173	14		T209	13		T137	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	12		T26	1		T135	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T138	1		T14	3		T134	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T138	1		T127	10		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T239	14		T98	1		T319	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T254	1		T251	9		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17144	1			T1	31		T2	207		T5	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T40	15		T236	1		T174	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T212	13		T178	6		T144	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T127	9		T35	4		T137	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T8	4		T26	14		T135	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T13	4		T102	2		T127	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T201	9		T131	11		T126	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T138	3		T15	4		T129	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T15	6		T129	18		T34	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T1	1		T35	1		T149	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T126	17		T141	13		T186	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T132	7		T33	13		T207	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T131	4		T125	5		T132	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T212	2		T200	2		T213	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1063	1			T7	17		T210	12		T125	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T200	14		T255	2		T244	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T209	15		T137	8		T208	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T26	2		T135	4		T125	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T138	7		T14	5		T149	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T138	13		T127	11		T35	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T239	17		T98	10		T319	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T251	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T1	3		T6	2		T32	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T236	14		T174	9		T320	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T14	3		T202	1		T236	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T141	1		T36	8		T309	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T140	3		T318	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T253	1		T257	6		T163	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T40	11		T74	1		T233	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T11	1		T40	15		T127	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T3	8		T8	12		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T13	3		T102	1		T130	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T26	1		T39	10		T201	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T138	1		T127	14		T15	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T129	13		T34	6		T137	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	2		T11	1		T132	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T15	6		T76	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T33	14		T207	1		T203	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T125	5		T132	8		T136	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T6	3		T133	1		T212	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T101	1		T131	1		T125	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	11		T9	1		T40	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1689	1			T4	47		T7	2		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	12		T135	7		T139	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T138	1		T134	13		T209	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T26	1		T138	1		T127	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17036	1			T1	31		T2	207		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T14	5		T236	7		T239	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T141	6		T36	6		T222	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T140	2		T318	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T253	4		T257	6		T163	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T212	13		T167	12		T178	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T127	9		T35	4		T137	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T8	4		T135	13		T213	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T13	4		T102	2		T204	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T26	14		T201	9		T131	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T138	3		T127	10		T15	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T129	18		T34	2		T137	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T1	1		T132	7		T35	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T15	6		T141	13		T186	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T33	13		T207	13		T149	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T125	5		T132	11		T126	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T212	2		T200	2		T213	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T131	4		T125	14		T139	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T200	14		T255	2		T248	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1084	1			T7	17		T210	12		T132	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T135	4		T139	7		T212	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T138	7		T209	15		T149	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T26	2		T138	13		T127	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	3		T6	2		T32	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T130	1		T74	1		T233	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T11	1		T127	10		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T3	1		T8	5		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T13	5		T102	3		T127	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T39	1		T201	10		T131	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T138	4		T15	9		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T15	8		T129	19		T34	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	2		T11	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T126	18		T74	1		T76	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T6	3		T132	8		T33	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T131	5		T125	6		T132	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T40	1		T133	1		T212	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1396	1			T4	3		T7	19		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T3	1		T9	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T173	1		T209	16		T137	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	1		T26	3		T135	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T138	8		T14	6		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T138	14		T127	12		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T239	18		T98	11		T319	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T254	1		T251	11		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17274	1			T1	34		T2	207		T5	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T40	1		T236	15		T174	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T130	6		T212	17		T178	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T127	10		T130	5		T35	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	7		T8	11		T135	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	2		T127	13		T226	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T39	9		T126	10		T217	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T15	2		T129	7		T16	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T15	4		T129	12		T34	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	1		T139	6		T258	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T126	9		T186	2		T249	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T132	9		T33	6		T241	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T125	4		T132	7		T136	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T40	8		T212	11		T200	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T4	44		T25	29		T38	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	10		T130	12		T200	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T173	13		T209	12		T137	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	11		T135	6		T125	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T14	2		T134	12		T204	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T127	9		T134	5		T35	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T239	13		T321	20		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T251	8		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T40	10		T140	2		T167	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T40	14		T174	7		T317	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T14	6		T202	1		T236	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T141	7		T36	7		T309	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T140	3		T318	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T253	5		T257	7		T163	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T40	1		T74	1		T233	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T11	1		T40	1		T127	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T3	1		T8	5		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T13	5		T102	3		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T26	15		T39	1		T201	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T138	4		T127	11		T15	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T129	19		T34	7		T137	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	2		T11	1		T132	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T15	8		T76	1		T141	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T33	21		T207	14		T203	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T125	6		T132	12		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	3		T133	1		T212	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T101	1		T131	5		T125	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T3	1		T9	1		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1419	1			T4	3		T7	19		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T3	1		T135	5		T139	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T138	8		T134	1		T209	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T26	3		T138	14		T127	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17177	1			T1	34		T2	207		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T14	2		T239	13		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T36	7		T222	10		T19	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T140	2		T318	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T257	5		T163	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T40	10		T212	17		T167	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T40	14		T127	10		T35	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	7		T8	11		T130	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T13	2		T130	5		T204	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T39	9		T126	15		T217	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T127	13		T15	2		T129	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T129	12		T34	1		T137	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T1	1		T132	9		T139	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T15	4		T186	2		T249	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T33	6		T258	4		T261	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T125	4		T132	7		T136	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T212	11		T200	22		T213	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T125	9		T226	8		T262	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	10		T40	8		T130	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1354	1			T4	44		T25	29		T38	27
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	11		T135	6		T139	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T134	12		T209	12		T204	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T127	9		T125	10		T134	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

auto[0]

4322

1

T1

1

T3

28

T4

44