Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26731

1

T1

37

T2

207

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23020

1

T1

34

T2

207

T4

47

auto[ADC_CTRL_FILTER_COND_OUT]

3711

1

T1

3

T3

31

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20190

1

T1

37

T2

207

T3

20

auto[1]

6541

1

T3

11

T4

47

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22404

1

T1

33

T2

207

T3

31

auto[1]

4327

1

T1

4

T6

2

T7

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	52	1			T129	9		T218	1		T292	17
values[0]	132	1			T125	24		T214	29		T99	14
values[1]	589	1			T26	15		T101	1		T131	1
values[2]	835	1			T1	3		T3	11		T9	1
values[3]	862	1			T8	16		T102	3		T127	21
values[4]	641	1			T138	8		T40	11		T135	11
values[5]	3082	1			T4	47		T7	19		T11	1
values[6]	889	1			T39	10		T201	10		T126	7
values[7]	720	1			T9	1		T130	20		T131	12
values[8]	648	1			T3	12		T11	1		T131	5
values[9]	1104	1			T3	8		T6	3		T11	1
minimum	17177	1			T1	34		T2	207		T5	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	960	1			T1	3		T26	15		T138	14
values[1]	871	1			T3	11		T8	16		T9	1
values[2]	672	1			T102	3		T40	11		T127	21
values[3]	3081	1			T4	47		T7	19		T12	1
values[4]	894	1			T11	1		T201	10		T135	15
values[5]	681	1			T39	10		T130	7		T204	27
values[6]	749	1			T9	1		T130	13		T131	12
values[7]	595	1			T3	20		T11	1		T26	3
values[8]	830	1			T6	3		T11	1		T13	7
values[9]	186	1			T70	1		T218	1		T309	1
minimum	17212	1			T1	34		T2	207		T5	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

4322

1

T1

1

T3

28

T4

44

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T131	1		T132	7		T173	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T1	2		T26	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T8	12		T9	1		T40	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	11		T101	1		T207	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T102	1		T127	10		T15	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T40	11		T74	1		T76	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1658	1			T4	47		T7	2		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T138	1		T136	16		T33	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T11	1		T71	1		T35	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T201	1		T135	2		T126	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T39	10		T130	7		T37	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T204	14		T202	1		T200	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T130	13		T131	1		T132	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T9	1		T141	1		T203	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T131	1		T125	11		T139	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T3	20		T11	1		T26	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T6	3		T11	1		T40	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T13	3		T127	25		T133	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T309	1		T292	7		T295	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T70	1		T218	1		T294	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17049	1			T1	31		T2	207		T5	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T318	3		T322	9		T165	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T132	6		T212	10		T137	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	1		T26	14		T138	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T8	4		T15	6		T129	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T207	13		T149	5		T142	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T102	2		T127	11		T15	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T17	5		T255	6		T248	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1094	1			T7	17		T210	12		T272	37
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T138	7		T33	13		T241	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T35	4		T178	6		T211	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T201	9		T135	13		T126	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T37	8		T144	7		T159	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T204	13		T200	2		T18	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T131	11		T132	18		T141	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T141	12		T208	14		T186	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T131	4		T125	13		T34	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T26	2		T138	3		T14	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T125	5		T149	12		T241	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T13	4		T127	19		T129	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T295	13		T147	2		T177	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T296	3		T291	16		T284	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	3		T6	2		T32	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T318	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T177	5		T323	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T129	8		T218	1		T292	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T214	13		T324	3		T314	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T125	10		T99	9		T318	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T131	1		T132	7		T173	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T26	1		T101	1		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T9	1		T40	9		T15	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	2		T3	11		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T8	12		T102	1		T127	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T74	1		T233	1		T225	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T135	7		T133	1		T70	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T138	1		T40	11		T136	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1623	1			T4	47		T7	2		T11	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T135	2		T126	11		T33	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T39	10		T134	6		T71	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T201	1		T126	6		T204	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T130	20		T131	1		T132	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T9	1		T218	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T131	1		T125	11		T139	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	12		T11	1		T126	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T6	3		T11	1		T40	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T3	8		T26	1		T13	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17036	1			T1	31		T2	207		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T177	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T129	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T214	16		T324	3		T314	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T125	14		T99	5		T318	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T132	6		T212	10		T213	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T26	14		T149	14		T144	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T15	6		T129	18		T137	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T1	1		T138	13		T207	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	4		T102	2		T127	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T195	2		T255	6		T159	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T135	4		T27	10		T222	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T138	7		T17	5		T258	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1070	1			T7	17		T210	12		T272	37
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T135	13		T126	4		T33	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T35	4		T37	8		T178	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T201	9		T126	1		T204	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T131	11		T132	18		T141	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T141	12		T208	14		T200	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T131	4		T125	13		T137	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T126	17		T186	4		T285	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T125	5		T34	2		T141	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T26	2		T13	4		T138	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	3		T6	2		T32	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T131	1		T132	7		T173	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T1	2		T26	15		T138	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T8	5		T9	1		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T3	1		T101	1		T207	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T102	3		T127	12		T15	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T40	1		T74	1		T76	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1428	1			T4	3		T7	19		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T138	8		T136	1		T33	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	1		T71	1		T35	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T201	10		T135	14		T126	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T39	1		T130	1		T37	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T204	14		T202	1		T200	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T130	1		T131	12		T132	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	1		T141	13		T203	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T131	5		T125	14		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	2		T11	1		T26	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T6	3		T11	1		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T13	5		T127	21		T133	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T309	1		T292	1		T295	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T70	1		T218	1		T294	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17178	1			T1	34		T2	207		T5	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T318	10		T322	1		T165	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T132	6		T212	2		T137	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	1		T125	9		T204	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T8	11		T40	8		T15	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	10		T195	1		T28	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T127	9		T15	2		T135	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T40	10		T225	10		T205	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T4	44		T25	29		T38	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T136	15		T33	6		T159	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T35	10		T225	8		T178	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T135	1		T126	15		T73	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T39	9		T130	6		T37	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T204	13		T200	22		T18	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T130	12		T132	16		T134	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T208	11		T224	2		T222	24
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T125	10		T139	6		T34	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	18		T14	2		T126	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T40	14		T125	4		T217	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	2		T127	23		T129	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T292	6		T177	4		T325	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T297	8		T291	13		T257	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T134	12		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T318	2		T322	8		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T177	11		T323	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T129	2		T218	1		T292	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T214	17		T324	4		T314	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T125	15		T99	8		T318	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T131	1		T132	7		T173	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T26	15		T101	1		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T9	1		T40	1		T15	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T1	2		T3	1		T138	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T8	5		T102	3		T127	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T74	1		T233	1		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T135	5		T133	1		T70	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T138	8		T40	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1391	1			T4	3		T7	19		T11	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T135	14		T126	5		T33	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T39	1		T134	1		T71	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T201	10		T126	2		T204	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T130	2		T131	12		T132	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T9	1		T218	1		T141	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T131	5		T125	14		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T3	1		T11	1		T126	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T6	3		T11	1		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	407	1			T3	1		T26	3		T13	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17177	1			T1	34		T2	207		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T177	4		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T129	7		T292	16		T297	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T214	12		T324	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T125	9		T99	6		T318	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T132	6		T134	12		T212	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T224	14		T85	25		T300	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T40	8		T15	4		T129	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T1	1		T3	10		T204	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T8	11		T127	9		T15	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T225	10		T205	17		T195	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T135	6		T222	13		T326	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T40	10		T136	15		T258	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T4	44		T25	29		T38	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T135	1		T126	10		T33	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T39	9		T134	5		T35	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T126	5		T204	13		T17	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T130	18		T132	16		T222	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T208	11		T224	2		T200	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T125	10		T139	6		T137	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T3	11		T126	9		T285	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T40	14		T125	4		T34	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	7		T13	2		T14	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

auto[0]

4322

1

T1

1

T3

28

T4

44