Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T3	1		T102	3		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T3	1		T39	1		T76	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T4	3		T7	19		T8	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	1		T125	14		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T6	3		T9	1		T101	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T130	1		T136	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T173	1		T133	1		T137	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T70	1		T73	3		T74	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	1		T138	8		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T130	1		T135	14		T125	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T11	1		T127	10		T131	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T1	2		T141	14		T232	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T138	4		T139	8		T35	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T11	2		T14	6		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T127	11		T131	1		T132	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T26	15		T40	1		T233	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T26	3		T173	1		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T15	17		T133	1		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T127	12		T129	2		T212	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T33	21		T36	7		T234	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17178	1			T1	34		T2	207		T5	115
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T3	11		T130	6		T125	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T3	7		T39	9		T140	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T4	44		T8	11		T25	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T125	10		T226	8		T246	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T132	16		T126	10		T139	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T130	5		T136	15		T159	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T137	11		T222	13		T247	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T73	3		T211	9		T174	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T3	10		T40	8		T34	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T130	12		T135	1		T125	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T127	10		T244	18		T228	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T1	1		T248	12		T249	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T139	8		T140	2		T18	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T14	2		T40	14		T135	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T127	13		T132	6		T126	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T40	10		T212	28		T224	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T173	13		T134	5		T16	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T15	6		T35	10		T204	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T127	9		T129	7		T212	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T33	6		T36	7		T239	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	453	1			T1	4		T2	5		T5	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T229	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T230	1		T231	6		T240	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T3	1		T102	3		T125	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T3	1		T39	1		T76	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T4	3		T7	19		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T9	1		T125	14		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T8	5		T9	1		T101	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T130	1		T136	1		T71	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T6	3		T132	12		T137	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T125	6		T133	1		T70	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	1		T40	1		T201	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T135	14		T139	2		T73	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T138	8		T131	12		T76	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T130	1		T141	14		T209	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	1		T138	4		T127	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	2		T11	1		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T132	7		T139	8		T140	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T11	1		T26	15		T14	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T26	3		T127	23		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T40	1		T15	17		T33	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16740	1			T1	30		T2	202		T5	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T129	7		T242	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T229	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T250	14		T243	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	11		T125	9		T35	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	7		T39	9		T140	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T4	44		T25	29		T38	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T125	10		T137	1		T226	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T8	11		T132	9		T126	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T130	5		T136	15		T244	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T132	7		T137	11		T222	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T125	4		T211	9		T159	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T3	10		T40	8		T155	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T135	1		T73	3		T167	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T34	1		T244	18		T228	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T130	12		T209	12		T225	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T127	10		T126	5		T18	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	1		T40	14		T135	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T132	6		T139	8		T140	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	2		T126	9		T129	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T127	22		T173	13		T134	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T40	10		T15	6		T33	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

auto[0]

4322

1

T1

1

T3

28

T4

44