Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26731

1

T1

37

T2

207

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23277

1

T1

34

T2

207

T3

8

auto[ADC_CTRL_FILTER_COND_OUT]

3454

1

T1

3

T3

23

T6

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20691

1

T1

37

T2

207

T3

19

auto[1]

6040

1

T3

12

T4

47

T7

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22404

1

T1

33

T2

207

T3

31

auto[1]

4327

1

T1

4

T6

2

T7

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	19	1			T251	19		-	-		-	-
values[0]	34	1			T140	5		T252	1		T253	5
values[1]	951	1			T11	1		T102	3		T40	26
values[2]	774	1			T3	8		T8	16		T9	1
values[3]	1037	1			T26	15		T138	4		T39	10
values[4]	633	1			T1	3		T11	1		T132	17
values[5]	642	1			T15	12		T33	27		T207	14
values[6]	646	1			T6	3		T125	10		T132	19
values[7]	634	1			T3	11		T9	1		T11	1
values[8]	3187	1			T3	12		T4	47		T7	19
values[9]	997	1			T26	3		T138	22		T14	8
minimum	17177	1			T1	34		T2	207		T5	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1223	1			T11	1		T40	26		T127	20
values[1]	921	1			T3	8		T8	16		T9	1
values[2]	832	1			T138	4		T39	10		T15	11
values[3]	604	1			T1	3		T11	1		T15	12
values[4]	565	1			T6	3		T132	17		T126	27
values[5]	815	1			T40	9		T131	5		T125	10
values[6]	2963	1			T3	11		T4	47		T7	19
values[7]	726	1			T3	12		T26	3		T135	11
values[8]	781	1			T138	22		T127	21		T131	1
values[9]	124	1			T14	8		T241	2		T247	34
minimum	17177	1			T1	34		T2	207		T5	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

4322

1

T1

1

T3

28

T4

44

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T40	11		T130	7		T74	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T11	1		T40	15		T127	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T3	8		T8	12		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	3		T102	1		T127	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T39	10		T201	1		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T138	1		T15	7		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T15	6		T34	6		T137	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	2		T11	1		T139	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T132	10		T126	10		T129	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T6	3		T33	14		T207	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T131	1		T125	5		T132	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T40	9		T133	1		T212	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1598	1			T4	47		T7	2		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	11		T9	1		T130	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T135	7		T125	11		T173	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	12		T26	1		T139	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T138	1		T134	13		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T138	1		T127	10		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T14	3		T241	1		T85	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T247	15		T148	1		T254	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17036	1			T1	31		T2	207		T5	115
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T212	13		T140	2		T167	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T127	9		T35	4		T137	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T8	4		T26	14		T135	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	4		T102	2		T127	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T201	9		T131	11		T126	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T138	3		T15	4		T129	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T15	6		T34	2		T137	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T1	1		T35	1		T149	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T132	7		T126	17		T129	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T33	13		T207	13		T241	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T131	4		T125	5		T132	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T212	2		T200	2		T213	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1072	1			T7	17		T210	12		T125	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T200	14		T255	2		T244	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T135	4		T125	13		T209	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T26	2		T139	7		T212	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T138	7		T149	9		T236	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T138	13		T127	11		T35	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T14	5		T241	1		T239	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T247	19		T251	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	3		T6	2		T32	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T251	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T140	3		T252	1		T256	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T253	1		T257	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T40	11		T74	1		T233	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T11	1		T102	1		T40	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T3	8		T8	12		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	3		T130	6		T203	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T26	1		T39	10		T201	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T138	1		T127	14		T15	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T132	10		T129	13		T76	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	2		T11	1		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T15	6		T141	1		T186	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T33	14		T207	1		T203	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T125	5		T132	8		T136	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T6	3		T133	1		T212	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	1		T101	1		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	11		T9	1		T40	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1705	1			T4	47		T7	2		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T3	12		T133	1		T139	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T138	1		T14	3		T125	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T26	1		T138	1		T127	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17036	1			T1	31		T2	207		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T251	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T140	2		T256	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T253	4		T257	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T212	13		T167	12		T178	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T102	2		T127	9		T35	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T8	4		T135	13		T213	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	4		T204	18		T223	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T26	14		T201	9		T131	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T138	3		T127	10		T15	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T132	7		T129	18		T34	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T1	1		T35	1		T16	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T15	6		T141	13		T186	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T33	13		T207	13		T149	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T125	5		T132	11		T126	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T212	2		T200	2		T213	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T131	4		T125	14		T144	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T200	14		T255	2		T248	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1107	1			T7	17		T210	12		T135	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T139	7		T212	10		T237	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T138	7		T14	5		T125	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T26	2		T138	13		T127	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	3		T6	2		T32	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T40	1		T130	1		T74	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T11	1		T40	1		T127	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T3	1		T8	5		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	5		T102	3		T127	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T39	1		T201	10		T131	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T138	4		T15	9		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	8		T34	7		T137	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	2		T11	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T132	8		T126	18		T129	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T6	3		T33	21		T207	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T131	5		T125	6		T132	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T40	1		T133	1		T212	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1402	1			T4	3		T7	19		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T3	1		T9	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T135	5		T125	14		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T3	1		T26	3		T139	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T138	8		T134	1		T149	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T138	14		T127	12		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T14	6		T241	2		T85	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T247	20		T148	1		T254	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17177	1			T1	34		T2	207		T5	115
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T40	10		T130	6		T212	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T40	14		T127	10		T130	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T3	7		T8	11		T135	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	2		T127	13		T226	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T39	9		T126	10		T217	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T15	2		T129	7		T16	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T15	4		T34	1		T137	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T1	1		T139	6		T258	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T132	9		T126	9		T129	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T33	6		T241	1		T159	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T125	4		T132	7		T136	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T40	8		T212	11		T225	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T4	44		T25	29		T38	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	10		T130	12		T200	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T135	6		T125	10		T173	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T3	11		T139	8		T212	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T134	12		T228	11		T259	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T127	9		T134	5		T35	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T14	2		T85	9		T239	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T247	14		T251	8		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T251	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T140	3		T252	1		T256	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T253	5		T257	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T40	1		T74	1		T233	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T11	1		T102	3		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T3	1		T8	5		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T13	5		T130	1		T203	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T26	15		T39	1		T201	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T138	4		T127	11		T15	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T132	8		T129	19		T76	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	2		T11	1		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T15	8		T141	14		T186	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T33	21		T207	14		T203	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T125	6		T132	12		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	3		T133	1		T212	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	1		T101	1		T131	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T3	1		T9	1		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1442	1			T4	3		T7	19		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	1		T133	1		T139	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T138	8		T14	6		T125	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T26	3		T138	14		T127	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17177	1			T1	34		T2	207		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T251	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T140	2		T256	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T257	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T40	10		T212	17		T167	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T40	14		T127	10		T35	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	7		T8	11		T130	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T13	2		T130	5		T204	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T39	9		T126	15		T217	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T127	13		T15	2		T129	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T132	9		T129	12		T34	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T1	1		T139	6		T16	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T15	4		T186	2		T260	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T33	6		T261	8		T155	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T125	4		T132	7		T136	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T212	11		T225	8		T200	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T125	9		T262	1		T220	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	10		T40	8		T130	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1370	1			T4	44		T25	29		T38	27
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	11		T139	8		T212	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T14	2		T125	10		T134	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T127	9		T134	5		T35	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

auto[0]

4322

1

T1

1

T3

28

T4

44