Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26731

1

T1

37

T2

207

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23217

1

T1

34

T2

207

T3

31

auto[ADC_CTRL_FILTER_COND_OUT]

3514

1

T1

3

T9

2

T11

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20625

1

T1

37

T2

207

T3

23

auto[1]

6106

1

T3

8

T4

47

T7

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22404

1

T1

33

T2

207

T3

31

auto[1]

4327

1

T1

4

T6

2

T7

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	14	1			T85	4		T263	10		-	-
values[0]	67	1			T11	1		T70	1		T186	5
values[1]	658	1			T127	44		T135	11		T126	15
values[2]	757	1			T8	16		T101	1		T138	14
values[3]	666	1			T1	3		T9	1		T201	10
values[4]	609	1			T26	3		T138	4		T40	11
values[5]	3066	1			T4	47		T7	19		T9	1
values[6]	1041	1			T3	11		T13	7		T15	12
values[7]	721	1			T40	9		T130	7		T125	24
values[8]	717	1			T3	12		T11	1		T102	3
values[9]	1238	1			T3	8		T6	3		T11	1
minimum	17177	1			T1	34		T2	207		T5	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	835	1			T11	1		T127	44		T135	11
values[1]	898	1			T1	3		T8	16		T101	1
values[2]	545	1			T9	1		T201	10		T173	14
values[3]	2963	1			T4	47		T7	19		T9	1
values[4]	743	1			T39	10		T14	8		T15	11
values[5]	943	1			T15	12		T130	7		T132	17
values[6]	886	1			T3	23		T13	7		T130	6
values[7]	614	1			T11	1		T102	3		T40	9
values[8]	903	1			T3	8		T6	3		T11	1
values[9]	224	1			T127	21		T133	1		T203	1
minimum	17177	1			T1	34		T2	207		T5	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

4322

1

T1

1

T3

28

T4

44

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T11	1		T127	14		T135	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T127	11		T133	1		T134	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T8	12		T101	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	2		T125	5		T132	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T201	1		T173	14		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T9	1		T133	1		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1540	1			T4	47		T7	2		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	1		T132	7		T35	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T131	1		T135	2		T33	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T39	10		T14	3		T15	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T128	1		T218	1		T203	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T15	6		T130	7		T132	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T3	23		T13	3		T134	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T130	6		T125	10		T129	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T102	1		T136	16		T126	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T11	1		T40	9		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T3	8		T6	3		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T26	1		T138	1		T125	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T127	10		T133	1		T247	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T203	1		T248	3		T85	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17036	1			T1	31		T2	207		T5	115
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T127	10		T135	4		T126	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T127	9		T208	14		T223	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T8	4		T138	13		T212	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	1		T125	5		T132	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T201	9		T142	5		T232	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T207	13		T137	8		T206	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T7	17		T26	2		T210	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T132	6		T35	1		T140	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T131	11		T135	13		T33	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T14	5		T15	4		T35	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T214	16		T223	6		T200	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T15	6		T132	7		T34	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	4		T73	2		T237	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T125	14		T129	1		T255	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T102	2		T126	1		T209	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T131	4		T139	7		T141	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T126	17		T141	12		T200	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T26	14		T138	7		T125	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T127	11		T264	14		T265	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T248	9		T266	8		T163	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	3		T6	2		T32	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T263	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T85	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T11	1		T70	1		T186	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T222	14		T267	11		T163	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T127	14		T135	7		T126	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T127	11		T208	12		T223	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T8	12		T101	1		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T132	8		T133	1		T134	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T201	1		T140	3		T17	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T1	2		T9	1		T125	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T26	1		T138	1		T40	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T132	7		T133	1		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1579	1			T4	47		T7	2		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T9	1		T39	10		T14	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T3	11		T13	3		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T15	6		T139	7		T34	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T134	6		T73	4		T218	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T40	9		T130	7		T125	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	12		T102	1		T126	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	1		T130	6		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	382	1			T3	8		T6	3		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T26	1		T138	1		T125	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17036	1			T1	31		T2	207		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T263	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T186	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T222	2		T267	12		T163	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T127	10		T135	4		T126	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T127	9		T208	14		T223	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T8	4		T138	13		T212	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T132	11		T149	9		T258	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T201	9		T140	2		T17	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T1	1		T125	5		T207	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T26	2		T138	3		T131	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T132	6		T35	1		T144	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T7	17		T210	12		T135	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	5		T15	4		T212	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T13	4		T214	16		T223	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T15	6		T34	2		T35	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T73	2		T237	11		T236	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T125	14		T132	7		T255	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T102	2		T126	1		T209	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T131	4		T139	7		T129	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T127	11		T126	17		T141	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T26	14		T138	7		T125	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	3		T6	2		T32	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T11	1		T127	11		T135	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T127	10		T133	1		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T8	5		T101	1		T138	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T1	2		T125	6		T132	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T201	10		T173	1		T142	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T9	1		T133	1		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T4	3		T7	19		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T9	1		T132	7		T35	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T131	12		T135	14		T33	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T39	1		T14	6		T15	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T128	1		T218	1		T203	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T15	8		T130	1		T132	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	2		T13	5		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T130	1		T125	15		T129	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T102	3		T136	1		T126	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	1		T40	1		T131	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T3	1		T6	3		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T26	15		T138	8		T125	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T127	12		T133	1		T247	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T203	1		T248	10		T85	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17177	1			T1	34		T2	207		T5	115
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T127	13		T135	6		T126	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T127	10		T134	12		T205	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T8	11		T130	12		T212	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	1		T125	4		T132	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T173	13		T268	9		T235	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T137	1		T217	14		T28	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1228	1			T4	44		T25	29		T38	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T132	6		T140	17		T137	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T135	1		T33	6		T262	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T39	9		T14	2		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T214	12		T200	10		T186	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T15	4		T130	6		T132	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T3	21		T13	2		T134	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T130	5		T125	9		T129	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T136	15		T126	5		T209	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T40	8		T139	8		T37	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	7		T40	14		T126	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T125	10		T35	1		T167	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T127	9		T247	9		T264	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T248	2		T85	3		T168	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T263	10		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T85	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T11	1		T70	1		T186	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T222	3		T267	13		T163	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T127	11		T135	5		T126	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T127	10		T208	15		T223	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T8	5		T101	1		T138	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T132	12		T133	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T201	10		T140	3		T17	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T1	2		T9	1		T125	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T26	3		T138	4		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T132	7		T133	1		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T4	3		T7	19		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T9	1		T39	1		T14	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T3	1		T13	5		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T15	8		T139	1		T34	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T134	1		T73	3		T218	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T40	1		T130	1		T125	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T3	1		T102	3		T126	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T11	1		T130	1		T131	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T3	1		T6	3		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T26	15		T138	8		T125	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17177	1			T1	34		T2	207		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T85	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T222	13		T267	10		T163	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T127	13		T135	6		T126	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T127	10		T208	11		T195	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T8	11		T130	12		T173	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T132	7		T134	12		T205	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T140	2		T17	7		T235	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T1	1		T125	4		T137	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T40	10		T129	12		T222	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T132	6		T217	14		T28	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T4	44		T25	29		T38	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T39	9		T14	2		T15	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T3	10		T13	2		T214	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T15	4		T139	6		T34	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T134	5		T73	3		T226	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T40	8		T130	6		T125	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	11		T126	5		T209	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T130	5		T139	8		T129	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T3	7		T40	14		T127	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T125	10		T35	1		T167	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

auto[0]

4322

1

T1

1

T3

28

T4

44