Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26731

1

T1

37

T2

207

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22917

1

T1

34

T2

207

T3

19

auto[ADC_CTRL_FILTER_COND_OUT]

3814

1

T1

3

T3

12

T6

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20245

1

T1

34

T2

207

T3

19

auto[1]

6486

1

T1

3

T3

12

T4

47

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22404

1

T1

33

T2

207

T3

31

auto[1]

4327

1

T1

4

T6

2

T7

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	21	1			T155	16		T171	1		T281	4
values[0]	39	1			T282	13		T283	23		T284	3
values[1]	790	1			T26	15		T102	3		T40	11
values[2]	744	1			T127	21		T132	17		T133	1
values[3]	748	1			T9	1		T138	4		T130	6
values[4]	522	1			T138	8		T40	9		T135	11
values[5]	603	1			T15	11		T125	10		T70	1
values[6]	634	1			T3	11		T9	1		T11	1
values[7]	795	1			T11	2		T127	20		T125	24
values[8]	819	1			T3	8		T8	16		T26	3
values[9]	3839	1			T1	3		T3	12		T4	47
minimum	17177	1			T1	34		T2	207		T5	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1002	1			T26	15		T102	3		T40	11
values[1]	748	1			T130	6		T136	16		T133	1
values[2]	769	1			T9	1		T138	4		T131	12
values[3]	481	1			T138	8		T40	9		T15	11
values[4]	597	1			T9	1		T39	10		T15	12
values[5]	751	1			T3	11		T11	1		T101	1
values[6]	3126	1			T3	8		T4	47		T7	19
values[7]	782	1			T8	16		T13	7		T40	15
values[8]	968	1			T1	3		T3	12		T6	3
values[9]	317	1			T127	24		T135	15		T128	1
minimum	17190	1			T1	34		T2	207		T5	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

4322

1

T1

1

T3

28

T4

44

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T26	1		T102	1		T40	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T127	10		T130	13		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T133	1		T129	8		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T130	6		T136	16		T129	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T9	1		T138	1		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T212	18		T203	1		T205	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T138	1		T132	7		T126	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T40	9		T15	7		T135	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T9	1		T15	6		T125	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T39	10		T213	13		T206	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	11		T11	1		T139	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T101	1		T131	1		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1614	1			T3	8		T4	47		T7	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T11	1		T125	11		T173	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	3		T131	1		T139	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T8	12		T40	15		T127	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T139	1		T35	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	2		T3	12		T6	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T127	14		T222	14		T268	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T135	2		T128	1		T222	25
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17039	1			T1	31		T2	207		T5	115
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T26	14		T102	2		T33	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T127	11		T16	5		T137	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T129	1		T141	12		T204	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T129	18		T35	3		T204	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T138	3		T131	11		T132	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T212	13		T208	14		T223	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T138	7		T132	6		T126	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T15	4		T135	4		T126	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T15	6		T125	5		T137	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T213	15		T206	15		T280	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T139	7		T34	2		T35	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T144	7		T285	5		T222	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1014	1			T7	17		T26	2		T210	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T125	13		T237	11		T248	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T13	4		T131	4		T207	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T8	4		T127	9		T125	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T139	1		T141	6		T167	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	1		T201	9		T126	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T127	10		T222	2		T268	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T135	13		T222	20		T220	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	3		T6	2		T32	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T155	7		T281	4		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T171	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T282	1		T284	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T283	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T26	1		T102	1		T40	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T130	13		T136	16		T134	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T132	10		T129	8		T140	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T127	10		T133	1		T129	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	1		T138	1		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T130	6		T203	1		T208	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T138	1		T126	10		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T40	9		T135	7		T126	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T125	5		T71	1		T214	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T15	7		T70	1		T225	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	11		T9	1		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T101	1		T39	10		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T11	1		T173	1		T233	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T11	1		T127	11		T125	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	8		T26	1		T13	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T8	12		T40	15		T132	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1850	1			T4	47		T7	2		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	381	1			T1	2		T3	12		T6	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17036	1			T1	31		T2	207		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T155	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T282	12		T284	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T283	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T26	14		T102	2		T33	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T16	5		T137	14		T241	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T132	7		T129	1		T140	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T127	11		T129	18		T35	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T138	3		T131	11		T132	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T208	14		T223	9		T237	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T138	7		T126	17		T212	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T135	4		T126	1		T212	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T125	5		T214	16		T178	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T15	4		T213	15		T18	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T15	6		T139	7		T34	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T144	7		T222	13		T77	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T35	1		T140	2		T186	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T127	9		T125	13		T237	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T26	2		T13	4		T138	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	4		T132	11		T149	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T7	17		T210	12		T127	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T1	1		T201	9		T135	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	3		T6	2		T32	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T26	15		T102	3		T40	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T127	12		T130	1		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T133	1		T129	2		T141	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T130	1		T136	1		T129	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T9	1		T138	4		T131	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T212	14		T203	1		T205	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T138	8		T132	7		T126	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T40	1		T15	9		T135	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	1		T15	8		T125	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T39	1		T213	16		T206	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	1		T11	1		T139	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T101	1		T131	1		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T3	1		T4	3		T7	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T11	1		T125	14		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T13	5		T131	5		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T8	5		T40	1		T127	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	353	1			T139	2		T35	1		T141	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	2		T3	1		T6	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T127	11		T222	3		T268	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T135	14		T128	1		T222	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17188	1			T1	34		T2	207		T5	115
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T40	10		T33	6		T140	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T127	9		T130	12		T134	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T129	7		T225	8		T204	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T130	5		T136	15		T129	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T132	9		T35	10		T137	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T212	17		T205	17		T208	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T132	6		T126	9		T212	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T40	8		T15	2		T135	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T15	4		T125	4		T137	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T39	9		T213	12		T280	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	10		T139	8		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T285	5		T222	10		T286	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1291	1			T3	7		T4	44		T25	29
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T125	10		T173	13		T205	26
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	2		T139	6		T209	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T8	11		T40	14		T127	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T167	13		T37	6		T17	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	1		T3	11		T126	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T127	13		T222	13		T268	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T135	1		T222	24		T220	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T287	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T155	10		T281	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T171	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T282	13		T284	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T283	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T26	15		T102	3		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T130	1		T136	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T132	8		T129	2		T140	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T127	12		T133	1		T129	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T9	1		T138	4		T131	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T130	1		T203	1		T208	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T138	8		T126	18		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T40	1		T135	5		T126	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T125	6		T71	1		T214	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T15	9		T70	1		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	1		T9	1		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T101	1		T39	1		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	1		T173	1		T233	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T11	1		T127	10		T125	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T3	1		T26	3		T13	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T8	5		T40	1		T132	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1631	1			T4	3		T7	19		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	404	1			T1	2		T3	1		T6	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17177	1			T1	34		T2	207		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T155	6		T281	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T283	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T40	10		T33	6		T36	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T130	12		T136	15		T134	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T132	9		T129	7		T140	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T127	9		T129	12		T35	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T132	6		T35	10		T225	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T130	5		T208	11		T288	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T126	9		T212	11		T137	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T40	8		T135	6		T126	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T125	4		T214	12		T178	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T15	2		T225	10		T213	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T3	10		T15	4		T139	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T39	9		T222	10		T77	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T140	2		T226	15		T186	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T127	10		T125	10		T173	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	7		T13	2		T14	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	11		T40	14		T132	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1486	1			T4	44		T25	29		T38	27
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T1	1		T3	11		T135	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

auto[0]

4322

1

T1

1

T3

28

T4

44