Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26731

1

T1

37

T2

207

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23241

1

T1

34

T2

207

T3

23

auto[ADC_CTRL_FILTER_COND_OUT]

3490

1

T1

3

T3

8

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20078

1

T1

33

T2

202

T3

23

auto[1]

6653

1

T1

4

T2

5

T3

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22404

1

T1

33

T2

207

T3

31

auto[1]

4327

1

T1

4

T6

2

T7

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	733	1			T1	4		T2	5		T5	5
values[0]	35	1			T125	24		T229	11		-	-
values[1]	891	1			T3	20		T102	3		T39	10
values[2]	2943	1			T4	47		T7	19		T8	16
values[3]	780	1			T9	1		T101	1		T130	6
values[4]	654	1			T6	3		T173	1		T133	2
values[5]	746	1			T3	11		T40	9		T201	10
values[6]	780	1			T11	1		T138	8		T127	20
values[7]	821	1			T1	3		T11	1		T138	4
values[8]	749	1			T11	1		T26	15		T14	8
values[9]	859	1			T26	3		T40	11		T127	45
minimum	16740	1			T1	30		T2	202		T5	110

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	723	1			T3	20		T102	3		T130	7
values[1]	2981	1			T4	47		T7	19		T8	16
values[2]	754	1			T6	3		T9	1		T101	1
values[3]	658	1			T125	10		T173	1		T133	1
values[4]	814	1			T3	11		T138	8		T40	9
values[5]	681	1			T1	3		T11	1		T127	20
values[6]	841	1			T11	2		T138	4		T14	8
values[7]	695	1			T26	15		T40	11		T127	24
values[8]	877	1			T26	3		T15	23		T173	14
values[9]	163	1			T127	21		T129	9		T212	13
minimum	17544	1			T1	34		T2	207		T5	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

4322

1

T1

1

T3

28

T4

44

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	12		T102	1		T130	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T3	8		T76	1		T140	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1649	1			T4	47		T7	2		T8	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	1		T125	11		T137	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	3		T9	1		T132	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T101	1		T130	6		T136	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T173	1		T139	7		T70	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T125	5		T133	1		T73	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T3	11		T138	1		T40	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T130	13		T135	2		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T11	1		T76	1		T233	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	2		T127	11		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T11	1		T126	10		T139	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	1		T138	1		T14	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T26	1		T127	14		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T40	11		T131	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T26	1		T173	14		T134	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T15	13		T33	14		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T127	10		T129	8		T212	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T36	8		T17	9		T222	25
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17132	1			T1	31		T2	207		T5	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T39	10		T34	2		T137	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T102	2		T35	3		T211	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T140	13		T142	5		T220	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1043	1			T7	17		T8	4		T13	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T125	13		T137	8		T149	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T132	18		T223	9		T232	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T126	4		T144	3		T159	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T137	10		T237	11		T236	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T125	5		T73	2		T211	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T138	7		T201	9		T207	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T135	13		T139	1		T167	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T27	10		T248	15		T244	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	1		T127	9		T131	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T126	17		T139	7		T129	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T138	3		T14	5		T135	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T26	14		T127	10		T132	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T131	4		T149	12		T178	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T26	2		T35	4		T16	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T15	10		T33	13		T214	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T127	11		T129	1		T212	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T36	6		T17	10		T222	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T1	3		T6	2		T32	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T137	14		T149	5		T293	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	524	1			T1	4		T2	5		T5	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T133	1		T222	25		T288	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T125	10		T229	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T3	12		T102	1		T74	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T3	8		T39	10		T76	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1608	1			T4	47		T7	2		T8	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T9	1		T125	11		T137	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T9	1		T132	18		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T101	1		T130	6		T136	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	3		T173	1		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T133	1		T74	1		T203	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T3	11		T40	9		T201	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T135	2		T125	5		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T11	1		T138	1		T76	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T127	11		T130	13		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	1		T126	10		T70	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T1	2		T138	1		T40	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T26	1		T132	7		T126	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T11	1		T14	3		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T26	1		T127	24		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T40	11		T15	13		T33	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16599	1			T1	27		T2	202		T5	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T129	1		T35	4		T212	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T222	20		T247	19		T98	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T125	14		T229	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T102	2		T35	3		T141	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T140	13		T137	14		T149	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1013	1			T7	17		T8	4		T13	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T125	13		T137	8		T149	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T132	18		T232	4		T247	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T126	4		T144	3		T258	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T223	9		T255	6		T273	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T211	12		T222	2		T159	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T201	9		T207	13		T137	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T135	13		T125	5		T139	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T138	7		T34	2		T27	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T127	9		T131	11		T141	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T126	17		T35	1		T141	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	1		T138	3		T135	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T26	14		T132	6		T126	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	5		T131	4		T140	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T26	2		T127	21		T212	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T15	10		T33	13		T36	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	3		T6	2		T32	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	1		T102	3		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	1		T76	1		T140	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1363	1			T4	3		T7	19		T8	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T9	1		T125	14		T137	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T6	3		T9	1		T132	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T101	1		T130	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T173	1		T139	1		T70	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T125	6		T133	1		T73	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T3	1		T138	8		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T130	1		T135	14		T139	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T11	1		T76	1		T233	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	2		T127	10		T131	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T11	1		T126	18		T139	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	1		T138	4		T14	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T26	15		T127	11		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T40	1		T131	5		T149	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T26	3		T173	1		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T15	17		T33	21		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T127	12		T129	2		T212	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T36	7		T17	12		T222	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17278	1			T1	34		T2	207		T5	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T39	1		T34	2		T137	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	11		T130	6		T35	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	7		T140	17		T217	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T4	44		T8	11		T25	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T125	10		T137	1		T226	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T132	16		T205	17		T255	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T130	5		T136	15		T126	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T139	6		T137	11		T247	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T125	4		T73	3		T211	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	10		T40	8		T34	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T130	12		T135	1		T167	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T248	12		T244	18		T228	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T1	1		T127	10		T209	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T126	9		T139	8		T129	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	2		T40	14		T135	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T127	13		T132	6		T126	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T40	10		T178	6		T200	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T173	13		T134	5		T35	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T15	6		T33	6		T214	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T127	9		T129	7		T212	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T36	7		T17	7		T222	24
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T125	9		T285	5		T258	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T39	9		T137	14		T293	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	525	1			T1	4		T2	5		T5	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T133	1		T222	21		T288	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T125	15		T229	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	1		T102	3		T74	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T3	1		T39	1		T76	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T4	3		T7	19		T8	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T9	1		T125	14		T137	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T9	1		T132	20		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T101	1		T130	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	3		T173	1		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T133	1		T74	1		T203	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T3	1		T40	1		T201	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T135	14		T125	6		T139	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T11	1		T138	8		T76	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T127	10		T130	1		T131	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T11	1		T126	18		T70	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	2		T138	4		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T26	15		T132	7		T126	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	1		T14	6		T131	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T26	3		T127	23		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T40	1		T15	17		T33	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16740	1			T1	30		T2	202		T5	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T173	13		T129	7		T35	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T222	24		T288	12		T247	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T125	9		T229	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	11		T35	1		T211	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T3	7		T39	9		T140	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T4	44		T8	11		T25	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T125	10		T137	1		T217	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T132	16		T205	17		T247	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T130	5		T136	15		T126	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T139	6		T255	7		T247	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T211	9		T222	13		T288	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	10		T40	8		T137	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T135	1		T125	4		T73	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T34	1		T244	18		T228	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T127	10		T130	12		T209	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T126	9		T204	9		T200	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	1		T40	14		T135	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T132	6		T126	5		T139	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T14	2		T140	2		T224	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T127	22		T134	5		T212	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T40	10		T15	6		T33	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

auto[0]

4322

1

T1

1

T3

28

T4

44