Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26731

1

T1

37

T2

207

T3

31

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23020

1

T1

34

T2

207

T4

47

auto[ADC_CTRL_FILTER_COND_OUT]

3711

1

T1

3

T3

31

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20190

1

T1

37

T2

207

T3

20

auto[1]

6541

1

T3

11

T4

47

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22404

1

T1

33

T2

207

T3

31

auto[1]

4327

1

T1

4

T6

2

T7

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	251	1			T11	1		T127	20		T129	9
values[0]	38	1			T125	24		T99	14		-	-
values[1]	653	1			T26	15		T131	1		T132	13
values[2]	919	1			T1	3		T3	11		T8	16
values[3]	802	1			T102	3		T127	21		T130	6
values[4]	716	1			T138	8		T40	11		T15	11
values[5]	3030	1			T4	47		T7	19		T11	1
values[6]	829	1			T39	10		T201	10		T130	7
values[7]	704	1			T9	1		T131	12		T132	36
values[8]	673	1			T3	12		T11	1		T130	13
values[9]	939	1			T3	8		T6	3		T26	3
minimum	17177	1			T1	34		T2	207		T5	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	680	1			T1	3		T26	15		T101	1
values[1]	863	1			T3	11		T8	16		T9	1
values[2]	728	1			T102	3		T40	11		T127	21
values[3]	3002	1			T4	47		T7	19		T12	1
values[4]	876	1			T11	1		T201	10		T135	15
values[5]	757	1			T39	10		T130	7		T134	6
values[6]	744	1			T9	1		T130	13		T131	12
values[7]	605	1			T3	20		T11	1		T138	4
values[8]	885	1			T6	3		T11	1		T26	3
values[9]	126	1			T217	15		T262	3		T294	1
minimum	17465	1			T1	34		T2	207		T5	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

4322

1

T1

1

T3

28

T4

44

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T131	1		T132	7		T173	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	2		T26	1		T101	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T8	12		T9	1		T40	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	11		T207	1		T233	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T102	1		T127	10		T15	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T40	11		T74	1		T76	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1635	1			T4	47		T7	2		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T138	1		T136	16		T33	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T11	1		T71	1		T35	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T201	1		T135	2		T126	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T39	10		T130	7		T134	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T204	14		T202	1		T200	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T130	13		T131	1		T132	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T9	1		T141	1		T203	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T131	1		T125	11		T139	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	20		T11	1		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T6	3		T11	1		T40	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T26	1		T13	3		T127	25
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T217	15		T262	3		T295	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T294	1		T296	1		T297	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17144	1			T1	31		T2	207		T5	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T241	1		T85	10		T99	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T132	6		T212	10		T36	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	1		T26	14		T138	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T8	4		T15	6		T129	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T207	13		T149	5		T142	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T102	2		T127	11		T15	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T17	5		T255	6		T159	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1066	1			T7	17		T210	12		T272	37
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T138	7		T33	13		T258	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T35	4		T16	5		T211	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T201	9		T135	13		T126	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T37	8		T178	6		T144	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T204	13		T200	2		T18	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T131	11		T132	18		T141	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T141	12		T208	14		T186	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T131	4		T125	13		T34	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T138	3		T14	5		T126	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T125	5		T149	12		T241	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T26	2		T13	4		T127	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T295	13		T147	2		T177	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T296	3		T257	3		T298	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T1	3		T6	2		T32	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T241	1		T99	5		T299	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T11	1		T262	3		T241	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T127	11		T129	8		T218	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T125	10		T99	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T131	1		T132	7		T173	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T26	1		T128	1		T76	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T8	12		T9	1		T40	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T1	2		T3	11		T101	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T102	1		T127	10		T130	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T74	1		T225	11		T203	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T15	7		T135	7		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T138	1		T40	11		T136	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1610	1			T4	47		T7	2		T11	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T135	2		T126	11		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T39	10		T130	7		T134	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T201	1		T126	6		T204	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T131	1		T132	18		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T9	1		T141	1		T203	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T130	13		T125	11		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	12		T11	1		T126	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T6	3		T40	15		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T3	8		T26	1		T13	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17036	1			T1	31		T2	207		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T241	1		T77	12		T244	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T127	9		T129	1		T29	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T125	14		T99	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T132	6		T212	10		T214	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T26	14		T149	9		T223	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T8	4		T15	6		T129	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T1	1		T138	13		T207	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T102	2		T127	11		T139	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T195	2		T255	6		T159	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T15	4		T135	4		T279	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T138	7		T33	13		T17	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1047	1			T7	17		T210	12		T272	37
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T135	13		T126	4		T139	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T35	4		T178	6		T144	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T201	9		T126	1		T204	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T131	11		T132	18		T141	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T141	12		T208	14		T200	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T125	13		T137	8		T211	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T126	17		T186	4		T285	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T131	4		T125	5		T34	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T26	2		T13	4		T138	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	3		T6	2		T32	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T131	1		T132	7		T173	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T1	2		T26	15		T101	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T8	5		T9	1		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T3	1		T207	14		T233	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T102	3		T127	12		T15	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T40	1		T74	1		T76	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1394	1			T4	3		T7	19		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T138	8		T136	1		T33	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T11	1		T71	1		T35	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T201	10		T135	14		T126	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T39	1		T130	1		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T204	14		T202	1		T200	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T130	1		T131	12		T132	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T9	1		T141	13		T203	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T131	5		T125	14		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	2		T11	1		T138	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T6	3		T11	1		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T26	3		T13	5		T127	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T217	1		T262	2		T295	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T294	1		T296	4		T297	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17265	1			T1	34		T2	207		T5	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T241	2		T85	1		T99	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T132	6		T212	2		T36	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T1	1		T125	9		T204	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T8	11		T40	8		T15	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T3	10		T195	1		T248	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T127	9		T15	2		T135	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T40	10		T225	10		T205	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1307	1			T4	44		T25	29		T38	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T136	15		T33	6		T258	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T35	10		T16	5		T225	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T135	1		T126	15		T73	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T39	9		T130	6		T134	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T204	13		T200	22		T18	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T130	12		T132	16		T222	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T208	11		T224	2		T222	24
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T125	10		T139	6		T34	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	18		T14	2		T126	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T40	14		T125	4		T241	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	2		T127	23		T129	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T217	14		T262	1		T177	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T297	8		T257	8		T169	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T134	12		T214	12		T244	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T85	9		T99	6		T227	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T11	1		T262	2		T241	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T127	10		T129	2		T218	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T125	15		T99	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T131	1		T132	7		T173	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T26	15		T128	1		T76	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T8	5		T9	1		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T1	2		T3	1		T101	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T102	3		T127	12		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T74	1		T225	1		T203	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T15	9		T135	5		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T138	8		T40	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1361	1			T4	3		T7	19		T11	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T135	14		T126	5		T139	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T39	1		T130	1		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T201	10		T126	2		T204	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T131	12		T132	20		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T9	1		T141	13		T203	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T130	1		T125	14		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T3	1		T11	1		T126	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T6	3		T40	1		T131	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T3	1		T26	3		T13	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17177	1			T1	34		T2	207		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T262	1		T241	1		T77	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T127	10		T129	7		T29	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T125	9		T99	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T132	6		T134	12		T212	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T224	14		T85	25		T300	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T8	11		T40	8		T15	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	1		T3	10		T204	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T127	9		T130	5		T173	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T225	10		T205	17		T195	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T15	2		T135	6		T279	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T40	10		T136	15		T33	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1296	1			T4	44		T25	29		T38	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T135	1		T126	10		T73	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T39	9		T130	6		T134	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T126	5		T204	13		T18	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T132	16		T37	6		T222	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T208	11		T224	2		T200	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T130	12		T125	10		T137	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T3	11		T126	9		T285	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T40	14		T125	4		T139	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	7		T13	2		T14	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22409

1

T1

36

T2

207

T3

3

auto[1]

auto[0]

4322

1

T1

1

T3

28

T4

44