Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.75 99.10 96.68 100.00 100.00 98.88 98.33 91.24


Total test records in report: 913
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T118 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2896694143 Mar 07 12:25:16 PM PST 24 Mar 07 12:25:20 PM PST 24 380614438 ps
T790 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.941414030 Mar 07 12:27:05 PM PST 24 Mar 07 12:27:06 PM PST 24 438916636 ps
T59 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3389226830 Mar 07 12:25:19 PM PST 24 Mar 07 12:25:24 PM PST 24 1025561211 ps
T60 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1383910354 Mar 07 12:26:41 PM PST 24 Mar 07 12:26:44 PM PST 24 610562503 ps
T121 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1657448443 Mar 07 12:25:50 PM PST 24 Mar 07 12:25:52 PM PST 24 330577678 ps
T791 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.4245102958 Mar 07 12:26:01 PM PST 24 Mar 07 12:26:02 PM PST 24 463174896 ps
T79 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1964620947 Mar 07 12:25:59 PM PST 24 Mar 07 12:26:00 PM PST 24 419412601 ps
T792 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2707286889 Mar 07 12:26:00 PM PST 24 Mar 07 12:26:01 PM PST 24 358813639 ps
T793 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2525816963 Mar 07 12:26:33 PM PST 24 Mar 07 12:26:35 PM PST 24 441153378 ps
T794 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.960966492 Mar 07 12:25:43 PM PST 24 Mar 07 12:25:44 PM PST 24 330104145 ps
T61 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1769401286 Mar 07 12:25:50 PM PST 24 Mar 07 12:25:52 PM PST 24 413377538 ps
T51 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1418085663 Mar 07 12:25:39 PM PST 24 Mar 07 12:25:43 PM PST 24 4201177816 ps
T795 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2844353400 Mar 07 12:26:55 PM PST 24 Mar 07 12:26:57 PM PST 24 524664203 ps
T796 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1070828291 Mar 07 12:26:04 PM PST 24 Mar 07 12:26:05 PM PST 24 371254488 ps
T52 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2781284396 Mar 07 12:25:40 PM PST 24 Mar 07 12:25:58 PM PST 24 7986455789 ps
T797 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.45166183 Mar 07 12:25:58 PM PST 24 Mar 07 12:25:59 PM PST 24 351284422 ps
T89 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3883140049 Mar 07 12:25:51 PM PST 24 Mar 07 12:25:52 PM PST 24 528324273 ps
T104 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3315132503 Mar 07 12:26:01 PM PST 24 Mar 07 12:26:02 PM PST 24 385131682 ps
T105 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3422443318 Mar 07 12:25:25 PM PST 24 Mar 07 12:25:26 PM PST 24 583632595 ps
T798 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3750869554 Mar 07 12:25:59 PM PST 24 Mar 07 12:26:00 PM PST 24 553740789 ps
T799 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.323389488 Mar 07 12:27:15 PM PST 24 Mar 07 12:27:17 PM PST 24 335202713 ps
T800 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1790768605 Mar 07 12:25:18 PM PST 24 Mar 07 12:25:21 PM PST 24 352361172 ps
T106 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2285315655 Mar 07 12:25:24 PM PST 24 Mar 07 12:25:29 PM PST 24 971396199 ps
T65 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1555106764 Mar 07 12:25:35 PM PST 24 Mar 07 12:25:37 PM PST 24 512662305 ps
T90 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1928770414 Mar 07 12:26:24 PM PST 24 Mar 07 12:26:26 PM PST 24 472367956 ps
T53 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1146870109 Mar 07 12:26:21 PM PST 24 Mar 07 12:26:27 PM PST 24 4213853446 ps
T47 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1327762143 Mar 07 12:25:24 PM PST 24 Mar 07 12:25:27 PM PST 24 2172404214 ps
T107 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3286786509 Mar 07 12:25:45 PM PST 24 Mar 07 12:25:47 PM PST 24 397042607 ps
T801 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2679885575 Mar 07 12:25:43 PM PST 24 Mar 07 12:25:44 PM PST 24 496500342 ps
T802 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.4164517090 Mar 07 12:26:30 PM PST 24 Mar 07 12:26:30 PM PST 24 659490566 ps
T803 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.903280141 Mar 07 12:25:50 PM PST 24 Mar 07 12:25:52 PM PST 24 577620378 ps
T50 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2465948266 Mar 07 12:25:36 PM PST 24 Mar 07 12:25:46 PM PST 24 2593168234 ps
T804 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2585179042 Mar 07 12:25:51 PM PST 24 Mar 07 12:25:52 PM PST 24 703303309 ps
T805 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2439627395 Mar 07 12:25:56 PM PST 24 Mar 07 12:25:57 PM PST 24 610641474 ps
T62 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.895568995 Mar 07 12:25:50 PM PST 24 Mar 07 12:25:53 PM PST 24 437997405 ps
T806 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2486701087 Mar 07 12:25:43 PM PST 24 Mar 07 12:25:44 PM PST 24 583203031 ps
T327 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.4282776737 Mar 07 12:25:50 PM PST 24 Mar 07 12:25:57 PM PST 24 4318499997 ps
T807 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.753408457 Mar 07 12:25:05 PM PST 24 Mar 07 12:25:07 PM PST 24 643708102 ps
T122 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1309746870 Mar 07 12:25:32 PM PST 24 Mar 07 12:25:33 PM PST 24 1000543710 ps
T808 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1510053433 Mar 07 12:26:01 PM PST 24 Mar 07 12:26:02 PM PST 24 309347492 ps
T809 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2609487375 Mar 07 12:26:30 PM PST 24 Mar 07 12:26:31 PM PST 24 558553238 ps
T810 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3358900057 Mar 07 12:26:43 PM PST 24 Mar 07 12:26:44 PM PST 24 586752305 ps
T119 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2050796652 Mar 07 12:26:00 PM PST 24 Mar 07 12:26:01 PM PST 24 477740737 ps
T811 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.4073289965 Mar 07 12:25:15 PM PST 24 Mar 07 12:25:17 PM PST 24 714682711 ps
T48 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1483411312 Mar 07 12:26:02 PM PST 24 Mar 07 12:26:19 PM PST 24 4114514176 ps
T812 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2730306844 Mar 07 12:26:42 PM PST 24 Mar 07 12:26:43 PM PST 24 451571818 ps
T813 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1787829223 Mar 07 12:26:27 PM PST 24 Mar 07 12:26:28 PM PST 24 377531283 ps
T814 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3493045012 Mar 07 12:25:32 PM PST 24 Mar 07 12:25:33 PM PST 24 504181863 ps
T815 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1072373645 Mar 07 12:26:01 PM PST 24 Mar 07 12:26:02 PM PST 24 874746555 ps
T816 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.28315069 Mar 07 12:26:06 PM PST 24 Mar 07 12:26:08 PM PST 24 443950306 ps
T49 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3657913394 Mar 07 12:25:58 PM PST 24 Mar 07 12:26:00 PM PST 24 2431177024 ps
T817 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2845908022 Mar 07 12:26:08 PM PST 24 Mar 07 12:26:10 PM PST 24 526490073 ps
T818 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2290521943 Mar 07 12:25:32 PM PST 24 Mar 07 12:25:34 PM PST 24 464605813 ps
T120 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2801519980 Mar 07 12:25:21 PM PST 24 Mar 07 12:25:23 PM PST 24 307406892 ps
T819 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2391823383 Mar 07 12:25:50 PM PST 24 Mar 07 12:25:51 PM PST 24 320988069 ps
T820 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.358092152 Mar 07 12:25:58 PM PST 24 Mar 07 12:25:59 PM PST 24 406472131 ps
T821 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1034359298 Mar 07 12:25:35 PM PST 24 Mar 07 12:25:39 PM PST 24 2509987953 ps
T822 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.4052414605 Mar 07 12:26:02 PM PST 24 Mar 07 12:26:03 PM PST 24 384787349 ps
T108 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3446232677 Mar 07 12:25:36 PM PST 24 Mar 07 12:25:38 PM PST 24 362947414 ps
T823 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3889027250 Mar 07 12:25:55 PM PST 24 Mar 07 12:25:57 PM PST 24 375142646 ps
T824 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1975619838 Mar 07 12:25:15 PM PST 24 Mar 07 12:25:17 PM PST 24 541136943 ps
T825 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3815018421 Mar 07 12:25:19 PM PST 24 Mar 07 12:25:23 PM PST 24 418499071 ps
T826 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1408618347 Mar 07 12:25:40 PM PST 24 Mar 07 12:25:42 PM PST 24 740174071 ps
T827 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2876074094 Mar 07 12:26:56 PM PST 24 Mar 07 12:27:04 PM PST 24 4581778569 ps
T828 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2765303037 Mar 07 12:26:08 PM PST 24 Mar 07 12:26:09 PM PST 24 419635217 ps
T829 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.318977405 Mar 07 12:25:54 PM PST 24 Mar 07 12:25:59 PM PST 24 4600574018 ps
T830 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2063724756 Mar 07 12:26:41 PM PST 24 Mar 07 12:26:42 PM PST 24 418233600 ps
T831 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.903487022 Mar 07 12:25:33 PM PST 24 Mar 07 12:25:36 PM PST 24 418913562 ps
T832 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1746694136 Mar 07 12:25:25 PM PST 24 Mar 07 12:25:30 PM PST 24 4503552032 ps
T833 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2106795714 Mar 07 12:26:30 PM PST 24 Mar 07 12:26:32 PM PST 24 420869072 ps
T834 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3139318218 Mar 07 12:26:02 PM PST 24 Mar 07 12:26:04 PM PST 24 416689884 ps
T835 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.4051405901 Mar 07 12:26:45 PM PST 24 Mar 07 12:26:47 PM PST 24 515206315 ps
T836 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3173148229 Mar 07 12:26:17 PM PST 24 Mar 07 12:26:19 PM PST 24 374497438 ps
T837 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3694303028 Mar 07 12:26:11 PM PST 24 Mar 07 12:26:15 PM PST 24 305048684 ps
T838 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.4218527366 Mar 07 12:26:17 PM PST 24 Mar 07 12:26:28 PM PST 24 3987627867 ps
T839 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3445851633 Mar 07 12:25:40 PM PST 24 Mar 07 12:25:45 PM PST 24 4542161674 ps
T840 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3012352471 Mar 07 12:25:59 PM PST 24 Mar 07 12:26:01 PM PST 24 405762627 ps
T109 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2116059928 Mar 07 12:25:21 PM PST 24 Mar 07 12:26:37 PM PST 24 50743133481 ps
T110 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2657711705 Mar 07 12:26:08 PM PST 24 Mar 07 12:26:11 PM PST 24 1015883290 ps
T841 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2735497305 Mar 07 12:25:59 PM PST 24 Mar 07 12:26:02 PM PST 24 1329452046 ps
T111 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.609980313 Mar 07 12:25:43 PM PST 24 Mar 07 12:25:45 PM PST 24 445728461 ps
T842 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3954159280 Mar 07 12:26:03 PM PST 24 Mar 07 12:26:05 PM PST 24 485090754 ps
T843 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3051254321 Mar 07 12:26:43 PM PST 24 Mar 07 12:26:51 PM PST 24 4404492910 ps
T844 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3523697952 Mar 07 12:26:07 PM PST 24 Mar 07 12:26:08 PM PST 24 434584389 ps
T845 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.4189041053 Mar 07 12:26:30 PM PST 24 Mar 07 12:26:31 PM PST 24 427258364 ps
T846 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.955809507 Mar 07 12:26:14 PM PST 24 Mar 07 12:26:16 PM PST 24 5124189454 ps
T847 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1449409418 Mar 07 12:25:22 PM PST 24 Mar 07 12:25:44 PM PST 24 5291611387 ps
T848 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1038453087 Mar 07 12:25:24 PM PST 24 Mar 07 12:25:26 PM PST 24 610380354 ps
T849 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3195781841 Mar 07 12:25:59 PM PST 24 Mar 07 12:26:00 PM PST 24 393643020 ps
T850 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3425763266 Mar 07 12:25:34 PM PST 24 Mar 07 12:25:36 PM PST 24 506810516 ps
T851 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.562046852 Mar 07 12:25:58 PM PST 24 Mar 07 12:25:59 PM PST 24 620871864 ps
T852 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.106530615 Mar 07 12:25:53 PM PST 24 Mar 07 12:25:55 PM PST 24 601223087 ps
T112 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2030708887 Mar 07 12:25:53 PM PST 24 Mar 07 12:25:55 PM PST 24 441702122 ps
T853 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.4027217745 Mar 07 12:27:12 PM PST 24 Mar 07 12:27:14 PM PST 24 418092043 ps
T854 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2327307603 Mar 07 12:26:46 PM PST 24 Mar 07 12:26:48 PM PST 24 320782123 ps
T328 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3739317079 Mar 07 12:25:32 PM PST 24 Mar 07 12:25:40 PM PST 24 8214935802 ps
T855 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.8174433 Mar 07 12:25:18 PM PST 24 Mar 07 12:25:31 PM PST 24 8266791484 ps
T856 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1009628480 Mar 07 12:25:16 PM PST 24 Mar 07 12:25:19 PM PST 24 340651151 ps
T857 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.830998006 Mar 07 12:25:43 PM PST 24 Mar 07 12:25:44 PM PST 24 580369572 ps
T858 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.4095814828 Mar 07 12:26:00 PM PST 24 Mar 07 12:26:05 PM PST 24 4591134682 ps
T859 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1783608295 Mar 07 12:26:10 PM PST 24 Mar 07 12:26:12 PM PST 24 478564149 ps
T860 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2139595291 Mar 07 12:26:46 PM PST 24 Mar 07 12:26:47 PM PST 24 564630103 ps
T861 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.234823614 Mar 07 12:26:05 PM PST 24 Mar 07 12:26:06 PM PST 24 365375208 ps
T862 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3063183272 Mar 07 12:26:03 PM PST 24 Mar 07 12:26:05 PM PST 24 586483740 ps
T863 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1314693150 Mar 07 12:27:05 PM PST 24 Mar 07 12:27:07 PM PST 24 284654840 ps
T864 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.563083319 Mar 07 12:26:41 PM PST 24 Mar 07 12:26:45 PM PST 24 4813297201 ps
T865 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2824787696 Mar 07 12:25:48 PM PST 24 Mar 07 12:25:50 PM PST 24 411850400 ps
T866 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2231927659 Mar 07 12:25:43 PM PST 24 Mar 07 12:25:53 PM PST 24 2001676921 ps
T867 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.122056485 Mar 07 12:26:07 PM PST 24 Mar 07 12:26:08 PM PST 24 302681524 ps
T868 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.14893406 Mar 07 12:25:31 PM PST 24 Mar 07 12:25:34 PM PST 24 868159441 ps
T869 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.511749259 Mar 07 12:27:15 PM PST 24 Mar 07 12:27:16 PM PST 24 456006336 ps
T870 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2253510933 Mar 07 12:26:42 PM PST 24 Mar 07 12:26:49 PM PST 24 8416467243 ps
T871 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.112911499 Mar 07 12:25:07 PM PST 24 Mar 07 12:25:11 PM PST 24 620278979 ps
T329 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1436114503 Mar 07 12:25:34 PM PST 24 Mar 07 12:25:56 PM PST 24 8649188067 ps
T872 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.8218415 Mar 07 12:25:43 PM PST 24 Mar 07 12:25:54 PM PST 24 4410371530 ps
T873 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2169088347 Mar 07 12:26:09 PM PST 24 Mar 07 12:26:13 PM PST 24 4961276158 ps
T113 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.650843869 Mar 07 12:26:16 PM PST 24 Mar 07 12:26:18 PM PST 24 673411479 ps
T874 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2991868408 Mar 07 12:25:37 PM PST 24 Mar 07 12:25:39 PM PST 24 427696878 ps
T875 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3871787157 Mar 07 12:26:17 PM PST 24 Mar 07 12:26:18 PM PST 24 600223453 ps
T876 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.4127151452 Mar 07 12:25:37 PM PST 24 Mar 07 12:25:39 PM PST 24 530096083 ps
T877 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.84992362 Mar 07 12:25:49 PM PST 24 Mar 07 12:25:54 PM PST 24 4032204470 ps
T878 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.99600270 Mar 07 12:25:23 PM PST 24 Mar 07 12:25:26 PM PST 24 388634725 ps
T879 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1512006414 Mar 07 12:25:33 PM PST 24 Mar 07 12:25:44 PM PST 24 4187152826 ps
T880 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1489960011 Mar 07 12:25:35 PM PST 24 Mar 07 12:25:37 PM PST 24 602244585 ps
T881 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2619658436 Mar 07 12:26:56 PM PST 24 Mar 07 12:26:58 PM PST 24 364986737 ps
T882 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2858053307 Mar 07 12:25:50 PM PST 24 Mar 07 12:25:52 PM PST 24 1991406606 ps
T883 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.880762782 Mar 07 12:26:22 PM PST 24 Mar 07 12:26:25 PM PST 24 474631745 ps
T884 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3839378449 Mar 07 12:25:56 PM PST 24 Mar 07 12:25:57 PM PST 24 380587202 ps
T885 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4289386608 Mar 07 12:26:43 PM PST 24 Mar 07 12:26:45 PM PST 24 419617231 ps
T886 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2041065119 Mar 07 12:26:28 PM PST 24 Mar 07 12:26:41 PM PST 24 8154102511 ps
T887 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1026668934 Mar 07 12:26:18 PM PST 24 Mar 07 12:26:20 PM PST 24 2257462531 ps
T888 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4073460789 Mar 07 12:26:46 PM PST 24 Mar 07 12:26:49 PM PST 24 379467593 ps
T889 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3322009172 Mar 07 12:26:00 PM PST 24 Mar 07 12:26:22 PM PST 24 7889435294 ps
T890 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2877620821 Mar 07 12:25:15 PM PST 24 Mar 07 12:26:37 PM PST 24 26082406147 ps
T117 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.385367090 Mar 07 12:26:23 PM PST 24 Mar 07 12:26:25 PM PST 24 545481870 ps
T891 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.570469476 Mar 07 12:25:50 PM PST 24 Mar 07 12:25:51 PM PST 24 475139605 ps
T892 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3725688953 Mar 07 12:25:33 PM PST 24 Mar 07 12:25:39 PM PST 24 1205780144 ps
T893 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1293664472 Mar 07 12:25:56 PM PST 24 Mar 07 12:25:56 PM PST 24 447009012 ps
T894 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3726442531 Mar 07 12:26:09 PM PST 24 Mar 07 12:26:30 PM PST 24 7550200440 ps
T895 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2216908264 Mar 07 12:25:15 PM PST 24 Mar 07 12:25:17 PM PST 24 455696832 ps
T114 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.522170304 Mar 07 12:26:21 PM PST 24 Mar 07 12:26:51 PM PST 24 13232914689 ps
T66 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.4088625124 Mar 07 12:26:18 PM PST 24 Mar 07 12:26:31 PM PST 24 8464137090 ps
T896 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3522279562 Mar 07 12:25:15 PM PST 24 Mar 07 12:25:22 PM PST 24 4558485752 ps
T897 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2419360409 Mar 07 12:26:43 PM PST 24 Mar 07 12:26:51 PM PST 24 2959230703 ps
T898 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3037889579 Mar 07 12:26:01 PM PST 24 Mar 07 12:26:05 PM PST 24 2162396407 ps
T899 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3531206150 Mar 07 12:25:43 PM PST 24 Mar 07 12:25:44 PM PST 24 293455642 ps
T900 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1872000530 Mar 07 12:25:11 PM PST 24 Mar 07 12:25:30 PM PST 24 4652462795 ps
T901 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.47978590 Mar 07 12:25:52 PM PST 24 Mar 07 12:25:53 PM PST 24 465135810 ps
T902 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1109932504 Mar 07 12:26:34 PM PST 24 Mar 07 12:26:37 PM PST 24 446943790 ps
T115 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2118811688 Mar 07 12:25:25 PM PST 24 Mar 07 12:25:30 PM PST 24 943875484 ps
T903 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1766099076 Mar 07 12:26:22 PM PST 24 Mar 07 12:26:24 PM PST 24 513734139 ps
T904 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1501958975 Mar 07 12:25:43 PM PST 24 Mar 07 12:25:45 PM PST 24 305594148 ps
T905 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2727895178 Mar 07 12:25:33 PM PST 24 Mar 07 12:25:38 PM PST 24 2514415137 ps
T906 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1780563426 Mar 07 12:25:59 PM PST 24 Mar 07 12:26:01 PM PST 24 364336935 ps
T907 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2597725884 Mar 07 12:25:23 PM PST 24 Mar 07 12:25:25 PM PST 24 801621270 ps
T908 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3339323338 Mar 07 12:25:28 PM PST 24 Mar 07 12:26:20 PM PST 24 27167306924 ps
T909 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1394113092 Mar 07 12:25:25 PM PST 24 Mar 07 12:25:27 PM PST 24 521863054 ps
T116 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3605517648 Mar 07 12:25:37 PM PST 24 Mar 07 12:27:31 PM PST 24 50096972754 ps
T910 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1482452287 Mar 07 12:26:07 PM PST 24 Mar 07 12:26:08 PM PST 24 413372002 ps
T911 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3104376586 Mar 07 12:25:58 PM PST 24 Mar 07 12:26:01 PM PST 24 438049187 ps
T912 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.914854040 Mar 07 12:25:37 PM PST 24 Mar 07 12:25:39 PM PST 24 366791457 ps
T913 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2300591678 Mar 07 12:27:29 PM PST 24 Mar 07 12:27:30 PM PST 24 385661483 ps
T330 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.113631710 Mar 07 12:25:22 PM PST 24 Mar 07 12:25:34 PM PST 24 4267559235 ps

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.394195059
Short name T1
Test name
Test status
Simulation time 60577801138 ps
CPU time 166.23 seconds
Started Mar 07 12:34:18 PM PST 24
Finished Mar 07 12:37:07 PM PST 24
Peak memory 210076 kb
Host smart-272d984c-3c48-486c-a3a0-0d866ff495d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394195059 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.394195059
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2529556477
Short name T11
Test name
Test status
Simulation time 486423444254 ps
CPU time 695.88 seconds
Started Mar 07 12:34:21 PM PST 24
Finished Mar 07 12:45:57 PM PST 24
Peak memory 201188 kb
Host smart-a1d1b8b0-76b1-45c6-83b8-cce3806ecbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529556477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2529556477
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.477272901
Short name T35
Test name
Test status
Simulation time 593010172613 ps
CPU time 382.05 seconds
Started Mar 07 12:35:31 PM PST 24
Finished Mar 07 12:41:53 PM PST 24
Peak memory 210160 kb
Host smart-178e1217-d5d2-42cc-899a-3c24bf4e8a1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477272901 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.477272901
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.11182930
Short name T3
Test name
Test status
Simulation time 532803973789 ps
CPU time 295.39 seconds
Started Mar 07 12:34:42 PM PST 24
Finished Mar 07 12:39:39 PM PST 24
Peak memory 201316 kb
Host smart-0321c578-2e4d-43e8-9923-c490f6c286d7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11182930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_w
akeup.11182930
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.3846952997
Short name T186
Test name
Test status
Simulation time 431345559034 ps
CPU time 1292.65 seconds
Started Mar 07 12:34:08 PM PST 24
Finished Mar 07 12:55:42 PM PST 24
Peak memory 212184 kb
Host smart-8a0dfd5e-7612-4a83-bfe9-3554ad1b50ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846952997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.3846952997
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.290501458
Short name T16
Test name
Test status
Simulation time 170716988862 ps
CPU time 152.08 seconds
Started Mar 07 12:33:20 PM PST 24
Finished Mar 07 12:35:53 PM PST 24
Peak memory 210096 kb
Host smart-406c8280-0f22-4e23-9836-9fb55c094613
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290501458 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.290501458
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.332799291
Short name T125
Test name
Test status
Simulation time 508571349733 ps
CPU time 325.47 seconds
Started Mar 07 12:36:19 PM PST 24
Finished Mar 07 12:41:44 PM PST 24
Peak memory 201304 kb
Host smart-7d671349-ee34-4069-bb25-5c0e90b7e9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332799291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.332799291
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.2032433578
Short name T212
Test name
Test status
Simulation time 512610530800 ps
CPU time 1214.93 seconds
Started Mar 07 12:33:23 PM PST 24
Finished Mar 07 12:53:38 PM PST 24
Peak memory 201404 kb
Host smart-7ab2590f-7b3a-4344-9fed-f57961230187
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032433578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.2032433578
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1718413717
Short name T222
Test name
Test status
Simulation time 539951843669 ps
CPU time 1183.63 seconds
Started Mar 07 12:33:22 PM PST 24
Finished Mar 07 12:53:06 PM PST 24
Peak memory 201292 kb
Host smart-4ce4aec7-1a74-46fc-9a6c-af05dbff2ea4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718413717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1718413717
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1980272208
Short name T204
Test name
Test status
Simulation time 506992199145 ps
CPU time 604.21 seconds
Started Mar 07 12:33:46 PM PST 24
Finished Mar 07 12:43:50 PM PST 24
Peak memory 201388 kb
Host smart-91dbe704-fa79-41f1-a214-adcd40c3260e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980272208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1980272208
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3389226830
Short name T59
Test name
Test status
Simulation time 1025561211 ps
CPU time 3.43 seconds
Started Mar 07 12:25:19 PM PST 24
Finished Mar 07 12:25:24 PM PST 24
Peak memory 217924 kb
Host smart-1474ec42-1556-417a-ad21-04eb2c00dfc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389226830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3389226830
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.121037683
Short name T127
Test name
Test status
Simulation time 527272340557 ps
CPU time 251.97 seconds
Started Mar 07 12:33:52 PM PST 24
Finished Mar 07 12:38:04 PM PST 24
Peak memory 201368 kb
Host smart-82d099e5-10b9-4d35-84d9-0d7081ba8895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121037683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.121037683
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2962296348
Short name T56
Test name
Test status
Simulation time 8200821152 ps
CPU time 19.98 seconds
Started Mar 07 12:33:32 PM PST 24
Finished Mar 07 12:33:53 PM PST 24
Peak memory 216616 kb
Host smart-0ee7b8d5-c332-434d-82a7-9db6f2d3535c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962296348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2962296348
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.4095467131
Short name T126
Test name
Test status
Simulation time 554327995506 ps
CPU time 356.32 seconds
Started Mar 07 12:34:09 PM PST 24
Finished Mar 07 12:40:06 PM PST 24
Peak memory 201372 kb
Host smart-07701224-69ac-45b7-a3ec-c9760b8d450d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095467131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.4095467131
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1683042764
Short name T4
Test name
Test status
Simulation time 593514968926 ps
CPU time 132.26 seconds
Started Mar 07 12:33:43 PM PST 24
Finished Mar 07 12:35:55 PM PST 24
Peak memory 201328 kb
Host smart-c9831acf-b1de-449d-8470-8c2dc97b245c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683042764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1683042764
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.760049321
Short name T132
Test name
Test status
Simulation time 521838671864 ps
CPU time 1203.29 seconds
Started Mar 07 12:34:03 PM PST 24
Finished Mar 07 12:54:07 PM PST 24
Peak memory 201320 kb
Host smart-d7fc0cc5-6684-4e1d-9feb-3bf30eca7f5f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760049321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.760049321
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2074423376
Short name T137
Test name
Test status
Simulation time 503724865949 ps
CPU time 543.39 seconds
Started Mar 07 12:34:13 PM PST 24
Finished Mar 07 12:43:17 PM PST 24
Peak memory 201304 kb
Host smart-1d9c43d9-09fc-4f56-9cc4-28676bb69ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074423376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2074423376
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.345375096
Short name T159
Test name
Test status
Simulation time 331584419737 ps
CPU time 87.2 seconds
Started Mar 07 12:33:52 PM PST 24
Finished Mar 07 12:35:20 PM PST 24
Peak memory 201288 kb
Host smart-0947b8f6-aa5c-4a09-9f24-22a175db368f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345375096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.345375096
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3422443318
Short name T105
Test name
Test status
Simulation time 583632595 ps
CPU time 1.17 seconds
Started Mar 07 12:25:25 PM PST 24
Finished Mar 07 12:25:26 PM PST 24
Peak memory 201340 kb
Host smart-02e1e2df-7f67-4faa-ae7f-2f3bb19c5c73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422443318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3422443318
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3988195072
Short name T177
Test name
Test status
Simulation time 537506503408 ps
CPU time 299.54 seconds
Started Mar 07 12:34:29 PM PST 24
Finished Mar 07 12:39:29 PM PST 24
Peak memory 201328 kb
Host smart-21c47cce-3fc1-4670-ac93-b17439af03a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988195072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3988195072
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3130330836
Short name T244
Test name
Test status
Simulation time 491020547376 ps
CPU time 1185.51 seconds
Started Mar 07 12:33:44 PM PST 24
Finished Mar 07 12:53:30 PM PST 24
Peak memory 201488 kb
Host smart-3cc244a7-f27f-4e6b-b9d4-874b821653a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130330836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3130330836
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3401270372
Short name T300
Test name
Test status
Simulation time 530746883607 ps
CPU time 1304.04 seconds
Started Mar 07 12:34:48 PM PST 24
Finished Mar 07 12:56:32 PM PST 24
Peak memory 201316 kb
Host smart-d9d51096-f705-48a4-a7f5-942542240bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401270372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3401270372
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2833258745
Short name T33
Test name
Test status
Simulation time 127388847034 ps
CPU time 311.3 seconds
Started Mar 07 12:34:08 PM PST 24
Finished Mar 07 12:39:20 PM PST 24
Peak memory 210128 kb
Host smart-ac18a27b-59a2-423b-aa75-33fb61a97ca1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833258745 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2833258745
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1170699080
Short name T141
Test name
Test status
Simulation time 493870083150 ps
CPU time 378.26 seconds
Started Mar 07 12:35:27 PM PST 24
Finished Mar 07 12:41:45 PM PST 24
Peak memory 201352 kb
Host smart-c2cbcf35-0a34-439b-86e5-69d99e7457ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170699080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1170699080
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.4155975234
Short name T267
Test name
Test status
Simulation time 162663614512 ps
CPU time 108.37 seconds
Started Mar 07 12:33:43 PM PST 24
Finished Mar 07 12:35:32 PM PST 24
Peak memory 201284 kb
Host smart-7e85c92e-b606-482c-a502-5b46b5d8db56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155975234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.4155975234
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3087279329
Short name T257
Test name
Test status
Simulation time 527552965292 ps
CPU time 1226.3 seconds
Started Mar 07 12:35:41 PM PST 24
Finished Mar 07 12:56:08 PM PST 24
Peak memory 200968 kb
Host smart-d5be9351-2218-4e78-b2de-5a8101695b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087279329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3087279329
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.4044031879
Short name T174
Test name
Test status
Simulation time 495482660113 ps
CPU time 263.36 seconds
Started Mar 07 12:34:38 PM PST 24
Finished Mar 07 12:39:04 PM PST 24
Peak memory 201308 kb
Host smart-14bcfd54-df88-43f0-b559-c58819dbebe5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044031879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.4044031879
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1854476849
Short name T241
Test name
Test status
Simulation time 436818598407 ps
CPU time 160.81 seconds
Started Mar 07 12:33:22 PM PST 24
Finished Mar 07 12:36:03 PM PST 24
Peak memory 210068 kb
Host smart-e029a9aa-02e5-4f65-a834-2dd78ce8ad6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854476849 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1854476849
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1991024596
Short name T67
Test name
Test status
Simulation time 445640567 ps
CPU time 1.51 seconds
Started Mar 07 12:33:56 PM PST 24
Finished Mar 07 12:33:58 PM PST 24
Peak memory 201104 kb
Host smart-22832dde-0166-4038-a656-e62091ca30a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991024596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1991024596
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1327762143
Short name T47
Test name
Test status
Simulation time 2172404214 ps
CPU time 2.33 seconds
Started Mar 07 12:25:24 PM PST 24
Finished Mar 07 12:25:27 PM PST 24
Peak memory 201260 kb
Host smart-3d26f074-0e08-4b4b-9ec2-8180f168e031
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327762143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1327762143
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2781284396
Short name T52
Test name
Test status
Simulation time 7986455789 ps
CPU time 17.13 seconds
Started Mar 07 12:25:40 PM PST 24
Finished Mar 07 12:25:58 PM PST 24
Peak memory 201620 kb
Host smart-5c6ae9df-604a-46e2-8d6a-9848888d1411
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781284396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2781284396
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.894465551
Short name T138
Test name
Test status
Simulation time 494746463883 ps
CPU time 283.14 seconds
Started Mar 07 12:33:34 PM PST 24
Finished Mar 07 12:38:17 PM PST 24
Peak memory 201320 kb
Host smart-81f9298a-8eb2-42e2-9ed5-74b539d579e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894465551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.894465551
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.1887356385
Short name T251
Test name
Test status
Simulation time 485925340152 ps
CPU time 296.61 seconds
Started Mar 07 12:34:46 PM PST 24
Finished Mar 07 12:39:43 PM PST 24
Peak memory 201304 kb
Host smart-793cdd67-becd-49b1-8252-4bccf25c6e17
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887356385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.1887356385
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3071198742
Short name T178
Test name
Test status
Simulation time 341390316511 ps
CPU time 115.27 seconds
Started Mar 07 12:33:55 PM PST 24
Finished Mar 07 12:35:51 PM PST 24
Peak memory 201248 kb
Host smart-1a56be07-4574-47f4-93b2-e94b3dfeb4b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071198742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3071198742
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.282035963
Short name T140
Test name
Test status
Simulation time 327870111374 ps
CPU time 721.22 seconds
Started Mar 07 12:33:35 PM PST 24
Finished Mar 07 12:45:36 PM PST 24
Peak memory 201320 kb
Host smart-d36a22ba-8e97-492a-b1b6-d02634464bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282035963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.282035963
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1368798645
Short name T129
Test name
Test status
Simulation time 363312015067 ps
CPU time 216.41 seconds
Started Mar 07 12:33:57 PM PST 24
Finished Mar 07 12:37:33 PM PST 24
Peak memory 201372 kb
Host smart-94f0a21a-f797-43b3-a745-bb6044cf0c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368798645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1368798645
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3255196399
Short name T266
Test name
Test status
Simulation time 302477796597 ps
CPU time 450.84 seconds
Started Mar 07 12:33:15 PM PST 24
Finished Mar 07 12:40:46 PM PST 24
Peak memory 211100 kb
Host smart-f8422462-0204-49bb-b0a3-69272d63c341
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255196399 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3255196399
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1293730838
Short name T284
Test name
Test status
Simulation time 412154249549 ps
CPU time 212.73 seconds
Started Mar 07 12:35:47 PM PST 24
Finished Mar 07 12:39:20 PM PST 24
Peak memory 210096 kb
Host smart-c62eb81c-b401-4eb6-9996-fb005dff9963
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293730838 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1293730838
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3788062457
Short name T70
Test name
Test status
Simulation time 495855033294 ps
CPU time 614.37 seconds
Started Mar 07 12:34:16 PM PST 24
Finished Mar 07 12:44:35 PM PST 24
Peak memory 201308 kb
Host smart-2be29f2d-b414-46af-b882-5b07351d56e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788062457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3788062457
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.1110746798
Short name T278
Test name
Test status
Simulation time 544113264453 ps
CPU time 1201.77 seconds
Started Mar 07 12:34:42 PM PST 24
Finished Mar 07 12:54:45 PM PST 24
Peak memory 201316 kb
Host smart-7bd31bc1-8ad4-491a-973e-2549cab042a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110746798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1110746798
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2709116224
Short name T281
Test name
Test status
Simulation time 527354062805 ps
CPU time 626.94 seconds
Started Mar 07 12:34:00 PM PST 24
Finished Mar 07 12:44:27 PM PST 24
Peak memory 201416 kb
Host smart-8db07fa2-1d79-4524-aa82-bfdffdaead46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709116224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2709116224
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1940755212
Short name T271
Test name
Test status
Simulation time 51313303678 ps
CPU time 122.71 seconds
Started Mar 07 12:33:33 PM PST 24
Finished Mar 07 12:35:36 PM PST 24
Peak memory 209264 kb
Host smart-fb25a8f2-9500-4167-bd01-6feb2a5cdeae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940755212 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1940755212
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3791382476
Short name T250
Test name
Test status
Simulation time 561765945959 ps
CPU time 1246.98 seconds
Started Mar 07 12:33:24 PM PST 24
Finished Mar 07 12:54:11 PM PST 24
Peak memory 200656 kb
Host smart-ab78abb5-d8ec-4458-948c-783a1d3110b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791382476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3791382476
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.1015492771
Short name T324
Test name
Test status
Simulation time 619974414066 ps
CPU time 484.3 seconds
Started Mar 07 12:34:39 PM PST 24
Finished Mar 07 12:42:46 PM PST 24
Peak memory 201360 kb
Host smart-ed7f451b-183a-4436-a06a-d71eef6cf851
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015492771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.1015492771
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1440802193
Short name T85
Test name
Test status
Simulation time 556586560704 ps
CPU time 143.95 seconds
Started Mar 07 12:33:57 PM PST 24
Finished Mar 07 12:36:22 PM PST 24
Peak memory 201324 kb
Host smart-67f0a84f-8415-4c75-94e7-6f34091f2106
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440802193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1440802193
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3344270822
Short name T229
Test name
Test status
Simulation time 435116561794 ps
CPU time 941.61 seconds
Started Mar 07 12:34:37 PM PST 24
Finished Mar 07 12:50:19 PM PST 24
Peak memory 201200 kb
Host smart-2dc1f6a4-b7c5-400c-9697-cc77b8b9f64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344270822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3344270822
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2244621208
Short name T205
Test name
Test status
Simulation time 344099795899 ps
CPU time 216.21 seconds
Started Mar 07 12:35:39 PM PST 24
Finished Mar 07 12:39:15 PM PST 24
Peak memory 201120 kb
Host smart-a8992377-80ca-414b-97cc-8a02c4771847
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244621208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2244621208
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.880723102
Short name T197
Test name
Test status
Simulation time 436505247797 ps
CPU time 1255.67 seconds
Started Mar 07 12:33:25 PM PST 24
Finished Mar 07 12:54:21 PM PST 24
Peak memory 213008 kb
Host smart-5c46c108-4ac0-4fa7-a2e4-b2a6f032f821
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880723102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.
880723102
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.205901695
Short name T34
Test name
Test status
Simulation time 68066468829 ps
CPU time 164.2 seconds
Started Mar 07 12:35:32 PM PST 24
Finished Mar 07 12:38:17 PM PST 24
Peak memory 209040 kb
Host smart-e15f57b7-3a2b-4148-b247-6740487bfc5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205901695 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.205901695
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2406105135
Short name T239
Test name
Test status
Simulation time 351066554442 ps
CPU time 883.66 seconds
Started Mar 07 12:36:07 PM PST 24
Finished Mar 07 12:50:55 PM PST 24
Peak memory 201308 kb
Host smart-4884a5b3-f31c-44ea-aca0-d8f5d45477d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406105135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2406105135
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1656509673
Short name T219
Test name
Test status
Simulation time 169657251955 ps
CPU time 55.89 seconds
Started Mar 07 12:33:18 PM PST 24
Finished Mar 07 12:34:14 PM PST 24
Peak memory 201332 kb
Host smart-c8417507-ce13-4f95-a1eb-05c7e29fb1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656509673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1656509673
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2188705788
Short name T283
Test name
Test status
Simulation time 508745937814 ps
CPU time 261.45 seconds
Started Mar 07 12:33:58 PM PST 24
Finished Mar 07 12:38:20 PM PST 24
Peak memory 201296 kb
Host smart-1832249c-02a2-4fba-b5a2-491a6641766e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188705788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2188705788
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3261853833
Short name T195
Test name
Test status
Simulation time 120162232931 ps
CPU time 347.97 seconds
Started Mar 07 12:34:09 PM PST 24
Finished Mar 07 12:39:57 PM PST 24
Peak memory 218156 kb
Host smart-97ee9eab-6cc4-4d8a-a50c-9b6387fa85a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261853833 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3261853833
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.1789647349
Short name T318
Test name
Test status
Simulation time 168255613508 ps
CPU time 295.98 seconds
Started Mar 07 12:33:14 PM PST 24
Finished Mar 07 12:38:10 PM PST 24
Peak memory 201292 kb
Host smart-c7208596-92fb-4d28-96a2-e3257ee8dd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789647349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1789647349
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1149034694
Short name T293
Test name
Test status
Simulation time 493853189455 ps
CPU time 312.35 seconds
Started Mar 07 12:34:27 PM PST 24
Finished Mar 07 12:39:40 PM PST 24
Peak memory 201324 kb
Host smart-3c98f9c9-0811-4992-a8d4-24cf69cf1e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149034694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1149034694
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3325743325
Short name T299
Test name
Test status
Simulation time 327008793306 ps
CPU time 305.84 seconds
Started Mar 07 12:34:28 PM PST 24
Finished Mar 07 12:39:34 PM PST 24
Peak memory 201380 kb
Host smart-36745cd6-4f2f-44ce-a974-fe7dc86a7881
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325743325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3325743325
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.4150154314
Short name T216
Test name
Test status
Simulation time 246650420221 ps
CPU time 415.32 seconds
Started Mar 07 12:35:16 PM PST 24
Finished Mar 07 12:42:12 PM PST 24
Peak memory 201696 kb
Host smart-8f96cfe1-f58f-4010-95ed-58a16fe40af6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150154314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.4150154314
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2285795429
Short name T289
Test name
Test status
Simulation time 735746326622 ps
CPU time 2085.38 seconds
Started Mar 07 12:35:37 PM PST 24
Finished Mar 07 01:10:23 PM PST 24
Peak memory 212744 kb
Host smart-2ac8012f-0207-4035-9c6b-858a22062dfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285795429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2285795429
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3056030301
Short name T134
Test name
Test status
Simulation time 343749403699 ps
CPU time 109.5 seconds
Started Mar 07 12:33:17 PM PST 24
Finished Mar 07 12:35:06 PM PST 24
Peak memory 201348 kb
Host smart-09c01fa5-304c-4c68-ac6a-d748a6d14743
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056030301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3056030301
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3177384654
Short name T269
Test name
Test status
Simulation time 275302641552 ps
CPU time 1001.76 seconds
Started Mar 07 12:34:34 PM PST 24
Finished Mar 07 12:51:16 PM PST 24
Peak memory 211928 kb
Host smart-f250c602-1f8d-45f3-b143-57b2514d39bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177384654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3177384654
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1052322791
Short name T263
Test name
Test status
Simulation time 168067400200 ps
CPU time 203.67 seconds
Started Mar 07 12:36:15 PM PST 24
Finished Mar 07 12:39:39 PM PST 24
Peak memory 201284 kb
Host smart-1faae491-2a9b-446d-a289-b056681c01ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052322791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1052322791
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1997554276
Short name T249
Test name
Test status
Simulation time 345507649313 ps
CPU time 303.5 seconds
Started Mar 07 12:33:23 PM PST 24
Finished Mar 07 12:38:27 PM PST 24
Peak memory 201272 kb
Host smart-f60e50ab-95ad-478c-a323-64c6d1ff9fc4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997554276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1997554276
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.4262086241
Short name T171
Test name
Test status
Simulation time 488166828668 ps
CPU time 279.1 seconds
Started Mar 07 12:33:37 PM PST 24
Finished Mar 07 12:38:16 PM PST 24
Peak memory 201308 kb
Host smart-640ac911-847e-49c4-9a7e-d355d6a097c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262086241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.4262086241
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3929840937
Short name T275
Test name
Test status
Simulation time 489332675998 ps
CPU time 1187.91 seconds
Started Mar 07 12:33:38 PM PST 24
Finished Mar 07 12:53:27 PM PST 24
Peak memory 201384 kb
Host smart-5fe9cc17-bbe0-4178-afe9-fd8f98cf4ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929840937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3929840937
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3368899336
Short name T194
Test name
Test status
Simulation time 85065020739 ps
CPU time 495.15 seconds
Started Mar 07 12:33:59 PM PST 24
Finished Mar 07 12:42:14 PM PST 24
Peak memory 201668 kb
Host smart-88f2bbed-4159-482a-9c78-08f660f83b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368899336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3368899336
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.156836024
Short name T280
Test name
Test status
Simulation time 368727491970 ps
CPU time 219.35 seconds
Started Mar 07 12:34:19 PM PST 24
Finished Mar 07 12:38:00 PM PST 24
Peak memory 201076 kb
Host smart-f372cdc7-8e91-4ba8-b94e-e8622ae49546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156836024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
156836024
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1875086898
Short name T332
Test name
Test status
Simulation time 360336197492 ps
CPU time 561.43 seconds
Started Mar 07 12:34:09 PM PST 24
Finished Mar 07 12:43:31 PM PST 24
Peak memory 201760 kb
Host smart-2e1b45ba-268c-4340-8b9e-91a81537e135
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875086898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1875086898
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.237097707
Short name T169
Test name
Test status
Simulation time 557013281802 ps
CPU time 310.17 seconds
Started Mar 07 12:34:55 PM PST 24
Finished Mar 07 12:40:07 PM PST 24
Peak memory 201308 kb
Host smart-82f66a2a-a551-48bb-b576-db705f573ac2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237097707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gati
ng.237097707
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.506824263
Short name T185
Test name
Test status
Simulation time 87091231547 ps
CPU time 294.79 seconds
Started Mar 07 12:35:41 PM PST 24
Finished Mar 07 12:40:35 PM PST 24
Peak memory 201644 kb
Host smart-c11e6fa6-f73f-48c4-951c-db4b1abe4744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506824263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.506824263
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3726442531
Short name T894
Test name
Test status
Simulation time 7550200440 ps
CPU time 20.64 seconds
Started Mar 07 12:26:09 PM PST 24
Finished Mar 07 12:26:30 PM PST 24
Peak memory 201684 kb
Host smart-a4f46f0a-2ef7-4028-9fe6-ab8c8ab0acb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726442531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3726442531
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.4088625124
Short name T66
Test name
Test status
Simulation time 8464137090 ps
CPU time 12.87 seconds
Started Mar 07 12:26:18 PM PST 24
Finished Mar 07 12:26:31 PM PST 24
Peak memory 200120 kb
Host smart-2a4e6edf-305d-474a-b739-250c8f591a46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088625124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.4088625124
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3461437418
Short name T26
Test name
Test status
Simulation time 328595124395 ps
CPU time 185.19 seconds
Started Mar 07 12:33:31 PM PST 24
Finished Mar 07 12:36:36 PM PST 24
Peak memory 201308 kb
Host smart-236c2dde-3cf8-4c39-9c1a-26f17c38c73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461437418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3461437418
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.313325722
Short name T477
Test name
Test status
Simulation time 203336584780 ps
CPU time 123.79 seconds
Started Mar 07 12:33:39 PM PST 24
Finished Mar 07 12:35:43 PM PST 24
Peak memory 201304 kb
Host smart-dcb3f333-803e-450c-99d7-bf37ccfd8caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313325722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.313325722
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3978570787
Short name T155
Test name
Test status
Simulation time 495861108105 ps
CPU time 1073.1 seconds
Started Mar 07 12:33:52 PM PST 24
Finished Mar 07 12:51:46 PM PST 24
Peak memory 201248 kb
Host smart-e8d598bf-8de7-4061-a204-52826f539ed8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978570787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3978570787
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.138933748
Short name T78
Test name
Test status
Simulation time 51869569081 ps
CPU time 196.32 seconds
Started Mar 07 12:33:53 PM PST 24
Finished Mar 07 12:37:12 PM PST 24
Peak memory 216084 kb
Host smart-f5974796-378b-407c-841d-7c331e885e2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138933748 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.138933748
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1130925040
Short name T306
Test name
Test status
Simulation time 517078013865 ps
CPU time 1243.22 seconds
Started Mar 07 12:33:56 PM PST 24
Finished Mar 07 12:54:40 PM PST 24
Peak memory 201328 kb
Host smart-b939d1cf-35ad-4586-b449-7e323bb493bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130925040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1130925040
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.537102993
Short name T549
Test name
Test status
Simulation time 184955359678 ps
CPU time 424.88 seconds
Started Mar 07 12:33:23 PM PST 24
Finished Mar 07 12:40:28 PM PST 24
Peak memory 201252 kb
Host smart-6f991d4a-2f18-4499-9164-57de57ce1494
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537102993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.537102993
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2775899968
Short name T314
Test name
Test status
Simulation time 322237230083 ps
CPU time 394.62 seconds
Started Mar 07 12:34:24 PM PST 24
Finished Mar 07 12:40:59 PM PST 24
Peak memory 201308 kb
Host smart-96815c51-ca4e-4628-b474-a8134b7a443b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775899968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2775899968
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3695822830
Short name T287
Test name
Test status
Simulation time 506655623638 ps
CPU time 330.81 seconds
Started Mar 07 12:34:21 PM PST 24
Finished Mar 07 12:39:52 PM PST 24
Peak memory 201224 kb
Host smart-446ab590-f2b0-4e72-b537-7b62dbe219dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695822830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3695822830
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3215675662
Short name T243
Test name
Test status
Simulation time 352981332838 ps
CPU time 441.55 seconds
Started Mar 07 12:35:05 PM PST 24
Finished Mar 07 12:42:27 PM PST 24
Peak memory 201300 kb
Host smart-69d93c44-8b48-49a8-a57b-bccc531b5bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215675662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3215675662
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.988340842
Short name T191
Test name
Test status
Simulation time 88985972476 ps
CPU time 476.87 seconds
Started Mar 07 12:35:28 PM PST 24
Finished Mar 07 12:43:25 PM PST 24
Peak memory 201732 kb
Host smart-1104ed80-3b96-43ae-adef-685822f9a535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988340842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.988340842
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1154533411
Short name T162
Test name
Test status
Simulation time 365610984634 ps
CPU time 206.24 seconds
Started Mar 07 12:36:07 PM PST 24
Finished Mar 07 12:39:37 PM PST 24
Peak memory 201396 kb
Host smart-9113eb3e-3bab-4ee1-9dcd-cfdac6b13891
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154533411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.1154533411
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.650843869
Short name T113
Test name
Test status
Simulation time 673411479 ps
CPU time 2.23 seconds
Started Mar 07 12:26:16 PM PST 24
Finished Mar 07 12:26:18 PM PST 24
Peak memory 201560 kb
Host smart-820b74ae-71fa-4202-9bfa-3ab81d3c0789
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650843869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.650843869
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2877620821
Short name T890
Test name
Test status
Simulation time 26082406147 ps
CPU time 80.11 seconds
Started Mar 07 12:25:15 PM PST 24
Finished Mar 07 12:26:37 PM PST 24
Peak memory 201604 kb
Host smart-dfb2f89f-ff0f-4ac9-bd90-7cdf32c48c53
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877620821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2877620821
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2735497305
Short name T841
Test name
Test status
Simulation time 1329452046 ps
CPU time 3.72 seconds
Started Mar 07 12:25:59 PM PST 24
Finished Mar 07 12:26:02 PM PST 24
Peak memory 201260 kb
Host smart-89c4f20e-5667-4c7c-807d-7a59bf8307ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735497305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2735497305
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.753408457
Short name T807
Test name
Test status
Simulation time 643708102 ps
CPU time 1.38 seconds
Started Mar 07 12:25:05 PM PST 24
Finished Mar 07 12:25:07 PM PST 24
Peak memory 201480 kb
Host smart-d8138b69-35cd-4c10-aaac-58777278c2ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753408457 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.753408457
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2896694143
Short name T118
Test name
Test status
Simulation time 380614438 ps
CPU time 1.18 seconds
Started Mar 07 12:25:16 PM PST 24
Finished Mar 07 12:25:20 PM PST 24
Peak memory 201292 kb
Host smart-a2096ac1-31da-4af5-84d2-dd7366d6d9ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896694143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2896694143
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3173148229
Short name T836
Test name
Test status
Simulation time 374497438 ps
CPU time 1.68 seconds
Started Mar 07 12:26:17 PM PST 24
Finished Mar 07 12:26:19 PM PST 24
Peak memory 201284 kb
Host smart-990825db-c8c2-4cf8-b3a8-eab54b1532cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173148229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3173148229
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1872000530
Short name T900
Test name
Test status
Simulation time 4652462795 ps
CPU time 18.9 seconds
Started Mar 07 12:25:11 PM PST 24
Finished Mar 07 12:25:30 PM PST 24
Peak memory 201608 kb
Host smart-8a6c1ce8-c855-4650-a94c-8543cd647929
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872000530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.1872000530
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.4073289965
Short name T811
Test name
Test status
Simulation time 714682711 ps
CPU time 1.94 seconds
Started Mar 07 12:25:15 PM PST 24
Finished Mar 07 12:25:17 PM PST 24
Peak memory 201636 kb
Host smart-262101da-e896-4055-bd26-4d6ad4bfeff4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073289965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.4073289965
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3522279562
Short name T896
Test name
Test status
Simulation time 4558485752 ps
CPU time 6.62 seconds
Started Mar 07 12:25:15 PM PST 24
Finished Mar 07 12:25:22 PM PST 24
Peak memory 201604 kb
Host smart-bf473f09-f585-4236-8144-c257871ba7b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522279562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3522279562
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2118811688
Short name T115
Test name
Test status
Simulation time 943875484 ps
CPU time 4.35 seconds
Started Mar 07 12:25:25 PM PST 24
Finished Mar 07 12:25:30 PM PST 24
Peak memory 201604 kb
Host smart-1b43f197-1f9d-4a07-bffb-a64fdb3277dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118811688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.2118811688
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3339323338
Short name T908
Test name
Test status
Simulation time 27167306924 ps
CPU time 52.31 seconds
Started Mar 07 12:25:28 PM PST 24
Finished Mar 07 12:26:20 PM PST 24
Peak memory 201592 kb
Host smart-90a6f1f0-ad09-4231-8de6-c1285b54591d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339323338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3339323338
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2597725884
Short name T907
Test name
Test status
Simulation time 801621270 ps
CPU time 1.17 seconds
Started Mar 07 12:25:23 PM PST 24
Finished Mar 07 12:25:25 PM PST 24
Peak memory 201436 kb
Host smart-d5375f95-4c54-4bd9-9f43-8b1472a5bf9c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597725884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2597725884
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.99600270
Short name T878
Test name
Test status
Simulation time 388634725 ps
CPU time 1.94 seconds
Started Mar 07 12:25:23 PM PST 24
Finished Mar 07 12:25:26 PM PST 24
Peak memory 201488 kb
Host smart-8570b52b-1b3f-449e-ab5a-9613d084a422
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99600270 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.99600270
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2801519980
Short name T120
Test name
Test status
Simulation time 307406892 ps
CPU time 1.48 seconds
Started Mar 07 12:25:21 PM PST 24
Finished Mar 07 12:25:23 PM PST 24
Peak memory 201332 kb
Host smart-17b30881-4686-4e65-869d-3b4731297cde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801519980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2801519980
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1975619838
Short name T824
Test name
Test status
Simulation time 541136943 ps
CPU time 0.81 seconds
Started Mar 07 12:25:15 PM PST 24
Finished Mar 07 12:25:17 PM PST 24
Peak memory 201256 kb
Host smart-070ebbd8-ac58-4d95-87ac-ae321b91aeae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975619838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1975619838
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.112911499
Short name T871
Test name
Test status
Simulation time 620278979 ps
CPU time 4.06 seconds
Started Mar 07 12:25:07 PM PST 24
Finished Mar 07 12:25:11 PM PST 24
Peak memory 217260 kb
Host smart-29fab869-3425-4197-a283-9f5c1b78ee61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112911499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.112911499
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1489960011
Short name T880
Test name
Test status
Simulation time 602244585 ps
CPU time 1.27 seconds
Started Mar 07 12:25:35 PM PST 24
Finished Mar 07 12:25:37 PM PST 24
Peak memory 201096 kb
Host smart-1ce2506f-3012-4e51-8ebd-008699ae2027
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489960011 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1489960011
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.609980313
Short name T111
Test name
Test status
Simulation time 445728461 ps
CPU time 1.75 seconds
Started Mar 07 12:25:43 PM PST 24
Finished Mar 07 12:25:45 PM PST 24
Peak memory 201208 kb
Host smart-5f0aabeb-b738-4d7c-85b6-0f0112e054f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609980313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.609980313
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2707286889
Short name T792
Test name
Test status
Simulation time 358813639 ps
CPU time 1.08 seconds
Started Mar 07 12:26:00 PM PST 24
Finished Mar 07 12:26:01 PM PST 24
Peak memory 201292 kb
Host smart-fa3e3173-4aa6-461b-8a73-40519ed05cce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707286889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2707286889
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2231927659
Short name T866
Test name
Test status
Simulation time 2001676921 ps
CPU time 10.33 seconds
Started Mar 07 12:25:43 PM PST 24
Finished Mar 07 12:25:53 PM PST 24
Peak memory 201312 kb
Host smart-d2d8fd38-a5cb-42f5-a5c7-df519d62173b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231927659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2231927659
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1783608295
Short name T859
Test name
Test status
Simulation time 478564149 ps
CPU time 1.88 seconds
Started Mar 07 12:26:10 PM PST 24
Finished Mar 07 12:26:12 PM PST 24
Peak memory 218036 kb
Host smart-c5e46848-27f1-40c6-8ac5-d00f8ecd5adb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783608295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1783608295
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1146870109
Short name T53
Test name
Test status
Simulation time 4213853446 ps
CPU time 6.24 seconds
Started Mar 07 12:26:21 PM PST 24
Finished Mar 07 12:26:27 PM PST 24
Peak memory 201596 kb
Host smart-8c173722-81c1-462d-99d8-cff62e038ba5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146870109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1146870109
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2585179042
Short name T804
Test name
Test status
Simulation time 703303309 ps
CPU time 1.25 seconds
Started Mar 07 12:25:51 PM PST 24
Finished Mar 07 12:25:52 PM PST 24
Peak memory 201228 kb
Host smart-7102b561-1744-450c-99de-5137aa566f61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585179042 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2585179042
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3286786509
Short name T107
Test name
Test status
Simulation time 397042607 ps
CPU time 1.18 seconds
Started Mar 07 12:25:45 PM PST 24
Finished Mar 07 12:25:47 PM PST 24
Peak memory 201168 kb
Host smart-215f6e3d-d399-48ea-af9b-f930e9b00a70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286786509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3286786509
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2824787696
Short name T865
Test name
Test status
Simulation time 411850400 ps
CPU time 1.65 seconds
Started Mar 07 12:25:48 PM PST 24
Finished Mar 07 12:25:50 PM PST 24
Peak memory 201308 kb
Host smart-4ca9cd92-9bfb-41d8-ab91-8c9298c9b37f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824787696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2824787696
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1483411312
Short name T48
Test name
Test status
Simulation time 4114514176 ps
CPU time 16.39 seconds
Started Mar 07 12:26:02 PM PST 24
Finished Mar 07 12:26:19 PM PST 24
Peak memory 201644 kb
Host smart-11dc8760-036b-4a72-9056-90aff760f6d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483411312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1483411312
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1408618347
Short name T826
Test name
Test status
Simulation time 740174071 ps
CPU time 1.99 seconds
Started Mar 07 12:25:40 PM PST 24
Finished Mar 07 12:25:42 PM PST 24
Peak memory 201568 kb
Host smart-e7d9fffd-731c-4b00-9b10-87ede991a4e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408618347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1408618347
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3739317079
Short name T328
Test name
Test status
Simulation time 8214935802 ps
CPU time 7.37 seconds
Started Mar 07 12:25:32 PM PST 24
Finished Mar 07 12:25:40 PM PST 24
Peak memory 201160 kb
Host smart-945398df-9b82-441c-a525-70510717c6dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739317079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3739317079
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3883140049
Short name T89
Test name
Test status
Simulation time 528324273 ps
CPU time 1.42 seconds
Started Mar 07 12:25:51 PM PST 24
Finished Mar 07 12:25:52 PM PST 24
Peak memory 201228 kb
Host smart-e81f2ec7-ec15-4fbb-9e09-987f50d67d3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883140049 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.3883140049
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2139595291
Short name T860
Test name
Test status
Simulation time 564630103 ps
CPU time 0.81 seconds
Started Mar 07 12:26:46 PM PST 24
Finished Mar 07 12:26:47 PM PST 24
Peak memory 201248 kb
Host smart-cebaf311-4ae2-4b3e-b3ea-e1812fb5802f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139595291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.2139595291
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2327307603
Short name T854
Test name
Test status
Simulation time 320782123 ps
CPU time 1.03 seconds
Started Mar 07 12:26:46 PM PST 24
Finished Mar 07 12:26:48 PM PST 24
Peak memory 201224 kb
Host smart-f52b7940-4230-4e6b-a10c-1594aa9481cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327307603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2327307603
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3037889579
Short name T898
Test name
Test status
Simulation time 2162396407 ps
CPU time 3.59 seconds
Started Mar 07 12:26:01 PM PST 24
Finished Mar 07 12:26:05 PM PST 24
Peak memory 201396 kb
Host smart-7ddd116d-b5b2-40aa-9206-be0ae117e11a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037889579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3037889579
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.903280141
Short name T803
Test name
Test status
Simulation time 577620378 ps
CPU time 1.53 seconds
Started Mar 07 12:25:50 PM PST 24
Finished Mar 07 12:25:52 PM PST 24
Peak memory 201412 kb
Host smart-3656dfc4-9b24-41ca-b52a-7b4495d1394a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903280141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.903280141
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3523697952
Short name T844
Test name
Test status
Simulation time 434584389 ps
CPU time 1.5 seconds
Started Mar 07 12:26:07 PM PST 24
Finished Mar 07 12:26:08 PM PST 24
Peak memory 201196 kb
Host smart-94b8f833-156c-4b68-b08c-3c28f1061fcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523697952 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3523697952
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.385367090
Short name T117
Test name
Test status
Simulation time 545481870 ps
CPU time 1.45 seconds
Started Mar 07 12:26:23 PM PST 24
Finished Mar 07 12:26:25 PM PST 24
Peak memory 201332 kb
Host smart-6b1ad171-f36f-451f-9a2d-9088d710be87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385367090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.385367090
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.4164517090
Short name T802
Test name
Test status
Simulation time 659490566 ps
CPU time 0.8 seconds
Started Mar 07 12:26:30 PM PST 24
Finished Mar 07 12:26:30 PM PST 24
Peak memory 201296 kb
Host smart-ddbff5df-77ec-4596-be2c-9c1ed98deb98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164517090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.4164517090
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.955809507
Short name T846
Test name
Test status
Simulation time 5124189454 ps
CPU time 2.03 seconds
Started Mar 07 12:26:14 PM PST 24
Finished Mar 07 12:26:16 PM PST 24
Peak memory 201512 kb
Host smart-f36257ae-5736-415e-b302-b8697a1d5261
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955809507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.955809507
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3694303028
Short name T837
Test name
Test status
Simulation time 305048684 ps
CPU time 2.67 seconds
Started Mar 07 12:26:11 PM PST 24
Finished Mar 07 12:26:15 PM PST 24
Peak memory 201612 kb
Host smart-75d632d7-deb3-415e-b950-911b97120cc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694303028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3694303028
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2876074094
Short name T827
Test name
Test status
Simulation time 4581778569 ps
CPU time 7.41 seconds
Started Mar 07 12:26:56 PM PST 24
Finished Mar 07 12:27:04 PM PST 24
Peak memory 200288 kb
Host smart-0c8fe702-414c-44cb-bf9a-8e082314b759
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876074094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.2876074094
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1928770414
Short name T90
Test name
Test status
Simulation time 472367956 ps
CPU time 1.91 seconds
Started Mar 07 12:26:24 PM PST 24
Finished Mar 07 12:26:26 PM PST 24
Peak memory 201384 kb
Host smart-88669824-7873-469f-9473-2544e2c2cc6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928770414 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1928770414
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1657448443
Short name T121
Test name
Test status
Simulation time 330577678 ps
CPU time 1.59 seconds
Started Mar 07 12:25:50 PM PST 24
Finished Mar 07 12:25:52 PM PST 24
Peak memory 201204 kb
Host smart-725fa2fa-7f67-4e3e-9d3b-c2717d0343d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657448443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1657448443
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.4052414605
Short name T822
Test name
Test status
Simulation time 384787349 ps
CPU time 0.94 seconds
Started Mar 07 12:26:02 PM PST 24
Finished Mar 07 12:26:03 PM PST 24
Peak memory 201120 kb
Host smart-7b5ca9e2-1d88-4d9c-95ab-d7093fde586c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052414605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.4052414605
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2858053307
Short name T882
Test name
Test status
Simulation time 1991406606 ps
CPU time 2.07 seconds
Started Mar 07 12:25:50 PM PST 24
Finished Mar 07 12:25:52 PM PST 24
Peak memory 201124 kb
Host smart-8edca1ee-9f90-4550-bda4-9ce089c1fa55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858053307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2858053307
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1769401286
Short name T61
Test name
Test status
Simulation time 413377538 ps
CPU time 1.98 seconds
Started Mar 07 12:25:50 PM PST 24
Finished Mar 07 12:25:52 PM PST 24
Peak memory 210652 kb
Host smart-24020cbb-4234-43f8-a483-95453b158404
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769401286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1769401286
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3322009172
Short name T889
Test name
Test status
Simulation time 7889435294 ps
CPU time 21.99 seconds
Started Mar 07 12:26:00 PM PST 24
Finished Mar 07 12:26:22 PM PST 24
Peak memory 201588 kb
Host smart-c3322395-e96b-4e60-bb8a-25866284b0e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322009172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3322009172
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3235360601
Short name T54
Test name
Test status
Simulation time 549698254 ps
CPU time 1.58 seconds
Started Mar 07 12:26:47 PM PST 24
Finished Mar 07 12:26:49 PM PST 24
Peak memory 209808 kb
Host smart-ff4e9344-e4ca-45e4-8aa8-760b15d0e21a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235360601 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3235360601
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1780563426
Short name T906
Test name
Test status
Simulation time 364336935 ps
CPU time 1.81 seconds
Started Mar 07 12:25:59 PM PST 24
Finished Mar 07 12:26:01 PM PST 24
Peak memory 201248 kb
Host smart-a22ecf76-0773-4688-8b87-ebc2299e0aac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780563426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1780563426
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1293664472
Short name T893
Test name
Test status
Simulation time 447009012 ps
CPU time 0.72 seconds
Started Mar 07 12:25:56 PM PST 24
Finished Mar 07 12:25:56 PM PST 24
Peak memory 201268 kb
Host smart-51dacbd8-c404-4d6c-b074-084255be1519
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293664472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1293664472
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3657913394
Short name T49
Test name
Test status
Simulation time 2431177024 ps
CPU time 1.55 seconds
Started Mar 07 12:25:58 PM PST 24
Finished Mar 07 12:26:00 PM PST 24
Peak memory 201372 kb
Host smart-94a28454-aa70-4ab2-ba34-e710302537b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657913394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.3657913394
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.895568995
Short name T62
Test name
Test status
Simulation time 437997405 ps
CPU time 2.85 seconds
Started Mar 07 12:25:50 PM PST 24
Finished Mar 07 12:25:53 PM PST 24
Peak memory 210620 kb
Host smart-5ec85761-b7bf-4ec2-9c45-e5ca33d99b30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895568995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.895568995
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.4282776737
Short name T327
Test name
Test status
Simulation time 4318499997 ps
CPU time 6.42 seconds
Started Mar 07 12:25:50 PM PST 24
Finished Mar 07 12:25:57 PM PST 24
Peak memory 201476 kb
Host smart-ebb87ebf-29c2-4c43-b05b-835bb120ca66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282776737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.4282776737
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1964620947
Short name T79
Test name
Test status
Simulation time 419412601 ps
CPU time 0.96 seconds
Started Mar 07 12:25:59 PM PST 24
Finished Mar 07 12:26:00 PM PST 24
Peak memory 201368 kb
Host smart-a98f4c15-d4c6-4d79-834d-011da988bee2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964620947 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.1964620947
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2030708887
Short name T112
Test name
Test status
Simulation time 441702122 ps
CPU time 1.36 seconds
Started Mar 07 12:25:53 PM PST 24
Finished Mar 07 12:25:55 PM PST 24
Peak memory 201316 kb
Host smart-a0c81070-981a-43ee-bffd-c58ba906ed0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030708887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2030708887
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.47978590
Short name T901
Test name
Test status
Simulation time 465135810 ps
CPU time 0.88 seconds
Started Mar 07 12:25:52 PM PST 24
Finished Mar 07 12:25:53 PM PST 24
Peak memory 201268 kb
Host smart-99150efa-728e-44e1-8e0c-05a11d32774f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47978590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.47978590
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.4095814828
Short name T858
Test name
Test status
Simulation time 4591134682 ps
CPU time 4.74 seconds
Started Mar 07 12:26:00 PM PST 24
Finished Mar 07 12:26:05 PM PST 24
Peak memory 200284 kb
Host smart-ae22fee1-0d36-4ce3-bf98-6404854c1792
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095814828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.4095814828
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.880762782
Short name T883
Test name
Test status
Simulation time 474631745 ps
CPU time 2.56 seconds
Started Mar 07 12:26:22 PM PST 24
Finished Mar 07 12:26:25 PM PST 24
Peak memory 201580 kb
Host smart-2d8a36ae-810a-4f48-8ddf-bb0a5890808c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880762782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.880762782
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.318977405
Short name T829
Test name
Test status
Simulation time 4600574018 ps
CPU time 4.42 seconds
Started Mar 07 12:25:54 PM PST 24
Finished Mar 07 12:25:59 PM PST 24
Peak memory 201716 kb
Host smart-c831dd9d-de2c-48f1-85b7-fe565aa5b1ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318977405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_in
tg_err.318977405
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.358092152
Short name T820
Test name
Test status
Simulation time 406472131 ps
CPU time 1.33 seconds
Started Mar 07 12:25:58 PM PST 24
Finished Mar 07 12:25:59 PM PST 24
Peak memory 201376 kb
Host smart-1c782b33-0251-4b3c-b278-39ada5e5898e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358092152 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.358092152
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.4051405901
Short name T835
Test name
Test status
Simulation time 515206315 ps
CPU time 1.96 seconds
Started Mar 07 12:26:45 PM PST 24
Finished Mar 07 12:26:47 PM PST 24
Peak memory 201248 kb
Host smart-18f19841-c393-4507-a2f6-e2c15d8785b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051405901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.4051405901
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4289386608
Short name T885
Test name
Test status
Simulation time 419617231 ps
CPU time 1.72 seconds
Started Mar 07 12:26:43 PM PST 24
Finished Mar 07 12:26:45 PM PST 24
Peak memory 201356 kb
Host smart-66e5dd80-af16-448c-88fd-26ed5086db69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289386608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.4289386608
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1026668934
Short name T887
Test name
Test status
Simulation time 2257462531 ps
CPU time 1.75 seconds
Started Mar 07 12:26:18 PM PST 24
Finished Mar 07 12:26:20 PM PST 24
Peak memory 199908 kb
Host smart-82176e33-9278-44c2-a0cb-1794b9385ec4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026668934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1026668934
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1766099076
Short name T903
Test name
Test status
Simulation time 513734139 ps
CPU time 1.52 seconds
Started Mar 07 12:26:22 PM PST 24
Finished Mar 07 12:26:24 PM PST 24
Peak memory 201580 kb
Host smart-5206af6d-1150-4abc-9ab8-badfce4a8aa1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766099076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1766099076
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3051254321
Short name T843
Test name
Test status
Simulation time 4404492910 ps
CPU time 7.06 seconds
Started Mar 07 12:26:43 PM PST 24
Finished Mar 07 12:26:51 PM PST 24
Peak memory 201588 kb
Host smart-cea5c5a1-e4b5-475d-b371-24de3326c5a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051254321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3051254321
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.562046852
Short name T851
Test name
Test status
Simulation time 620871864 ps
CPU time 1.33 seconds
Started Mar 07 12:25:58 PM PST 24
Finished Mar 07 12:25:59 PM PST 24
Peak memory 201376 kb
Host smart-8bb4fe97-2b7b-4370-9703-719aff8e45c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562046852 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.562046852
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3315132503
Short name T104
Test name
Test status
Simulation time 385131682 ps
CPU time 1.22 seconds
Started Mar 07 12:26:01 PM PST 24
Finished Mar 07 12:26:02 PM PST 24
Peak memory 200880 kb
Host smart-e3e5de61-4eec-4981-b4ab-902ec3ee0793
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315132503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3315132503
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3358900057
Short name T810
Test name
Test status
Simulation time 586752305 ps
CPU time 0.73 seconds
Started Mar 07 12:26:43 PM PST 24
Finished Mar 07 12:26:44 PM PST 24
Peak memory 201408 kb
Host smart-918252d7-9e46-4050-ae69-b8e18e128b24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358900057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3358900057
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2419360409
Short name T897
Test name
Test status
Simulation time 2959230703 ps
CPU time 8.17 seconds
Started Mar 07 12:26:43 PM PST 24
Finished Mar 07 12:26:51 PM PST 24
Peak memory 201496 kb
Host smart-7f866de8-b7fd-433e-99d9-32060ea37332
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419360409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2419360409
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2106795714
Short name T833
Test name
Test status
Simulation time 420869072 ps
CPU time 1.65 seconds
Started Mar 07 12:26:30 PM PST 24
Finished Mar 07 12:26:32 PM PST 24
Peak memory 201512 kb
Host smart-6663ad67-3dc2-42d7-a84f-fa1d5378a17f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106795714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.2106795714
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2041065119
Short name T886
Test name
Test status
Simulation time 8154102511 ps
CPU time 12.59 seconds
Started Mar 07 12:26:28 PM PST 24
Finished Mar 07 12:26:41 PM PST 24
Peak memory 201640 kb
Host smart-9f5b4ff6-e365-4bc3-a2df-0b6cd1404805
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041065119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2041065119
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2439627395
Short name T805
Test name
Test status
Simulation time 610641474 ps
CPU time 1.3 seconds
Started Mar 07 12:25:56 PM PST 24
Finished Mar 07 12:25:57 PM PST 24
Peak memory 201324 kb
Host smart-a674ae51-3aba-4b93-bb31-ab0c3ac2dba6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439627395 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2439627395
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2050796652
Short name T119
Test name
Test status
Simulation time 477740737 ps
CPU time 1.1 seconds
Started Mar 07 12:26:00 PM PST 24
Finished Mar 07 12:26:01 PM PST 24
Peak memory 199964 kb
Host smart-8660d72d-b7ee-48eb-a96c-e10a7d6a456e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050796652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2050796652
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.45166183
Short name T797
Test name
Test status
Simulation time 351284422 ps
CPU time 1.01 seconds
Started Mar 07 12:25:58 PM PST 24
Finished Mar 07 12:25:59 PM PST 24
Peak memory 201296 kb
Host smart-c833cbc8-58ed-4da2-a2fd-8f8ffc52f69b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45166183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.45166183
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.563083319
Short name T864
Test name
Test status
Simulation time 4813297201 ps
CPU time 3.37 seconds
Started Mar 07 12:26:41 PM PST 24
Finished Mar 07 12:26:45 PM PST 24
Peak memory 201560 kb
Host smart-573b4137-1b3a-4692-aa81-fce279755d38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563083319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.563083319
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1383910354
Short name T60
Test name
Test status
Simulation time 610562503 ps
CPU time 3.13 seconds
Started Mar 07 12:26:41 PM PST 24
Finished Mar 07 12:26:44 PM PST 24
Peak memory 210820 kb
Host smart-ebf41fc6-1dde-4b61-8ec7-f71326c49c51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383910354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1383910354
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2253510933
Short name T870
Test name
Test status
Simulation time 8416467243 ps
CPU time 7.59 seconds
Started Mar 07 12:26:42 PM PST 24
Finished Mar 07 12:26:49 PM PST 24
Peak memory 201628 kb
Host smart-11b2f8e8-675e-4d8a-8002-54cf4387b162
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253510933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2253510933
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2657711705
Short name T110
Test name
Test status
Simulation time 1015883290 ps
CPU time 3 seconds
Started Mar 07 12:26:08 PM PST 24
Finished Mar 07 12:26:11 PM PST 24
Peak memory 201564 kb
Host smart-99ae9302-547c-45f6-b708-0ad7ab358bbc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657711705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2657711705
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2116059928
Short name T109
Test name
Test status
Simulation time 50743133481 ps
CPU time 75.57 seconds
Started Mar 07 12:25:21 PM PST 24
Finished Mar 07 12:26:37 PM PST 24
Peak memory 201448 kb
Host smart-0f8a2ecd-3615-4140-81c9-822803d6dc9b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116059928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2116059928
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.14893406
Short name T868
Test name
Test status
Simulation time 868159441 ps
CPU time 2.67 seconds
Started Mar 07 12:25:31 PM PST 24
Finished Mar 07 12:25:34 PM PST 24
Peak memory 201248 kb
Host smart-19ec1e7f-ae50-4fe1-b698-66797abf393a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14893406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_res
et.14893406
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2391823383
Short name T819
Test name
Test status
Simulation time 320988069 ps
CPU time 1.58 seconds
Started Mar 07 12:25:50 PM PST 24
Finished Mar 07 12:25:51 PM PST 24
Peak memory 201380 kb
Host smart-1b171a5d-e6aa-427f-99ee-80c3994a366a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391823383 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2391823383
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1790768605
Short name T800
Test name
Test status
Simulation time 352361172 ps
CPU time 0.78 seconds
Started Mar 07 12:25:18 PM PST 24
Finished Mar 07 12:25:21 PM PST 24
Peak memory 201148 kb
Host smart-60256e5f-1c43-4f42-bf89-a50e34e74065
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790768605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1790768605
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1449409418
Short name T847
Test name
Test status
Simulation time 5291611387 ps
CPU time 21.72 seconds
Started Mar 07 12:25:22 PM PST 24
Finished Mar 07 12:25:44 PM PST 24
Peak memory 201588 kb
Host smart-171aac8e-32f6-4947-9d8a-c8bcd580918e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449409418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1449409418
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1038453087
Short name T848
Test name
Test status
Simulation time 610380354 ps
CPU time 1.72 seconds
Started Mar 07 12:25:24 PM PST 24
Finished Mar 07 12:25:26 PM PST 24
Peak memory 201588 kb
Host smart-7043bf0f-897f-41fe-88f2-3217f2ddf31c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038453087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1038453087
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1436114503
Short name T329
Test name
Test status
Simulation time 8649188067 ps
CPU time 22.46 seconds
Started Mar 07 12:25:34 PM PST 24
Finished Mar 07 12:25:56 PM PST 24
Peak memory 201564 kb
Host smart-1d19e516-4ed4-44ef-8ab4-eb6b704bc71d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436114503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1436114503
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3012352471
Short name T840
Test name
Test status
Simulation time 405762627 ps
CPU time 1.5 seconds
Started Mar 07 12:25:59 PM PST 24
Finished Mar 07 12:26:01 PM PST 24
Peak memory 201152 kb
Host smart-8355ea72-80af-403d-bf63-9efd0d537d32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012352471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3012352471
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4073460789
Short name T888
Test name
Test status
Simulation time 379467593 ps
CPU time 1.53 seconds
Started Mar 07 12:26:46 PM PST 24
Finished Mar 07 12:26:49 PM PST 24
Peak memory 201136 kb
Host smart-b951c0d0-1f4c-419e-bc97-429d6c8bba5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073460789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.4073460789
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2063724756
Short name T830
Test name
Test status
Simulation time 418233600 ps
CPU time 0.9 seconds
Started Mar 07 12:26:41 PM PST 24
Finished Mar 07 12:26:42 PM PST 24
Peak memory 201276 kb
Host smart-7e0f27f9-f893-4718-8706-3bed15352f3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063724756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2063724756
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3195781841
Short name T849
Test name
Test status
Simulation time 393643020 ps
CPU time 1.27 seconds
Started Mar 07 12:25:59 PM PST 24
Finished Mar 07 12:26:00 PM PST 24
Peak memory 201164 kb
Host smart-dd15cc1d-828e-487d-9224-bb5309501b74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195781841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3195781841
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3839378449
Short name T884
Test name
Test status
Simulation time 380587202 ps
CPU time 1.54 seconds
Started Mar 07 12:25:56 PM PST 24
Finished Mar 07 12:25:57 PM PST 24
Peak memory 201224 kb
Host smart-30291061-854c-4f07-bc2c-8ce4b55556c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839378449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3839378449
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2609487375
Short name T809
Test name
Test status
Simulation time 558553238 ps
CPU time 0.74 seconds
Started Mar 07 12:26:30 PM PST 24
Finished Mar 07 12:26:31 PM PST 24
Peak memory 201196 kb
Host smart-c232d705-2e9d-4a09-8c9c-2cbcd73e2ac5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609487375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2609487375
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3750869554
Short name T798
Test name
Test status
Simulation time 553740789 ps
CPU time 0.87 seconds
Started Mar 07 12:25:59 PM PST 24
Finished Mar 07 12:26:00 PM PST 24
Peak memory 201200 kb
Host smart-5559d908-1c51-4841-ab32-5da035851a6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750869554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.3750869554
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3889027250
Short name T823
Test name
Test status
Simulation time 375142646 ps
CPU time 1.26 seconds
Started Mar 07 12:25:55 PM PST 24
Finished Mar 07 12:25:57 PM PST 24
Peak memory 201288 kb
Host smart-8e82033a-3550-4fac-8cd7-95b6bcb0c457
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889027250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3889027250
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2730306844
Short name T812
Test name
Test status
Simulation time 451571818 ps
CPU time 0.93 seconds
Started Mar 07 12:26:42 PM PST 24
Finished Mar 07 12:26:43 PM PST 24
Peak memory 201332 kb
Host smart-83a45d60-8b5e-4006-a198-e3f4644659da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730306844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2730306844
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2765303037
Short name T828
Test name
Test status
Simulation time 419635217 ps
CPU time 1.51 seconds
Started Mar 07 12:26:08 PM PST 24
Finished Mar 07 12:26:09 PM PST 24
Peak memory 201136 kb
Host smart-05d7bc52-8f21-436b-a75e-28960cd3eba5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765303037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2765303037
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2285315655
Short name T106
Test name
Test status
Simulation time 971396199 ps
CPU time 4.27 seconds
Started Mar 07 12:25:24 PM PST 24
Finished Mar 07 12:25:29 PM PST 24
Peak memory 201408 kb
Host smart-0d8a0f06-b669-436b-b379-07fe5f01ca28
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285315655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2285315655
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3605517648
Short name T116
Test name
Test status
Simulation time 50096972754 ps
CPU time 113.72 seconds
Started Mar 07 12:25:37 PM PST 24
Finished Mar 07 12:27:31 PM PST 24
Peak memory 201532 kb
Host smart-259c0e30-0ee3-471b-946f-a9d1590afb21
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605517648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3605517648
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1072373645
Short name T815
Test name
Test status
Simulation time 874746555 ps
CPU time 1.1 seconds
Started Mar 07 12:26:01 PM PST 24
Finished Mar 07 12:26:02 PM PST 24
Peak memory 201348 kb
Host smart-bc371ff8-6d64-4e2b-a76f-8c80477ed28c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072373645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1072373645
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3871787157
Short name T875
Test name
Test status
Simulation time 600223453 ps
CPU time 0.93 seconds
Started Mar 07 12:26:17 PM PST 24
Finished Mar 07 12:26:18 PM PST 24
Peak memory 201384 kb
Host smart-207d0a10-1712-421d-81b9-052c1940894d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871787157 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3871787157
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3815018421
Short name T825
Test name
Test status
Simulation time 418499071 ps
CPU time 1.78 seconds
Started Mar 07 12:25:19 PM PST 24
Finished Mar 07 12:25:23 PM PST 24
Peak memory 201352 kb
Host smart-a89d6e06-c35f-4b9d-aed0-9e988a6dbcdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815018421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3815018421
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1009628480
Short name T856
Test name
Test status
Simulation time 340651151 ps
CPU time 1.47 seconds
Started Mar 07 12:25:16 PM PST 24
Finished Mar 07 12:25:19 PM PST 24
Peak memory 201200 kb
Host smart-8d3a6c6d-fe77-4aea-86ce-acb13207688e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009628480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1009628480
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1746694136
Short name T832
Test name
Test status
Simulation time 4503552032 ps
CPU time 4.78 seconds
Started Mar 07 12:25:25 PM PST 24
Finished Mar 07 12:25:30 PM PST 24
Peak memory 201572 kb
Host smart-3f669fbd-e3a9-4461-8102-c33e09346174
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746694136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.1746694136
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.8174433
Short name T855
Test name
Test status
Simulation time 8266791484 ps
CPU time 11.56 seconds
Started Mar 07 12:25:18 PM PST 24
Finished Mar 07 12:25:31 PM PST 24
Peak memory 201356 kb
Host smart-e301fd9e-25e9-4a38-85a8-2fba3b19d10f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8174433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_intg_
err.8174433
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3954159280
Short name T842
Test name
Test status
Simulation time 485090754 ps
CPU time 1.76 seconds
Started Mar 07 12:26:03 PM PST 24
Finished Mar 07 12:26:05 PM PST 24
Peak memory 201124 kb
Host smart-3aa4928f-8879-45b2-b2b0-807cb12959f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954159280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3954159280
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2619658436
Short name T881
Test name
Test status
Simulation time 364986737 ps
CPU time 1.61 seconds
Started Mar 07 12:26:56 PM PST 24
Finished Mar 07 12:26:58 PM PST 24
Peak memory 199972 kb
Host smart-2f3c2d8d-6522-429a-be59-0c63bad7b6ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619658436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.2619658436
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1070828291
Short name T796
Test name
Test status
Simulation time 371254488 ps
CPU time 1.07 seconds
Started Mar 07 12:26:04 PM PST 24
Finished Mar 07 12:26:05 PM PST 24
Peak memory 201240 kb
Host smart-0135a036-7c4e-448a-a237-48926c4c29cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070828291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1070828291
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.122056485
Short name T867
Test name
Test status
Simulation time 302681524 ps
CPU time 1.3 seconds
Started Mar 07 12:26:07 PM PST 24
Finished Mar 07 12:26:08 PM PST 24
Peak memory 201272 kb
Host smart-2af93f9b-4e24-4f0e-8755-fc8f2bbfddf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122056485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.122056485
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2300591678
Short name T913
Test name
Test status
Simulation time 385661483 ps
CPU time 1.63 seconds
Started Mar 07 12:27:29 PM PST 24
Finished Mar 07 12:27:30 PM PST 24
Peak memory 201244 kb
Host smart-3e4c5ed0-9f99-4522-8316-91860681281f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300591678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2300591678
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.323389488
Short name T799
Test name
Test status
Simulation time 335202713 ps
CPU time 1.3 seconds
Started Mar 07 12:27:15 PM PST 24
Finished Mar 07 12:27:17 PM PST 24
Peak memory 201132 kb
Host smart-8f4530ed-c6d0-4963-af9d-eece7811d884
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323389488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.323389488
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2525816963
Short name T793
Test name
Test status
Simulation time 441153378 ps
CPU time 1.72 seconds
Started Mar 07 12:26:33 PM PST 24
Finished Mar 07 12:26:35 PM PST 24
Peak memory 201224 kb
Host smart-f1b57b44-e4b3-4ddf-9e54-56b2209b0cac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525816963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2525816963
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3063183272
Short name T862
Test name
Test status
Simulation time 586483740 ps
CPU time 0.84 seconds
Started Mar 07 12:26:03 PM PST 24
Finished Mar 07 12:26:05 PM PST 24
Peak memory 200344 kb
Host smart-50484789-b068-45bb-9354-ad73ada275d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063183272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3063183272
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.234823614
Short name T861
Test name
Test status
Simulation time 365375208 ps
CPU time 0.77 seconds
Started Mar 07 12:26:05 PM PST 24
Finished Mar 07 12:26:06 PM PST 24
Peak memory 201304 kb
Host smart-da94bd78-c1bf-43d9-bc11-11ca84cc887f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234823614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.234823614
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.4027217745
Short name T853
Test name
Test status
Simulation time 418092043 ps
CPU time 1.74 seconds
Started Mar 07 12:27:12 PM PST 24
Finished Mar 07 12:27:14 PM PST 24
Peak memory 201332 kb
Host smart-c1ff2074-1587-4c57-afb9-01e4e46022c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027217745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.4027217745
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3725688953
Short name T892
Test name
Test status
Simulation time 1205780144 ps
CPU time 5.14 seconds
Started Mar 07 12:25:33 PM PST 24
Finished Mar 07 12:25:39 PM PST 24
Peak memory 201548 kb
Host smart-314e88b9-261e-4e69-9154-a1dc1845daa9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725688953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3725688953
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.522170304
Short name T114
Test name
Test status
Simulation time 13232914689 ps
CPU time 30.45 seconds
Started Mar 07 12:26:21 PM PST 24
Finished Mar 07 12:26:51 PM PST 24
Peak memory 201628 kb
Host smart-095c4059-7c36-44ad-8b70-fccfe167fa19
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522170304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_b
ash.522170304
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1309746870
Short name T122
Test name
Test status
Simulation time 1000543710 ps
CPU time 0.87 seconds
Started Mar 07 12:25:32 PM PST 24
Finished Mar 07 12:25:33 PM PST 24
Peak memory 201316 kb
Host smart-11a5ed75-08c2-426a-8228-62ed28410f92
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309746870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.1309746870
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3425763266
Short name T850
Test name
Test status
Simulation time 506810516 ps
CPU time 1.21 seconds
Started Mar 07 12:25:34 PM PST 24
Finished Mar 07 12:25:36 PM PST 24
Peak memory 200948 kb
Host smart-30ea473b-9cb6-4824-b11f-089293368e04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425763266 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3425763266
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.570469476
Short name T891
Test name
Test status
Simulation time 475139605 ps
CPU time 1.14 seconds
Started Mar 07 12:25:50 PM PST 24
Finished Mar 07 12:25:51 PM PST 24
Peak memory 201280 kb
Host smart-d16af0b3-dcc4-4482-b559-f2ad52417042
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570469476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.570469476
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2216908264
Short name T895
Test name
Test status
Simulation time 455696832 ps
CPU time 0.64 seconds
Started Mar 07 12:25:15 PM PST 24
Finished Mar 07 12:25:17 PM PST 24
Peak memory 201060 kb
Host smart-268f3d8b-6dcc-41f7-817c-c9d4a5194c08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216908264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2216908264
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.8218415
Short name T872
Test name
Test status
Simulation time 4410371530 ps
CPU time 10.56 seconds
Started Mar 07 12:25:43 PM PST 24
Finished Mar 07 12:25:54 PM PST 24
Peak memory 201544 kb
Host smart-5a8ec5fc-a9e6-4b9d-8f77-86c48f25235b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8218415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl
_same_csr_outstanding.8218415
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1394113092
Short name T909
Test name
Test status
Simulation time 521863054 ps
CPU time 2.56 seconds
Started Mar 07 12:25:25 PM PST 24
Finished Mar 07 12:25:27 PM PST 24
Peak memory 209788 kb
Host smart-5f4dc125-330f-47f2-875a-397c64ea31a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394113092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1394113092
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.113631710
Short name T330
Test name
Test status
Simulation time 4267559235 ps
CPU time 10.98 seconds
Started Mar 07 12:25:22 PM PST 24
Finished Mar 07 12:25:34 PM PST 24
Peak memory 201444 kb
Host smart-de4abb93-7189-49db-b2d6-49cd0992c3fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113631710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_int
g_err.113631710
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1314693150
Short name T863
Test name
Test status
Simulation time 284654840 ps
CPU time 1.34 seconds
Started Mar 07 12:27:05 PM PST 24
Finished Mar 07 12:27:07 PM PST 24
Peak memory 201280 kb
Host smart-2660e34c-6d44-403d-be46-9ba30b956b5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314693150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1314693150
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1510053433
Short name T808
Test name
Test status
Simulation time 309347492 ps
CPU time 0.79 seconds
Started Mar 07 12:26:01 PM PST 24
Finished Mar 07 12:26:02 PM PST 24
Peak memory 201124 kb
Host smart-e1ebaca5-2f7a-4eaf-a12e-b6bcc4f8a0d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510053433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1510053433
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.28315069
Short name T816
Test name
Test status
Simulation time 443950306 ps
CPU time 0.94 seconds
Started Mar 07 12:26:06 PM PST 24
Finished Mar 07 12:26:08 PM PST 24
Peak memory 201252 kb
Host smart-366e6489-fc23-453a-ae91-8460208a1f84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28315069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.28315069
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.511749259
Short name T869
Test name
Test status
Simulation time 456006336 ps
CPU time 0.89 seconds
Started Mar 07 12:27:15 PM PST 24
Finished Mar 07 12:27:16 PM PST 24
Peak memory 201152 kb
Host smart-08ae85d6-c731-4849-a2d7-d58a38cd65ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511749259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.511749259
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1787829223
Short name T813
Test name
Test status
Simulation time 377531283 ps
CPU time 0.89 seconds
Started Mar 07 12:26:27 PM PST 24
Finished Mar 07 12:26:28 PM PST 24
Peak memory 201236 kb
Host smart-462fe75e-3f15-4dc5-a87e-ce3ba11e0c91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787829223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1787829223
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.941414030
Short name T790
Test name
Test status
Simulation time 438916636 ps
CPU time 0.72 seconds
Started Mar 07 12:27:05 PM PST 24
Finished Mar 07 12:27:06 PM PST 24
Peak memory 201236 kb
Host smart-95d41f16-f935-408d-a3a9-acfbfb0de7f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941414030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.941414030
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2845908022
Short name T817
Test name
Test status
Simulation time 526490073 ps
CPU time 2.01 seconds
Started Mar 07 12:26:08 PM PST 24
Finished Mar 07 12:26:10 PM PST 24
Peak memory 201128 kb
Host smart-e737634b-96ca-40ff-aafd-c22b5cd51e61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845908022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.2845908022
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2844353400
Short name T795
Test name
Test status
Simulation time 524664203 ps
CPU time 0.9 seconds
Started Mar 07 12:26:55 PM PST 24
Finished Mar 07 12:26:57 PM PST 24
Peak memory 201364 kb
Host smart-3d6f5b35-4a43-49f8-a160-a9c79c74f32a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844353400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2844353400
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1482452287
Short name T910
Test name
Test status
Simulation time 413372002 ps
CPU time 0.96 seconds
Started Mar 07 12:26:07 PM PST 24
Finished Mar 07 12:26:08 PM PST 24
Peak memory 201256 kb
Host smart-039c512f-a490-46ff-babe-b9ac4aeb7488
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482452287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1482452287
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3139318218
Short name T834
Test name
Test status
Simulation time 416689884 ps
CPU time 1.64 seconds
Started Mar 07 12:26:02 PM PST 24
Finished Mar 07 12:26:04 PM PST 24
Peak memory 201256 kb
Host smart-de9dc911-8d56-4602-90e2-63723c7e1aec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139318218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3139318218
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2991868408
Short name T874
Test name
Test status
Simulation time 427696878 ps
CPU time 1.43 seconds
Started Mar 07 12:25:37 PM PST 24
Finished Mar 07 12:25:39 PM PST 24
Peak memory 201380 kb
Host smart-2e2e3905-8526-46ca-bd87-3e9bbfc982a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991868408 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2991868408
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3446232677
Short name T108
Test name
Test status
Simulation time 362947414 ps
CPU time 1.62 seconds
Started Mar 07 12:25:36 PM PST 24
Finished Mar 07 12:25:38 PM PST 24
Peak memory 201304 kb
Host smart-9a0a8af5-86a4-44de-837a-4cf9d51676f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446232677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3446232677
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.4189041053
Short name T845
Test name
Test status
Simulation time 427258364 ps
CPU time 0.96 seconds
Started Mar 07 12:26:30 PM PST 24
Finished Mar 07 12:26:31 PM PST 24
Peak memory 201280 kb
Host smart-35075352-b6fb-4ed6-a669-ef0e36f34e9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189041053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.4189041053
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1034359298
Short name T821
Test name
Test status
Simulation time 2509987953 ps
CPU time 3.94 seconds
Started Mar 07 12:25:35 PM PST 24
Finished Mar 07 12:25:39 PM PST 24
Peak memory 201372 kb
Host smart-fcdba42f-993d-4914-baeb-ebd20f4ce3ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034359298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.1034359298
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3104376586
Short name T911
Test name
Test status
Simulation time 438049187 ps
CPU time 2.45 seconds
Started Mar 07 12:25:58 PM PST 24
Finished Mar 07 12:26:01 PM PST 24
Peak memory 201552 kb
Host smart-4bab67c4-56ca-40dc-bcc5-150d0f27e4b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104376586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3104376586
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1418085663
Short name T51
Test name
Test status
Simulation time 4201177816 ps
CPU time 3.15 seconds
Started Mar 07 12:25:39 PM PST 24
Finished Mar 07 12:25:43 PM PST 24
Peak memory 201620 kb
Host smart-029d7a7d-1e9c-4f5a-8d74-c2b453d42fa8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418085663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1418085663
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2486701087
Short name T806
Test name
Test status
Simulation time 583203031 ps
CPU time 1.03 seconds
Started Mar 07 12:25:43 PM PST 24
Finished Mar 07 12:25:44 PM PST 24
Peak memory 201288 kb
Host smart-245920e5-e936-4a7a-9cea-d0cf5b5fec5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486701087 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2486701087
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.903487022
Short name T831
Test name
Test status
Simulation time 418913562 ps
CPU time 1.77 seconds
Started Mar 07 12:25:33 PM PST 24
Finished Mar 07 12:25:36 PM PST 24
Peak memory 199880 kb
Host smart-b9f96cc6-2242-4ca8-903e-3f6742af6f2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903487022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.903487022
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3531206150
Short name T899
Test name
Test status
Simulation time 293455642 ps
CPU time 1.41 seconds
Started Mar 07 12:25:43 PM PST 24
Finished Mar 07 12:25:44 PM PST 24
Peak memory 201268 kb
Host smart-fea2baa5-fc27-4190-b8ef-ae2146aae8de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531206150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3531206150
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2465948266
Short name T50
Test name
Test status
Simulation time 2593168234 ps
CPU time 9.4 seconds
Started Mar 07 12:25:36 PM PST 24
Finished Mar 07 12:25:46 PM PST 24
Peak memory 201260 kb
Host smart-ab371399-798e-4c50-8766-528a8f2d9078
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465948266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2465948266
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1501958975
Short name T904
Test name
Test status
Simulation time 305594148 ps
CPU time 2.6 seconds
Started Mar 07 12:25:43 PM PST 24
Finished Mar 07 12:25:45 PM PST 24
Peak memory 209816 kb
Host smart-49a6aad4-c838-4b04-846b-85f0fa8c8cbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501958975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1501958975
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2290521943
Short name T818
Test name
Test status
Simulation time 464605813 ps
CPU time 1.93 seconds
Started Mar 07 12:25:32 PM PST 24
Finished Mar 07 12:25:34 PM PST 24
Peak memory 200988 kb
Host smart-fdc2c2e6-5c53-4d62-81ed-41317ad0803c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290521943 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2290521943
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.4127151452
Short name T876
Test name
Test status
Simulation time 530096083 ps
CPU time 1.88 seconds
Started Mar 07 12:25:37 PM PST 24
Finished Mar 07 12:25:39 PM PST 24
Peak memory 201172 kb
Host smart-cfe360f0-b4b0-43a8-9e9f-061e9a2c32db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127151452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.4127151452
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1109932504
Short name T902
Test name
Test status
Simulation time 446943790 ps
CPU time 1.9 seconds
Started Mar 07 12:26:34 PM PST 24
Finished Mar 07 12:26:37 PM PST 24
Peak memory 201256 kb
Host smart-1f74bad4-80f3-4931-875f-8e360ec87ad2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109932504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1109932504
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2169088347
Short name T873
Test name
Test status
Simulation time 4961276158 ps
CPU time 3.63 seconds
Started Mar 07 12:26:09 PM PST 24
Finished Mar 07 12:26:13 PM PST 24
Peak memory 201628 kb
Host smart-533803b0-7bbf-4bf3-b5bf-169d4fe5e6cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169088347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2169088347
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.4143397646
Short name T55
Test name
Test status
Simulation time 627977332 ps
CPU time 2.4 seconds
Started Mar 07 12:25:35 PM PST 24
Finished Mar 07 12:25:38 PM PST 24
Peak memory 201464 kb
Host smart-f257d4ab-2f88-41d1-bc52-91b37050a249
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143397646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.4143397646
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.84992362
Short name T877
Test name
Test status
Simulation time 4032204470 ps
CPU time 4.1 seconds
Started Mar 07 12:25:49 PM PST 24
Finished Mar 07 12:25:54 PM PST 24
Peak memory 201532 kb
Host smart-a7327aaa-9bfc-4436-8bab-f8f2bc86c08f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84992362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_intg
_err.84992362
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3493045012
Short name T814
Test name
Test status
Simulation time 504181863 ps
CPU time 1.43 seconds
Started Mar 07 12:25:32 PM PST 24
Finished Mar 07 12:25:33 PM PST 24
Peak memory 200868 kb
Host smart-640ac9aa-8349-41bb-8e89-8f51186d48c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493045012 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3493045012
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.830998006
Short name T857
Test name
Test status
Simulation time 580369572 ps
CPU time 1.34 seconds
Started Mar 07 12:25:43 PM PST 24
Finished Mar 07 12:25:44 PM PST 24
Peak memory 201208 kb
Host smart-16236f52-528b-4781-98c5-9c25007821e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830998006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.830998006
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.4245102958
Short name T791
Test name
Test status
Simulation time 463174896 ps
CPU time 0.94 seconds
Started Mar 07 12:26:01 PM PST 24
Finished Mar 07 12:26:02 PM PST 24
Peak memory 201324 kb
Host smart-ecbe0de9-8d92-4204-a497-6e6ff61abc94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245102958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.4245102958
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3445851633
Short name T839
Test name
Test status
Simulation time 4542161674 ps
CPU time 5.18 seconds
Started Mar 07 12:25:40 PM PST 24
Finished Mar 07 12:25:45 PM PST 24
Peak memory 201592 kb
Host smart-6b7fc515-3da9-4629-ac57-ca6df9a9c9f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445851633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3445851633
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.106530615
Short name T852
Test name
Test status
Simulation time 601223087 ps
CPU time 2.35 seconds
Started Mar 07 12:25:53 PM PST 24
Finished Mar 07 12:25:55 PM PST 24
Peak memory 217736 kb
Host smart-8791fdc3-426b-4a3b-befd-5130c2574a3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106530615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.106530615
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.4218527366
Short name T838
Test name
Test status
Simulation time 3987627867 ps
CPU time 11.24 seconds
Started Mar 07 12:26:17 PM PST 24
Finished Mar 07 12:26:28 PM PST 24
Peak memory 201560 kb
Host smart-51469d47-5270-4ebf-982a-42037b5c3bf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218527366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.4218527366
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2679885575
Short name T801
Test name
Test status
Simulation time 496500342 ps
CPU time 1.41 seconds
Started Mar 07 12:25:43 PM PST 24
Finished Mar 07 12:25:44 PM PST 24
Peak memory 201288 kb
Host smart-5463bf50-b74e-4f97-9ad9-b4ed55815dc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679885575 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2679885575
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.914854040
Short name T912
Test name
Test status
Simulation time 366791457 ps
CPU time 1.66 seconds
Started Mar 07 12:25:37 PM PST 24
Finished Mar 07 12:25:39 PM PST 24
Peak memory 201172 kb
Host smart-153309f0-8c29-4a92-89c9-320004b6f363
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914854040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.914854040
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.960966492
Short name T794
Test name
Test status
Simulation time 330104145 ps
CPU time 0.83 seconds
Started Mar 07 12:25:43 PM PST 24
Finished Mar 07 12:25:44 PM PST 24
Peak memory 201168 kb
Host smart-678635c5-efa9-48f0-84a7-9a94b80afdb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960966492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.960966492
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2727895178
Short name T905
Test name
Test status
Simulation time 2514415137 ps
CPU time 3.95 seconds
Started Mar 07 12:25:33 PM PST 24
Finished Mar 07 12:25:38 PM PST 24
Peak memory 200024 kb
Host smart-7dfbdd0f-9d40-402f-a168-bea3f6e59260
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727895178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2727895178
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1555106764
Short name T65
Test name
Test status
Simulation time 512662305 ps
CPU time 1.83 seconds
Started Mar 07 12:25:35 PM PST 24
Finished Mar 07 12:25:37 PM PST 24
Peak memory 201264 kb
Host smart-c0a6c39f-5772-4932-9c77-3857191a9c6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555106764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1555106764
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1512006414
Short name T879
Test name
Test status
Simulation time 4187152826 ps
CPU time 11.21 seconds
Started Mar 07 12:25:33 PM PST 24
Finished Mar 07 12:25:44 PM PST 24
Peak memory 201216 kb
Host smart-28147cbd-bc2a-4278-9707-90c6cd462dcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512006414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1512006414
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.3958730786
Short name T578
Test name
Test status
Simulation time 505851757 ps
CPU time 1.69 seconds
Started Mar 07 12:33:18 PM PST 24
Finished Mar 07 12:33:20 PM PST 24
Peak memory 201108 kb
Host smart-1647f952-3bbd-4c77-a849-f67e6f4cee63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958730786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.3958730786
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.267534570
Short name T569
Test name
Test status
Simulation time 160315415765 ps
CPU time 174.16 seconds
Started Mar 07 12:33:17 PM PST 24
Finished Mar 07 12:36:11 PM PST 24
Peak memory 201444 kb
Host smart-d54f6148-6c58-41b6-8964-b59c9301defc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267534570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.267534570
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1743092089
Short name T375
Test name
Test status
Simulation time 488747492291 ps
CPU time 251.93 seconds
Started Mar 07 12:33:15 PM PST 24
Finished Mar 07 12:37:27 PM PST 24
Peak memory 201308 kb
Host smart-40f51de2-51df-4c9e-b8ee-09833dae7e55
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743092089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1743092089
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2917805830
Short name T176
Test name
Test status
Simulation time 328229924914 ps
CPU time 198.28 seconds
Started Mar 07 12:33:15 PM PST 24
Finished Mar 07 12:36:34 PM PST 24
Peak memory 201300 kb
Host smart-31a3b47c-8133-43d1-907e-9da0040912c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917805830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2917805830
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1939504399
Short name T339
Test name
Test status
Simulation time 166383387891 ps
CPU time 213.61 seconds
Started Mar 07 12:33:32 PM PST 24
Finished Mar 07 12:37:06 PM PST 24
Peak memory 201320 kb
Host smart-cef3762f-e58d-43e5-8b72-ce033f76cb4d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939504399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1939504399
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3691793845
Short name T489
Test name
Test status
Simulation time 605714650803 ps
CPU time 1151.53 seconds
Started Mar 07 12:33:19 PM PST 24
Finished Mar 07 12:52:30 PM PST 24
Peak memory 201384 kb
Host smart-9f27b030-62dc-4aef-982b-40a8deb1ff8c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691793845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.3691793845
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3406055174
Short name T759
Test name
Test status
Simulation time 116609904830 ps
CPU time 530.87 seconds
Started Mar 07 12:33:18 PM PST 24
Finished Mar 07 12:42:09 PM PST 24
Peak memory 201716 kb
Host smart-d93e04cb-63fc-4f24-9a3b-d2b10d134c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406055174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3406055174
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3669408512
Short name T599
Test name
Test status
Simulation time 40085652176 ps
CPU time 26.94 seconds
Started Mar 07 12:33:24 PM PST 24
Finished Mar 07 12:33:51 PM PST 24
Peak memory 201124 kb
Host smart-35118963-fbd2-4fa3-a8a2-097555a89daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669408512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3669408512
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.411934173
Short name T445
Test name
Test status
Simulation time 4451218385 ps
CPU time 11.23 seconds
Started Mar 07 12:33:24 PM PST 24
Finished Mar 07 12:33:35 PM PST 24
Peak memory 200696 kb
Host smart-4e3fa1fd-4b62-4da4-bae2-59d02542518e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411934173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.411934173
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2274548114
Short name T58
Test name
Test status
Simulation time 7465026100 ps
CPU time 5.43 seconds
Started Mar 07 12:33:27 PM PST 24
Finished Mar 07 12:33:33 PM PST 24
Peak memory 216652 kb
Host smart-8fc9b691-1356-4d7c-98bb-0ac0af5fae68
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274548114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2274548114
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3720581755
Short name T696
Test name
Test status
Simulation time 5854122819 ps
CPU time 4.08 seconds
Started Mar 07 12:33:32 PM PST 24
Finished Mar 07 12:33:37 PM PST 24
Peak memory 201180 kb
Host smart-5894ad59-71a4-4e87-b0f7-1eceac4385d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720581755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3720581755
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.605579262
Short name T282
Test name
Test status
Simulation time 204262278025 ps
CPU time 489.24 seconds
Started Mar 07 12:33:21 PM PST 24
Finished Mar 07 12:41:31 PM PST 24
Peak memory 201304 kb
Host smart-87bc2cc3-9f9a-4976-8f63-ee28347a55a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605579262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.605579262
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.639989252
Short name T509
Test name
Test status
Simulation time 528260151 ps
CPU time 1.96 seconds
Started Mar 07 12:33:16 PM PST 24
Finished Mar 07 12:33:18 PM PST 24
Peak memory 201088 kb
Host smart-c458e1c2-d43f-44f6-a22a-379ce898325a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639989252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.639989252
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1884434965
Short name T513
Test name
Test status
Simulation time 168561315213 ps
CPU time 98.31 seconds
Started Mar 07 12:33:21 PM PST 24
Finished Mar 07 12:34:59 PM PST 24
Peak memory 201396 kb
Host smart-f4bb0179-ccc3-4ebd-97af-f86d32071643
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884434965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1884434965
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2462331139
Short name T156
Test name
Test status
Simulation time 565683860104 ps
CPU time 190 seconds
Started Mar 07 12:33:31 PM PST 24
Finished Mar 07 12:36:41 PM PST 24
Peak memory 201264 kb
Host smart-63a7ca5e-96fc-47dc-ac05-06f2497e6a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462331139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2462331139
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1852446093
Short name T7
Test name
Test status
Simulation time 331003823968 ps
CPU time 182.56 seconds
Started Mar 07 12:33:24 PM PST 24
Finished Mar 07 12:36:26 PM PST 24
Peak memory 200860 kb
Host smart-b17b803e-ccbe-47f9-879e-31e11dc010ec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852446093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1852446093
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.370913337
Short name T230
Test name
Test status
Simulation time 484675316927 ps
CPU time 606.87 seconds
Started Mar 07 12:33:26 PM PST 24
Finished Mar 07 12:43:33 PM PST 24
Peak memory 201372 kb
Host smart-264c9cd1-ba60-468c-ae64-36be13affae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370913337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.370913337
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2144775090
Short name T349
Test name
Test status
Simulation time 161573032930 ps
CPU time 68 seconds
Started Mar 07 12:33:41 PM PST 24
Finished Mar 07 12:34:49 PM PST 24
Peak memory 201304 kb
Host smart-1e43729d-3e25-49d3-9298-ba1620165299
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144775090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2144775090
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.881416362
Short name T761
Test name
Test status
Simulation time 401557379454 ps
CPU time 930.04 seconds
Started Mar 07 12:33:30 PM PST 24
Finished Mar 07 12:49:00 PM PST 24
Peak memory 201372 kb
Host smart-bd9cb7c5-7884-4196-95f0-c82f14300f56
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881416362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.a
dc_ctrl_filters_wakeup_fixed.881416362
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1642781630
Short name T773
Test name
Test status
Simulation time 98352625794 ps
CPU time 527.17 seconds
Started Mar 07 12:33:15 PM PST 24
Finished Mar 07 12:42:02 PM PST 24
Peak memory 201756 kb
Host smart-b2033b88-d7a4-4002-9f64-4eeb5c52d72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642781630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1642781630
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.607153021
Short name T777
Test name
Test status
Simulation time 28502636734 ps
CPU time 61.82 seconds
Started Mar 07 12:33:41 PM PST 24
Finished Mar 07 12:34:48 PM PST 24
Peak memory 201184 kb
Host smart-785cddea-eddb-46f5-931e-0b19a4724ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607153021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.607153021
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1915386153
Short name T639
Test name
Test status
Simulation time 4747658346 ps
CPU time 6.21 seconds
Started Mar 07 12:33:24 PM PST 24
Finished Mar 07 12:33:30 PM PST 24
Peak memory 201156 kb
Host smart-332e4a56-01b1-464a-9d56-9d6ac00a6aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915386153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1915386153
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1698188733
Short name T69
Test name
Test status
Simulation time 7921508345 ps
CPU time 10.29 seconds
Started Mar 07 12:33:18 PM PST 24
Finished Mar 07 12:33:29 PM PST 24
Peak memory 217640 kb
Host smart-a19a5ae5-4ac7-4527-9b91-ba3d8535ec44
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698188733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1698188733
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3457951926
Short name T695
Test name
Test status
Simulation time 6114630633 ps
CPU time 13.61 seconds
Started Mar 07 12:33:15 PM PST 24
Finished Mar 07 12:33:29 PM PST 24
Peak memory 201144 kb
Host smart-16d87290-41c4-4adc-8de9-e649f357e05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457951926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3457951926
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.192409932
Short name T674
Test name
Test status
Simulation time 520966346301 ps
CPU time 1263.98 seconds
Started Mar 07 12:33:17 PM PST 24
Finished Mar 07 12:54:21 PM PST 24
Peak memory 201272 kb
Host smart-68cb9541-7431-4d3e-817d-6c6014acdd9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192409932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.192409932
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3646147678
Short name T279
Test name
Test status
Simulation time 39079089922 ps
CPU time 98.36 seconds
Started Mar 07 12:33:15 PM PST 24
Finished Mar 07 12:34:53 PM PST 24
Peak memory 210476 kb
Host smart-43ab06bf-1239-4735-9d3c-a4248d8dfad8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646147678 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3646147678
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.818008917
Short name T235
Test name
Test status
Simulation time 167032760662 ps
CPU time 201.67 seconds
Started Mar 07 12:33:25 PM PST 24
Finished Mar 07 12:36:46 PM PST 24
Peak memory 201184 kb
Host smart-f984021b-532d-438e-aa8e-6673645ea4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818008917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.818008917
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.652431940
Short name T675
Test name
Test status
Simulation time 328588233668 ps
CPU time 363.91 seconds
Started Mar 07 12:33:33 PM PST 24
Finished Mar 07 12:39:37 PM PST 24
Peak memory 201368 kb
Host smart-a917d9cc-a919-40a9-9732-3b42efbe83b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652431940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.652431940
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1930918479
Short name T356
Test name
Test status
Simulation time 497778499231 ps
CPU time 1188.4 seconds
Started Mar 07 12:33:37 PM PST 24
Finished Mar 07 12:53:26 PM PST 24
Peak memory 201356 kb
Host smart-bd3fc536-2f76-4a4d-a275-4eb4f0816bb6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930918479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.1930918479
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.163203358
Short name T74
Test name
Test status
Simulation time 330294413697 ps
CPU time 216.87 seconds
Started Mar 07 12:33:29 PM PST 24
Finished Mar 07 12:37:07 PM PST 24
Peak memory 201312 kb
Host smart-939d1a6e-1702-48c9-939f-e092633389bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163203358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.163203358
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.598651499
Short name T551
Test name
Test status
Simulation time 162022249017 ps
CPU time 85.53 seconds
Started Mar 07 12:33:39 PM PST 24
Finished Mar 07 12:35:04 PM PST 24
Peak memory 201292 kb
Host smart-bd9f8493-1a7f-4b6c-8132-62dc214b4ddc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=598651499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.598651499
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.2081747774
Short name T730
Test name
Test status
Simulation time 172591896065 ps
CPU time 110.85 seconds
Started Mar 07 12:33:58 PM PST 24
Finished Mar 07 12:35:49 PM PST 24
Peak memory 201328 kb
Host smart-1f6ec028-4fa8-4224-8e73-08a41c075f81
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081747774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.2081747774
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3307365832
Short name T81
Test name
Test status
Simulation time 191902379148 ps
CPU time 222.72 seconds
Started Mar 07 12:33:37 PM PST 24
Finished Mar 07 12:37:20 PM PST 24
Peak memory 201304 kb
Host smart-5fe48a26-ff70-4ff7-b26f-f16b55d95047
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307365832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3307365832
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.563010651
Short name T745
Test name
Test status
Simulation time 130729773022 ps
CPU time 653.57 seconds
Started Mar 07 12:33:40 PM PST 24
Finished Mar 07 12:44:34 PM PST 24
Peak memory 201696 kb
Host smart-425fc861-1276-44ec-9feb-a5b7cf2968c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563010651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.563010651
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.4065553628
Short name T594
Test name
Test status
Simulation time 30387639601 ps
CPU time 38.91 seconds
Started Mar 07 12:33:43 PM PST 24
Finished Mar 07 12:34:22 PM PST 24
Peak memory 201184 kb
Host smart-724c8798-3c21-4a63-9f23-ca58c6b0d06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065553628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.4065553628
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2639648242
Short name T363
Test name
Test status
Simulation time 4636296468 ps
CPU time 7.53 seconds
Started Mar 07 12:33:32 PM PST 24
Finished Mar 07 12:33:40 PM PST 24
Peak memory 201268 kb
Host smart-fc2c14d9-2107-4271-b7f6-a7578573bb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639648242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2639648242
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.842776546
Short name T406
Test name
Test status
Simulation time 5541278414 ps
CPU time 14.41 seconds
Started Mar 07 12:33:45 PM PST 24
Finished Mar 07 12:34:00 PM PST 24
Peak memory 201160 kb
Host smart-81641f3d-f787-4d10-aa0a-575f597afc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842776546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.842776546
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1458246739
Short name T642
Test name
Test status
Simulation time 35765241890 ps
CPU time 75.46 seconds
Started Mar 07 12:33:42 PM PST 24
Finished Mar 07 12:34:58 PM PST 24
Peak memory 215864 kb
Host smart-ace20ca4-c73c-4c1f-aa10-192265c3b3a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458246739 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1458246739
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.2022696933
Short name T728
Test name
Test status
Simulation time 419035704 ps
CPU time 0.89 seconds
Started Mar 07 12:33:39 PM PST 24
Finished Mar 07 12:33:40 PM PST 24
Peak memory 201128 kb
Host smart-5996c352-2a78-4834-a6ff-cc58a1d4c734
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022696933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2022696933
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.294827631
Short name T650
Test name
Test status
Simulation time 497248732814 ps
CPU time 373.58 seconds
Started Mar 07 12:33:41 PM PST 24
Finished Mar 07 12:39:54 PM PST 24
Peak memory 201320 kb
Host smart-afdc75e3-2b0e-4bfe-b099-4aa72ea5fabb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294827631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.294827631
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1997072020
Short name T652
Test name
Test status
Simulation time 325422705887 ps
CPU time 382.5 seconds
Started Mar 07 12:33:34 PM PST 24
Finished Mar 07 12:39:56 PM PST 24
Peak memory 201464 kb
Host smart-7c593327-a2ca-40b9-9771-7dfc773fe872
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997072020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1997072020
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3106490087
Short name T309
Test name
Test status
Simulation time 329816797777 ps
CPU time 811.59 seconds
Started Mar 07 12:33:29 PM PST 24
Finished Mar 07 12:47:01 PM PST 24
Peak memory 201212 kb
Host smart-c49f1d64-1acf-402e-a123-2986ad81de7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106490087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3106490087
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.3286399082
Short name T361
Test name
Test status
Simulation time 160948263272 ps
CPU time 200.44 seconds
Started Mar 07 12:33:22 PM PST 24
Finished Mar 07 12:36:43 PM PST 24
Peak memory 201284 kb
Host smart-b8cf5d98-7d5c-41e9-a66e-94a55a2d2bf4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286399082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.3286399082
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1262284125
Short name T308
Test name
Test status
Simulation time 171103905579 ps
CPU time 98.6 seconds
Started Mar 07 12:33:48 PM PST 24
Finished Mar 07 12:35:26 PM PST 24
Peak memory 201328 kb
Host smart-dabfcbed-a7d0-4d9a-8973-ab470bf0efb0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262284125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1262284125
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.758566808
Short name T521
Test name
Test status
Simulation time 198597225626 ps
CPU time 452.97 seconds
Started Mar 07 12:33:23 PM PST 24
Finished Mar 07 12:40:56 PM PST 24
Peak memory 201356 kb
Host smart-27c0d76f-12e9-4db0-a775-0e56ceb8190b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758566808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
adc_ctrl_filters_wakeup_fixed.758566808
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3357611200
Short name T546
Test name
Test status
Simulation time 62216220063 ps
CPU time 337.68 seconds
Started Mar 07 12:33:52 PM PST 24
Finished Mar 07 12:39:30 PM PST 24
Peak memory 201796 kb
Host smart-4aa9a96d-661b-414f-8373-a5bbb8286869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357611200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3357611200
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.1215457960
Short name T633
Test name
Test status
Simulation time 43650075494 ps
CPU time 48.92 seconds
Started Mar 07 12:33:46 PM PST 24
Finished Mar 07 12:34:35 PM PST 24
Peak memory 201212 kb
Host smart-a246a2d2-6c2a-4478-a020-4a634cdeea75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215457960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.1215457960
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1753105413
Short name T364
Test name
Test status
Simulation time 5302153573 ps
CPU time 13.65 seconds
Started Mar 07 12:33:43 PM PST 24
Finished Mar 07 12:33:57 PM PST 24
Peak memory 201192 kb
Host smart-657065ab-6498-4db8-b2e6-b44c8e33a2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753105413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1753105413
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.71322638
Short name T734
Test name
Test status
Simulation time 5956805121 ps
CPU time 3.03 seconds
Started Mar 07 12:33:46 PM PST 24
Finished Mar 07 12:33:50 PM PST 24
Peak memory 201188 kb
Host smart-c4271372-2dd4-4dd3-b2f0-3369e426be4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71322638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.71322638
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.2112778556
Short name T574
Test name
Test status
Simulation time 167178762078 ps
CPU time 103.86 seconds
Started Mar 07 12:33:51 PM PST 24
Finished Mar 07 12:35:35 PM PST 24
Peak memory 201372 kb
Host smart-7483e93c-f91f-4d47-a07c-fac0883f3a5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112778556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.2112778556
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.405914722
Short name T77
Test name
Test status
Simulation time 99377966845 ps
CPU time 231.66 seconds
Started Mar 07 12:33:42 PM PST 24
Finished Mar 07 12:37:34 PM PST 24
Peak memory 210212 kb
Host smart-71b06ee9-614f-417e-91d5-635670f93cdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405914722 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.405914722
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2098765919
Short name T723
Test name
Test status
Simulation time 447205158 ps
CPU time 1.67 seconds
Started Mar 07 12:33:57 PM PST 24
Finished Mar 07 12:33:59 PM PST 24
Peak memory 201008 kb
Host smart-c9efc3af-55f0-42b4-bb55-43ab37073595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098765919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2098765919
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2030295990
Short name T242
Test name
Test status
Simulation time 337470691525 ps
CPU time 823.68 seconds
Started Mar 07 12:33:41 PM PST 24
Finished Mar 07 12:47:25 PM PST 24
Peak memory 201312 kb
Host smart-43130911-f602-443e-bf39-da6865ba339b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030295990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2030295990
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.1891466541
Short name T508
Test name
Test status
Simulation time 162617366076 ps
CPU time 315.37 seconds
Started Mar 07 12:33:43 PM PST 24
Finished Mar 07 12:38:59 PM PST 24
Peak memory 201408 kb
Host smart-1f0c310c-f96c-4745-b9d1-6ec2ae233b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891466541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1891466541
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1618919804
Short name T412
Test name
Test status
Simulation time 329410864817 ps
CPU time 738.86 seconds
Started Mar 07 12:33:53 PM PST 24
Finished Mar 07 12:46:14 PM PST 24
Peak memory 201376 kb
Host smart-03ffce11-11ff-498a-b05a-082123a9a312
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618919804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1618919804
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.167778227
Short name T637
Test name
Test status
Simulation time 164621350747 ps
CPU time 397.15 seconds
Started Mar 07 12:33:38 PM PST 24
Finished Mar 07 12:40:16 PM PST 24
Peak memory 201316 kb
Host smart-6257f0ef-a608-480f-bf67-12bf1873324e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167778227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.167778227
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2625365209
Short name T452
Test name
Test status
Simulation time 326211282651 ps
CPU time 746.28 seconds
Started Mar 07 12:33:48 PM PST 24
Finished Mar 07 12:46:14 PM PST 24
Peak memory 201364 kb
Host smart-9fad2350-9c50-459e-a5b6-aacc73d687e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625365209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2625365209
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.36183758
Short name T321
Test name
Test status
Simulation time 176243777312 ps
CPU time 402.23 seconds
Started Mar 07 12:33:33 PM PST 24
Finished Mar 07 12:40:15 PM PST 24
Peak memory 201380 kb
Host smart-40357c16-7192-42fd-958f-7c23cfde06fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36183758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_w
akeup.36183758
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3637597182
Short name T735
Test name
Test status
Simulation time 606425083042 ps
CPU time 774.22 seconds
Started Mar 07 12:33:45 PM PST 24
Finished Mar 07 12:46:40 PM PST 24
Peak memory 201352 kb
Host smart-bc852054-8772-4387-84a8-adc22542f311
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637597182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3637597182
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2164214955
Short name T196
Test name
Test status
Simulation time 59129854301 ps
CPU time 363.98 seconds
Started Mar 07 12:33:32 PM PST 24
Finished Mar 07 12:39:37 PM PST 24
Peak memory 201748 kb
Host smart-a445f75f-a076-42ed-8ead-9e7696e509e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164214955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2164214955
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2973821541
Short name T458
Test name
Test status
Simulation time 41278251227 ps
CPU time 99.65 seconds
Started Mar 07 12:33:46 PM PST 24
Finished Mar 07 12:35:26 PM PST 24
Peak memory 201196 kb
Host smart-8fe0887e-33da-4a7e-8305-b471d35fe377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973821541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2973821541
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3909437294
Short name T526
Test name
Test status
Simulation time 5435037424 ps
CPU time 13.58 seconds
Started Mar 07 12:33:55 PM PST 24
Finished Mar 07 12:34:09 PM PST 24
Peak memory 201140 kb
Host smart-03815cdf-9d57-42c7-adcc-8c41ded172f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909437294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3909437294
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3212430016
Short name T468
Test name
Test status
Simulation time 5691454617 ps
CPU time 14.33 seconds
Started Mar 07 12:33:39 PM PST 24
Finished Mar 07 12:33:53 PM PST 24
Peak memory 201240 kb
Host smart-755fa2af-69d9-4a74-b2d0-c6654f52e529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212430016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3212430016
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.4133006949
Short name T2
Test name
Test status
Simulation time 131629807679 ps
CPU time 521.37 seconds
Started Mar 07 12:33:51 PM PST 24
Finished Mar 07 12:42:32 PM PST 24
Peak memory 201748 kb
Host smart-02340944-fd33-4f01-9193-6158b4da50fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133006949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.4133006949
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1521969224
Short name T32
Test name
Test status
Simulation time 31848414438 ps
CPU time 87.17 seconds
Started Mar 07 12:33:36 PM PST 24
Finished Mar 07 12:35:03 PM PST 24
Peak memory 201932 kb
Host smart-0d0c370b-0e70-487a-a447-e8cc2483a668
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521969224 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1521969224
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.4200176971
Short name T495
Test name
Test status
Simulation time 316366318 ps
CPU time 0.81 seconds
Started Mar 07 12:33:56 PM PST 24
Finished Mar 07 12:33:57 PM PST 24
Peak memory 201188 kb
Host smart-91687ff9-02f3-4645-b75c-8adc79c9e833
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200176971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.4200176971
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3752163805
Short name T272
Test name
Test status
Simulation time 489798602247 ps
CPU time 295.78 seconds
Started Mar 07 12:34:16 PM PST 24
Finished Mar 07 12:39:16 PM PST 24
Peak memory 201396 kb
Host smart-65f6c0da-5468-4b39-bebf-8e1d28faad5d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752163805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3752163805
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1575095531
Short name T146
Test name
Test status
Simulation time 492071912298 ps
CPU time 101.68 seconds
Started Mar 07 12:33:52 PM PST 24
Finished Mar 07 12:35:34 PM PST 24
Peak memory 201204 kb
Host smart-d86ddd5f-b5f6-4b66-8885-b071d51ab4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575095531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1575095531
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2473179608
Short name T474
Test name
Test status
Simulation time 164944040260 ps
CPU time 186.93 seconds
Started Mar 07 12:33:50 PM PST 24
Finished Mar 07 12:36:57 PM PST 24
Peak memory 201316 kb
Host smart-13827739-e914-48fe-a4da-60020869ac17
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473179608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.2473179608
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.870675890
Short name T173
Test name
Test status
Simulation time 390444666738 ps
CPU time 67.56 seconds
Started Mar 07 12:33:45 PM PST 24
Finished Mar 07 12:34:53 PM PST 24
Peak memory 201336 kb
Host smart-54fa4efd-7dfb-4d92-a3a5-9ce6206fb65a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870675890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.870675890
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.989122226
Short name T444
Test name
Test status
Simulation time 202675237988 ps
CPU time 510.85 seconds
Started Mar 07 12:33:49 PM PST 24
Finished Mar 07 12:42:20 PM PST 24
Peak memory 201304 kb
Host smart-73e7c52a-638f-4f0d-8b09-e4e13316370b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989122226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
adc_ctrl_filters_wakeup_fixed.989122226
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2390015669
Short name T454
Test name
Test status
Simulation time 92843546096 ps
CPU time 491.98 seconds
Started Mar 07 12:33:55 PM PST 24
Finished Mar 07 12:42:08 PM PST 24
Peak memory 201816 kb
Host smart-d7ac5ea4-ca60-4e4c-86e7-f6cf00ac2622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390015669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2390015669
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.338576239
Short name T740
Test name
Test status
Simulation time 22306908449 ps
CPU time 50.8 seconds
Started Mar 07 12:33:51 PM PST 24
Finished Mar 07 12:34:42 PM PST 24
Peak memory 201196 kb
Host smart-5f6a8e28-24d2-4b77-afbc-bb754d946155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338576239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.338576239
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1386729215
Short name T527
Test name
Test status
Simulation time 3123504565 ps
CPU time 3.23 seconds
Started Mar 07 12:34:09 PM PST 24
Finished Mar 07 12:34:13 PM PST 24
Peak memory 201196 kb
Host smart-3bfd10ce-5831-485e-8ab6-6d21ea25385c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386729215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1386729215
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2186458627
Short name T538
Test name
Test status
Simulation time 6190242605 ps
CPU time 15.6 seconds
Started Mar 07 12:33:57 PM PST 24
Finished Mar 07 12:34:13 PM PST 24
Peak memory 201192 kb
Host smart-f7ef833a-bedf-4afc-882d-41d65c04d8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186458627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2186458627
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.473164050
Short name T629
Test name
Test status
Simulation time 74669280403 ps
CPU time 241.55 seconds
Started Mar 07 12:33:48 PM PST 24
Finished Mar 07 12:37:50 PM PST 24
Peak memory 201332 kb
Host smart-ed3e230c-c5af-475e-8040-8dcc19b19c51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473164050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
473164050
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.4206749107
Short name T462
Test name
Test status
Simulation time 554948190 ps
CPU time 0.68 seconds
Started Mar 07 12:33:55 PM PST 24
Finished Mar 07 12:33:56 PM PST 24
Peak memory 201128 kb
Host smart-0cf1dce4-2391-4108-86a8-454aa0722f7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206749107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.4206749107
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1902260183
Short name T209
Test name
Test status
Simulation time 160021073918 ps
CPU time 351.19 seconds
Started Mar 07 12:33:54 PM PST 24
Finished Mar 07 12:39:47 PM PST 24
Peak memory 201320 kb
Host smart-a790a5f3-3afc-4f82-a82f-8363b7cd6a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902260183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1902260183
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2777679608
Short name T380
Test name
Test status
Simulation time 166264015473 ps
CPU time 402.29 seconds
Started Mar 07 12:33:50 PM PST 24
Finished Mar 07 12:40:33 PM PST 24
Peak memory 201320 kb
Host smart-f1d28724-3ad4-41fe-b2a8-239bc54a7705
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777679608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2777679608
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1524408938
Short name T628
Test name
Test status
Simulation time 160694322567 ps
CPU time 393.32 seconds
Started Mar 07 12:33:57 PM PST 24
Finished Mar 07 12:40:30 PM PST 24
Peak memory 201276 kb
Host smart-73bf044b-3e63-4ff4-9ca8-499e87c5a203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524408938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1524408938
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.3265172299
Short name T389
Test name
Test status
Simulation time 164164586261 ps
CPU time 120.23 seconds
Started Mar 07 12:33:49 PM PST 24
Finished Mar 07 12:35:49 PM PST 24
Peak memory 201396 kb
Host smart-df0fd9be-2a1d-4b1d-acba-dac4e7cb61cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265172299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.3265172299
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.641102397
Short name T758
Test name
Test status
Simulation time 351415215646 ps
CPU time 807.74 seconds
Started Mar 07 12:33:42 PM PST 24
Finished Mar 07 12:47:10 PM PST 24
Peak memory 201404 kb
Host smart-e660f9b1-35fd-472d-b188-3bd413699d24
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641102397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.641102397
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2660220826
Short name T598
Test name
Test status
Simulation time 590791298909 ps
CPU time 656.29 seconds
Started Mar 07 12:33:49 PM PST 24
Finished Mar 07 12:44:46 PM PST 24
Peak memory 201292 kb
Host smart-692d7140-32aa-45e3-96be-f07cb53276de
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660220826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2660220826
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1105327078
Short name T188
Test name
Test status
Simulation time 111682731344 ps
CPU time 607.53 seconds
Started Mar 07 12:33:54 PM PST 24
Finished Mar 07 12:44:03 PM PST 24
Peak memory 201704 kb
Host smart-1492a585-80cf-4284-84b8-71cf5dc6e20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105327078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1105327078
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.751434816
Short name T592
Test name
Test status
Simulation time 22394285328 ps
CPU time 52.48 seconds
Started Mar 07 12:33:53 PM PST 24
Finished Mar 07 12:34:48 PM PST 24
Peak memory 201140 kb
Host smart-84ecae31-7df3-48e0-8650-4e2f7ca9f073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751434816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.751434816
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3905098601
Short name T346
Test name
Test status
Simulation time 2942801816 ps
CPU time 7.53 seconds
Started Mar 07 12:33:54 PM PST 24
Finished Mar 07 12:34:03 PM PST 24
Peak memory 201192 kb
Host smart-c80bea48-7fb9-432f-b864-b200d08bb270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905098601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3905098601
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.4222087477
Short name T520
Test name
Test status
Simulation time 5918323379 ps
CPU time 1.87 seconds
Started Mar 07 12:33:43 PM PST 24
Finished Mar 07 12:33:45 PM PST 24
Peak memory 201236 kb
Host smart-8d5995a0-f8b0-418b-985d-e038f7debc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222087477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.4222087477
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2618395254
Short name T237
Test name
Test status
Simulation time 363601428126 ps
CPU time 214.64 seconds
Started Mar 07 12:33:49 PM PST 24
Finished Mar 07 12:37:24 PM PST 24
Peak memory 201384 kb
Host smart-ea40df3f-9477-4887-97bb-0b93827ba1bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618395254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2618395254
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3474579357
Short name T731
Test name
Test status
Simulation time 554894666208 ps
CPU time 295.34 seconds
Started Mar 07 12:33:57 PM PST 24
Finished Mar 07 12:38:53 PM PST 24
Peak memory 210000 kb
Host smart-7bb083e3-e616-47cf-867d-3e20db5ef870
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474579357 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3474579357
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.3793211084
Short name T393
Test name
Test status
Simulation time 527858964 ps
CPU time 0.9 seconds
Started Mar 07 12:33:52 PM PST 24
Finished Mar 07 12:33:53 PM PST 24
Peak memory 201128 kb
Host smart-66b7db3e-33f9-4264-b0d5-761689d117ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793211084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.3793211084
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1847994247
Short name T457
Test name
Test status
Simulation time 165226985597 ps
CPU time 359.74 seconds
Started Mar 07 12:33:40 PM PST 24
Finished Mar 07 12:39:39 PM PST 24
Peak memory 201376 kb
Host smart-50310662-1e0a-4788-a7e7-554043321f9a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847994247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1847994247
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3056709639
Short name T748
Test name
Test status
Simulation time 490914739956 ps
CPU time 1083.38 seconds
Started Mar 07 12:33:50 PM PST 24
Finished Mar 07 12:51:54 PM PST 24
Peak memory 201264 kb
Host smart-710c358d-85c4-48e0-868c-a7d82fdd9fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056709639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3056709639
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.695020421
Short name T739
Test name
Test status
Simulation time 166109958217 ps
CPU time 377.92 seconds
Started Mar 07 12:33:53 PM PST 24
Finished Mar 07 12:40:13 PM PST 24
Peak memory 201072 kb
Host smart-5a7adc5f-c6b9-4a22-820d-c447ced98c47
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=695020421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrup
t_fixed.695020421
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2396231497
Short name T785
Test name
Test status
Simulation time 491214861189 ps
CPU time 1146.39 seconds
Started Mar 07 12:34:01 PM PST 24
Finished Mar 07 12:53:08 PM PST 24
Peak memory 201260 kb
Host smart-8d701119-b9de-4772-99c8-033e324ae96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396231497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2396231497
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.4157628540
Short name T365
Test name
Test status
Simulation time 322139586903 ps
CPU time 759.2 seconds
Started Mar 07 12:33:49 PM PST 24
Finished Mar 07 12:46:28 PM PST 24
Peak memory 201316 kb
Host smart-b8d14348-f433-45f3-8928-6bde814acbb5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157628540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.4157628540
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.1142473662
Short name T160
Test name
Test status
Simulation time 358920500912 ps
CPU time 121.8 seconds
Started Mar 07 12:34:06 PM PST 24
Finished Mar 07 12:36:08 PM PST 24
Peak memory 201328 kb
Host smart-bca95918-14bb-45ba-bce8-f0fbd6fca116
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142473662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.1142473662
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.4164311268
Short name T556
Test name
Test status
Simulation time 144992431219 ps
CPU time 467.31 seconds
Started Mar 07 12:33:50 PM PST 24
Finished Mar 07 12:41:37 PM PST 24
Peak memory 201696 kb
Host smart-aa94aa3f-67f9-4081-a6ea-16eb067784f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164311268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.4164311268
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1103346796
Short name T491
Test name
Test status
Simulation time 44023221681 ps
CPU time 50.08 seconds
Started Mar 07 12:33:41 PM PST 24
Finished Mar 07 12:34:31 PM PST 24
Peak memory 201184 kb
Host smart-18cddee0-0b93-44cc-8305-623a898c8e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103346796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1103346796
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3165631942
Short name T506
Test name
Test status
Simulation time 3624086285 ps
CPU time 4.36 seconds
Started Mar 07 12:33:47 PM PST 24
Finished Mar 07 12:33:52 PM PST 24
Peak memory 201164 kb
Host smart-4b15c149-d1b1-4588-b4bd-5f7486f0157c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165631942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3165631942
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.109872652
Short name T420
Test name
Test status
Simulation time 6228909969 ps
CPU time 4.94 seconds
Started Mar 07 12:33:59 PM PST 24
Finished Mar 07 12:34:05 PM PST 24
Peak memory 201156 kb
Host smart-c95fc018-07de-4004-a347-38a90746a116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109872652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.109872652
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1581681306
Short name T276
Test name
Test status
Simulation time 327602470459 ps
CPU time 822.01 seconds
Started Mar 07 12:33:50 PM PST 24
Finished Mar 07 12:47:32 PM PST 24
Peak memory 201312 kb
Host smart-0ac67ab4-28e0-49b4-aa6a-85cdd8a93997
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581681306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1581681306
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.2785622034
Short name T20
Test name
Test status
Simulation time 168432098592 ps
CPU time 115.42 seconds
Started Mar 07 12:33:52 PM PST 24
Finished Mar 07 12:35:48 PM PST 24
Peak memory 209600 kb
Host smart-b36e3db1-409d-4b35-b695-2b3d6500d7ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785622034 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.2785622034
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2675386922
Short name T694
Test name
Test status
Simulation time 505346048 ps
CPU time 1.77 seconds
Started Mar 07 12:33:51 PM PST 24
Finished Mar 07 12:33:53 PM PST 24
Peak memory 201092 kb
Host smart-6caf5192-ae18-4bc8-bd1f-15ff551d3fa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675386922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2675386922
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1533388102
Short name T316
Test name
Test status
Simulation time 491053222948 ps
CPU time 583.27 seconds
Started Mar 07 12:33:53 PM PST 24
Finished Mar 07 12:43:39 PM PST 24
Peak memory 201320 kb
Host smart-386acc54-9643-4d89-aad2-4b75f5d61e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533388102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1533388102
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3880028501
Short name T648
Test name
Test status
Simulation time 160124813441 ps
CPU time 65.86 seconds
Started Mar 07 12:34:00 PM PST 24
Finished Mar 07 12:35:07 PM PST 24
Peak memory 201268 kb
Host smart-7f01baa2-a294-48eb-a5c0-0928f742f663
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880028501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3880028501
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3517414889
Short name T290
Test name
Test status
Simulation time 163403490554 ps
CPU time 39.9 seconds
Started Mar 07 12:33:57 PM PST 24
Finished Mar 07 12:34:37 PM PST 24
Peak memory 201320 kb
Host smart-f86eb52a-2300-4856-9ddd-2ba710f2b803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517414889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3517414889
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.802483772
Short name T358
Test name
Test status
Simulation time 488287796157 ps
CPU time 615.33 seconds
Started Mar 07 12:33:53 PM PST 24
Finished Mar 07 12:44:11 PM PST 24
Peak memory 201320 kb
Host smart-93e85c61-c0b4-4088-bcf0-19323f1b4ce9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=802483772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixe
d.802483772
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3635883172
Short name T297
Test name
Test status
Simulation time 366527197590 ps
CPU time 940.38 seconds
Started Mar 07 12:34:03 PM PST 24
Finished Mar 07 12:49:44 PM PST 24
Peak memory 201404 kb
Host smart-17715a38-a793-43bf-86a5-d30a1e398bb4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635883172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3635883172
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.293566099
Short name T512
Test name
Test status
Simulation time 401257521310 ps
CPU time 142.88 seconds
Started Mar 07 12:33:58 PM PST 24
Finished Mar 07 12:36:21 PM PST 24
Peak memory 201184 kb
Host smart-b5914a1f-6c21-44ab-b209-a24aa2c6bbc0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293566099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.293566099
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.1700571153
Short name T784
Test name
Test status
Simulation time 106965597501 ps
CPU time 383.19 seconds
Started Mar 07 12:33:58 PM PST 24
Finished Mar 07 12:40:21 PM PST 24
Peak memory 201760 kb
Host smart-a1e44f41-4bd5-4ec7-b298-f8d11eefbfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700571153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.1700571153
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1685592299
Short name T494
Test name
Test status
Simulation time 26751388939 ps
CPU time 63.49 seconds
Started Mar 07 12:33:57 PM PST 24
Finished Mar 07 12:35:00 PM PST 24
Peak memory 201168 kb
Host smart-122f76ea-e1e8-448c-8fd7-1eb3f991542a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685592299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1685592299
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2432752511
Short name T123
Test name
Test status
Simulation time 3224990301 ps
CPU time 2.66 seconds
Started Mar 07 12:33:57 PM PST 24
Finished Mar 07 12:34:00 PM PST 24
Peak memory 201196 kb
Host smart-82ff1574-020d-4379-85db-c3c07348b305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432752511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2432752511
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.751842477
Short name T350
Test name
Test status
Simulation time 5824415548 ps
CPU time 7.26 seconds
Started Mar 07 12:33:37 PM PST 24
Finished Mar 07 12:33:46 PM PST 24
Peak memory 201180 kb
Host smart-32845c28-c049-4d15-b502-4cef83bb2333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751842477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.751842477
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.41297836
Short name T31
Test name
Test status
Simulation time 326909368239 ps
CPU time 211.16 seconds
Started Mar 07 12:34:03 PM PST 24
Finished Mar 07 12:37:35 PM PST 24
Peak memory 201472 kb
Host smart-3ec92fb8-f01d-45a1-b1f8-5507228d5fb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41297836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.41297836
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2475206342
Short name T23
Test name
Test status
Simulation time 101483637680 ps
CPU time 193.53 seconds
Started Mar 07 12:33:54 PM PST 24
Finished Mar 07 12:37:09 PM PST 24
Peak memory 209612 kb
Host smart-8414b8d0-b46d-4503-822c-598a36e8b8fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475206342 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2475206342
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3033003667
Short name T427
Test name
Test status
Simulation time 475165688 ps
CPU time 1.59 seconds
Started Mar 07 12:33:54 PM PST 24
Finished Mar 07 12:33:57 PM PST 24
Peak memory 201132 kb
Host smart-deaeac7a-d42a-4f53-baa3-377a79260d0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033003667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3033003667
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2728779108
Short name T682
Test name
Test status
Simulation time 576189149811 ps
CPU time 1080.89 seconds
Started Mar 07 12:33:51 PM PST 24
Finished Mar 07 12:51:52 PM PST 24
Peak memory 201328 kb
Host smart-ee327a3e-8e81-47db-927f-381448d30201
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728779108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2728779108
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1137855359
Short name T144
Test name
Test status
Simulation time 489312539749 ps
CPU time 484.6 seconds
Started Mar 07 12:33:53 PM PST 24
Finished Mar 07 12:41:57 PM PST 24
Peak memory 201308 kb
Host smart-62bfd23c-3a53-4989-95ea-b5dc8b1e081a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137855359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1137855359
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.976763900
Short name T511
Test name
Test status
Simulation time 330537264236 ps
CPU time 849.43 seconds
Started Mar 07 12:33:48 PM PST 24
Finished Mar 07 12:47:58 PM PST 24
Peak memory 201392 kb
Host smart-1f049807-af43-4d73-a859-c58268dd7914
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=976763900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.976763900
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.3254517739
Short name T252
Test name
Test status
Simulation time 330398492446 ps
CPU time 192.81 seconds
Started Mar 07 12:33:54 PM PST 24
Finished Mar 07 12:37:08 PM PST 24
Peak memory 201228 kb
Host smart-c67d0ab1-0822-46f4-9957-f7afdaa1fcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254517739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3254517739
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1938728361
Short name T632
Test name
Test status
Simulation time 158045019949 ps
CPU time 368.61 seconds
Started Mar 07 12:33:54 PM PST 24
Finished Mar 07 12:40:04 PM PST 24
Peak memory 201296 kb
Host smart-78b6971e-98b9-4d7f-a5af-9162f2d90973
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938728361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.1938728361
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.4157362904
Short name T286
Test name
Test status
Simulation time 384896878088 ps
CPU time 459.12 seconds
Started Mar 07 12:33:55 PM PST 24
Finished Mar 07 12:41:35 PM PST 24
Peak memory 201368 kb
Host smart-30095277-5ef3-4dc3-b629-9476d6dc38f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157362904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.4157362904
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3875801892
Short name T736
Test name
Test status
Simulation time 209670434922 ps
CPU time 111.15 seconds
Started Mar 07 12:33:52 PM PST 24
Finished Mar 07 12:35:43 PM PST 24
Peak memory 201228 kb
Host smart-7c5f955c-44fa-43cb-a4b2-80e11cbda952
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875801892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3875801892
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1762391226
Short name T757
Test name
Test status
Simulation time 112028635878 ps
CPU time 421.62 seconds
Started Mar 07 12:33:56 PM PST 24
Finished Mar 07 12:40:58 PM PST 24
Peak memory 201668 kb
Host smart-7ea11bf0-9276-4f01-bfb4-3fc232f679eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762391226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1762391226
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.4127191623
Short name T744
Test name
Test status
Simulation time 45878988185 ps
CPU time 15.51 seconds
Started Mar 07 12:33:48 PM PST 24
Finished Mar 07 12:34:04 PM PST 24
Peak memory 201252 kb
Host smart-799bf1c3-6665-415d-a97c-c8f15ae3111f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127191623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.4127191623
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.3254052695
Short name T698
Test name
Test status
Simulation time 2687567147 ps
CPU time 7.4 seconds
Started Mar 07 12:33:58 PM PST 24
Finished Mar 07 12:34:05 PM PST 24
Peak memory 201280 kb
Host smart-599cb226-a57b-41a2-9100-8dd64413089d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254052695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3254052695
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1316726482
Short name T438
Test name
Test status
Simulation time 5805623468 ps
CPU time 7.95 seconds
Started Mar 07 12:33:52 PM PST 24
Finished Mar 07 12:34:00 PM PST 24
Peak memory 201084 kb
Host smart-52429ba6-8a83-4edb-a62a-bbfa45fe3abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316726482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1316726482
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.4097601984
Short name T27
Test name
Test status
Simulation time 205050010949 ps
CPU time 260.13 seconds
Started Mar 07 12:33:52 PM PST 24
Finished Mar 07 12:38:13 PM PST 24
Peak memory 201284 kb
Host smart-e82a254a-12d0-471f-bf6a-488b1db262cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097601984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.4097601984
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3576904077
Short name T100
Test name
Test status
Simulation time 21687224449 ps
CPU time 48.63 seconds
Started Mar 07 12:34:01 PM PST 24
Finished Mar 07 12:34:49 PM PST 24
Peak memory 201508 kb
Host smart-c1e1402c-3ece-4b6d-99d1-1acf8f349cb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576904077 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3576904077
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1313946319
Short name T669
Test name
Test status
Simulation time 459365525 ps
CPU time 1.8 seconds
Started Mar 07 12:33:58 PM PST 24
Finished Mar 07 12:34:00 PM PST 24
Peak memory 201080 kb
Host smart-f5d97a4f-7836-41a0-8a38-b9f791e5de51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313946319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1313946319
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2277158570
Short name T265
Test name
Test status
Simulation time 492575585743 ps
CPU time 674.23 seconds
Started Mar 07 12:34:07 PM PST 24
Finished Mar 07 12:45:22 PM PST 24
Peak memory 201308 kb
Host smart-5e11a877-f755-4980-9b9f-6ab8b5975bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277158570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2277158570
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1315892291
Short name T404
Test name
Test status
Simulation time 495845658312 ps
CPU time 332.53 seconds
Started Mar 07 12:33:56 PM PST 24
Finished Mar 07 12:39:29 PM PST 24
Peak memory 201308 kb
Host smart-fef0041f-4d72-4dcb-8efb-51bd26b98d93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315892291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1315892291
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1626224701
Short name T580
Test name
Test status
Simulation time 323425281845 ps
CPU time 424.02 seconds
Started Mar 07 12:33:53 PM PST 24
Finished Mar 07 12:40:59 PM PST 24
Peak memory 201324 kb
Host smart-7f055349-bedb-4c3f-abd2-3049518330f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626224701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1626224701
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2384889250
Short name T83
Test name
Test status
Simulation time 167409650299 ps
CPU time 109.81 seconds
Started Mar 07 12:33:49 PM PST 24
Finished Mar 07 12:35:39 PM PST 24
Peak memory 201252 kb
Host smart-58f22608-8b55-4779-95ec-021686ecee2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384889250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2384889250
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1201258136
Short name T168
Test name
Test status
Simulation time 386104351567 ps
CPU time 113.96 seconds
Started Mar 07 12:33:57 PM PST 24
Finished Mar 07 12:35:51 PM PST 24
Peak memory 201324 kb
Host smart-0ecd2cb4-d05e-4a28-a845-01ca7ef47480
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201258136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1201258136
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2072313225
Short name T86
Test name
Test status
Simulation time 203478346440 ps
CPU time 108.02 seconds
Started Mar 07 12:33:52 PM PST 24
Finished Mar 07 12:35:40 PM PST 24
Peak memory 201320 kb
Host smart-b2253548-a7fc-4e53-9caa-35cf963cab92
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072313225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2072313225
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.3439386724
Short name T577
Test name
Test status
Simulation time 114166439622 ps
CPU time 486.11 seconds
Started Mar 07 12:34:03 PM PST 24
Finished Mar 07 12:42:09 PM PST 24
Peak memory 201776 kb
Host smart-9101bba6-0d6f-4201-8445-c48692a6616d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439386724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.3439386724
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2708559552
Short name T612
Test name
Test status
Simulation time 37530061272 ps
CPU time 25.05 seconds
Started Mar 07 12:34:04 PM PST 24
Finished Mar 07 12:34:30 PM PST 24
Peak memory 201168 kb
Host smart-1c6cf56f-a62f-4b97-9cfb-b604f6ce6f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708559552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2708559552
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1807879103
Short name T342
Test name
Test status
Simulation time 3958967244 ps
CPU time 4.96 seconds
Started Mar 07 12:34:02 PM PST 24
Finished Mar 07 12:34:08 PM PST 24
Peak memory 201192 kb
Host smart-32243d90-09d2-4491-8db8-7bfafa984a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807879103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1807879103
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1383235056
Short name T610
Test name
Test status
Simulation time 5655240925 ps
CPU time 3.37 seconds
Started Mar 07 12:34:21 PM PST 24
Finished Mar 07 12:34:24 PM PST 24
Peak memory 201088 kb
Host smart-85ba637e-66c6-4ef7-855c-aa0d02c8c2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383235056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1383235056
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1558712856
Short name T528
Test name
Test status
Simulation time 86045210358 ps
CPU time 290.72 seconds
Started Mar 07 12:34:13 PM PST 24
Finished Mar 07 12:39:04 PM PST 24
Peak memory 217908 kb
Host smart-26caf0c8-1c56-44fe-a94a-f242f7b8f4e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558712856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1558712856
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.4055008335
Short name T753
Test name
Test status
Simulation time 78458519408 ps
CPU time 46.83 seconds
Started Mar 07 12:34:00 PM PST 24
Finished Mar 07 12:34:47 PM PST 24
Peak memory 210332 kb
Host smart-53044c2b-51cf-4faf-8187-a220671b5217
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055008335 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.4055008335
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1010277909
Short name T355
Test name
Test status
Simulation time 498704270 ps
CPU time 0.88 seconds
Started Mar 07 12:34:03 PM PST 24
Finished Mar 07 12:34:04 PM PST 24
Peak memory 201124 kb
Host smart-b149a156-7a11-4e39-95e3-968d3553ad51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010277909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1010277909
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.4090454317
Short name T258
Test name
Test status
Simulation time 493968089871 ps
CPU time 1004.39 seconds
Started Mar 07 12:33:51 PM PST 24
Finished Mar 07 12:50:36 PM PST 24
Peak memory 201344 kb
Host smart-efdb3254-252e-4cc3-bf26-66392f132607
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090454317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.4090454317
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.2123439271
Short name T220
Test name
Test status
Simulation time 497416347690 ps
CPU time 1228.28 seconds
Started Mar 07 12:34:01 PM PST 24
Finished Mar 07 12:54:30 PM PST 24
Peak memory 201312 kb
Host smart-e348aa1c-635c-4854-90f7-188a3ad7a69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123439271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2123439271
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2509336746
Short name T298
Test name
Test status
Simulation time 494541258782 ps
CPU time 297.97 seconds
Started Mar 07 12:34:01 PM PST 24
Finished Mar 07 12:38:59 PM PST 24
Peak memory 201380 kb
Host smart-e5d7b2be-1a40-4f10-bc54-d5c3a6280648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509336746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2509336746
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3707280637
Short name T533
Test name
Test status
Simulation time 331554403108 ps
CPU time 389.87 seconds
Started Mar 07 12:34:02 PM PST 24
Finished Mar 07 12:40:32 PM PST 24
Peak memory 201480 kb
Host smart-9bb7281a-75ae-4ffb-b178-b05c8b2db1db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707280637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3707280637
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.4220881051
Short name T690
Test name
Test status
Simulation time 169051584195 ps
CPU time 401.49 seconds
Started Mar 07 12:34:01 PM PST 24
Finished Mar 07 12:40:43 PM PST 24
Peak memory 201208 kb
Host smart-9825e5cf-19d9-4f53-b448-2a48ed320263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220881051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.4220881051
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1251878073
Short name T151
Test name
Test status
Simulation time 329522700727 ps
CPU time 128.08 seconds
Started Mar 07 12:33:59 PM PST 24
Finished Mar 07 12:36:08 PM PST 24
Peak memory 201228 kb
Host smart-2b078a71-c3c2-435c-b829-1b67215f78c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251878073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1251878073
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.278973315
Short name T701
Test name
Test status
Simulation time 605770419355 ps
CPU time 213.28 seconds
Started Mar 07 12:34:17 PM PST 24
Finished Mar 07 12:37:54 PM PST 24
Peak memory 201300 kb
Host smart-48b49be1-b816-475c-9fe6-d83e41680cb4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278973315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.278973315
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3464716962
Short name T183
Test name
Test status
Simulation time 135485510161 ps
CPU time 717.91 seconds
Started Mar 07 12:33:57 PM PST 24
Finished Mar 07 12:45:55 PM PST 24
Peak memory 201708 kb
Host smart-9cd3dce3-357b-417f-a579-f43cf5d9d4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464716962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3464716962
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1354762524
Short name T764
Test name
Test status
Simulation time 26628407901 ps
CPU time 13.3 seconds
Started Mar 07 12:34:01 PM PST 24
Finished Mar 07 12:34:15 PM PST 24
Peak memory 201172 kb
Host smart-0680a66b-a7c4-4b90-9d68-99209e3db778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354762524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1354762524
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2569152023
Short name T371
Test name
Test status
Simulation time 4165794774 ps
CPU time 1.69 seconds
Started Mar 07 12:33:51 PM PST 24
Finished Mar 07 12:33:53 PM PST 24
Peak memory 201152 kb
Host smart-6148967e-01a5-4a1f-812f-407a00ff711c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569152023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2569152023
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.88166136
Short name T449
Test name
Test status
Simulation time 5819952495 ps
CPU time 1.79 seconds
Started Mar 07 12:33:58 PM PST 24
Finished Mar 07 12:34:00 PM PST 24
Peak memory 201036 kb
Host smart-e9bb0b1b-7740-41ec-9f78-46473d0350a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88166136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.88166136
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.2957705892
Short name T254
Test name
Test status
Simulation time 228430922485 ps
CPU time 171.33 seconds
Started Mar 07 12:33:48 PM PST 24
Finished Mar 07 12:36:40 PM PST 24
Peak memory 200908 kb
Host smart-42e13b9f-4fcf-46ef-a312-602b2b5a1562
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957705892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.2957705892
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1353833666
Short name T215
Test name
Test status
Simulation time 37801539048 ps
CPU time 21.32 seconds
Started Mar 07 12:33:55 PM PST 24
Finished Mar 07 12:34:17 PM PST 24
Peak memory 201412 kb
Host smart-4d73d306-d5dd-4dab-9efb-fbc3836fa416
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353833666 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1353833666
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3197621723
Short name T432
Test name
Test status
Simulation time 486686976 ps
CPU time 1.24 seconds
Started Mar 07 12:33:14 PM PST 24
Finished Mar 07 12:33:15 PM PST 24
Peak memory 201204 kb
Host smart-a12d2673-b2f8-4246-8d2e-d88070e180b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197621723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3197621723
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3747754661
Short name T666
Test name
Test status
Simulation time 163656448759 ps
CPU time 244.41 seconds
Started Mar 07 12:33:19 PM PST 24
Finished Mar 07 12:37:23 PM PST 24
Peak memory 201304 kb
Host smart-1d87fdb5-d1e5-4dea-b800-eccf505bb52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747754661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3747754661
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.1087604954
Short name T295
Test name
Test status
Simulation time 168830080282 ps
CPU time 84.43 seconds
Started Mar 07 12:33:19 PM PST 24
Finished Mar 07 12:34:43 PM PST 24
Peak memory 201336 kb
Host smart-a67b9791-270b-4f72-9039-12bf5d167d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087604954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1087604954
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.4089419390
Short name T91
Test name
Test status
Simulation time 319869547788 ps
CPU time 204.15 seconds
Started Mar 07 12:33:19 PM PST 24
Finished Mar 07 12:36:43 PM PST 24
Peak memory 201308 kb
Host smart-60f87084-1494-44ee-8cab-8386f41e7435
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089419390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.4089419390
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1214327658
Short name T697
Test name
Test status
Simulation time 318927570606 ps
CPU time 204.68 seconds
Started Mar 07 12:33:23 PM PST 24
Finished Mar 07 12:36:48 PM PST 24
Peak memory 201256 kb
Host smart-ed399335-977f-48e6-be78-1ff25058f5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214327658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1214327658
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1833613401
Short name T683
Test name
Test status
Simulation time 161053571239 ps
CPU time 87.55 seconds
Started Mar 07 12:33:24 PM PST 24
Finished Mar 07 12:34:52 PM PST 24
Peak memory 200720 kb
Host smart-8b2dce6e-76db-43fd-8f07-f91ade8c5db3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833613401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1833613401
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.3077109940
Short name T161
Test name
Test status
Simulation time 379238166231 ps
CPU time 177.6 seconds
Started Mar 07 12:33:32 PM PST 24
Finished Mar 07 12:36:30 PM PST 24
Peak memory 201376 kb
Host smart-cb5d43a8-c6f9-4913-8b91-e0414838128c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077109940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.3077109940
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.234392378
Short name T455
Test name
Test status
Simulation time 409241392375 ps
CPU time 88.78 seconds
Started Mar 07 12:33:23 PM PST 24
Finished Mar 07 12:34:52 PM PST 24
Peak memory 201352 kb
Host smart-0777ff02-1286-43c5-a4b6-525e9a5ec197
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234392378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.234392378
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3136449955
Short name T536
Test name
Test status
Simulation time 95011587422 ps
CPU time 330.5 seconds
Started Mar 07 12:33:19 PM PST 24
Finished Mar 07 12:38:49 PM PST 24
Peak memory 201760 kb
Host smart-47e8db64-4977-4bc6-8410-79da32804789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136449955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3136449955
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.1690725316
Short name T384
Test name
Test status
Simulation time 27261706095 ps
CPU time 34.77 seconds
Started Mar 07 12:33:18 PM PST 24
Finished Mar 07 12:33:53 PM PST 24
Peak memory 201172 kb
Host smart-901a6d9d-455c-477a-9680-f3469f89997d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690725316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1690725316
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2161881208
Short name T439
Test name
Test status
Simulation time 4314391215 ps
CPU time 3.28 seconds
Started Mar 07 12:33:22 PM PST 24
Finished Mar 07 12:33:26 PM PST 24
Peak memory 201196 kb
Host smart-013704c5-3bd7-4e12-a6d3-166e4022a3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161881208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2161881208
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1710698036
Short name T68
Test name
Test status
Simulation time 7926882918 ps
CPU time 19.55 seconds
Started Mar 07 12:33:14 PM PST 24
Finished Mar 07 12:33:34 PM PST 24
Peak memory 217624 kb
Host smart-d2100a6b-6d1f-4c1d-ac33-f00252d612f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710698036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1710698036
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.180833689
Short name T492
Test name
Test status
Simulation time 6083461642 ps
CPU time 4.39 seconds
Started Mar 07 12:33:12 PM PST 24
Finished Mar 07 12:33:17 PM PST 24
Peak memory 201268 kb
Host smart-00b44cc0-d9cf-49f5-a7c9-b1237e656624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180833689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.180833689
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1684143070
Short name T24
Test name
Test status
Simulation time 446973729 ps
CPU time 0.81 seconds
Started Mar 07 12:33:57 PM PST 24
Finished Mar 07 12:33:58 PM PST 24
Peak memory 201128 kb
Host smart-8e190440-b7b2-4fdf-b1f8-91fd3fb7c13d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684143070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1684143070
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3655393264
Short name T617
Test name
Test status
Simulation time 333227728222 ps
CPU time 457.74 seconds
Started Mar 07 12:34:00 PM PST 24
Finished Mar 07 12:41:38 PM PST 24
Peak memory 201316 kb
Host smart-23f9b6e0-c515-4a71-b41c-bb8195b48a7c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655393264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3655393264
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.4129267016
Short name T783
Test name
Test status
Simulation time 173281969570 ps
CPU time 112.36 seconds
Started Mar 07 12:34:07 PM PST 24
Finished Mar 07 12:35:59 PM PST 24
Peak memory 201324 kb
Host smart-6179e04d-8278-4cb8-879d-726866353837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129267016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.4129267016
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.4205635703
Short name T102
Test name
Test status
Simulation time 165463318980 ps
CPU time 95.88 seconds
Started Mar 07 12:34:05 PM PST 24
Finished Mar 07 12:35:42 PM PST 24
Peak memory 201296 kb
Host smart-26eb4b2f-af7c-4e8d-8755-e75f40164744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205635703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.4205635703
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2725065676
Short name T396
Test name
Test status
Simulation time 498617427568 ps
CPU time 280.22 seconds
Started Mar 07 12:33:58 PM PST 24
Finished Mar 07 12:38:39 PM PST 24
Peak memory 201368 kb
Host smart-e0941e31-fe5e-461f-bc30-f2e3cf94b829
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725065676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2725065676
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1908395554
Short name T603
Test name
Test status
Simulation time 489685730974 ps
CPU time 1128.85 seconds
Started Mar 07 12:34:02 PM PST 24
Finished Mar 07 12:52:51 PM PST 24
Peak memory 201328 kb
Host smart-752ad675-1b7b-4d38-82b2-a9cdba6d5fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908395554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1908395554
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2362393467
Short name T579
Test name
Test status
Simulation time 162215785749 ps
CPU time 368.84 seconds
Started Mar 07 12:34:06 PM PST 24
Finished Mar 07 12:40:16 PM PST 24
Peak memory 201324 kb
Host smart-890530e1-0798-4b70-a2f2-2f43bb29fb39
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362393467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2362393467
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2177377240
Short name T226
Test name
Test status
Simulation time 366456084793 ps
CPU time 925.62 seconds
Started Mar 07 12:33:50 PM PST 24
Finished Mar 07 12:49:16 PM PST 24
Peak memory 201364 kb
Host smart-ee5348f2-1da0-4f3f-ab26-b8d43988fe6b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177377240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2177377240
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1734099216
Short name T754
Test name
Test status
Simulation time 587721697153 ps
CPU time 1372.29 seconds
Started Mar 07 12:34:05 PM PST 24
Finished Mar 07 12:56:58 PM PST 24
Peak memory 201308 kb
Host smart-31cfdc93-3c30-4d7a-94b4-2f96cfdb6f26
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734099216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1734099216
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3119659659
Short name T749
Test name
Test status
Simulation time 124333138052 ps
CPU time 433.07 seconds
Started Mar 07 12:33:57 PM PST 24
Finished Mar 07 12:41:10 PM PST 24
Peak memory 201584 kb
Host smart-a9e781f3-d048-45a9-9d95-0c3d6ac73d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119659659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3119659659
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.27949706
Short name T667
Test name
Test status
Simulation time 29978351198 ps
CPU time 68.9 seconds
Started Mar 07 12:34:02 PM PST 24
Finished Mar 07 12:35:11 PM PST 24
Peak memory 201200 kb
Host smart-2041028a-0ce6-4ebb-8547-392ad973e0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27949706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.27949706
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1912166204
Short name T87
Test name
Test status
Simulation time 4081382372 ps
CPU time 5.65 seconds
Started Mar 07 12:34:01 PM PST 24
Finished Mar 07 12:34:06 PM PST 24
Peak memory 201240 kb
Host smart-e0130b12-8960-4e25-b794-6ba9ce0524a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912166204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1912166204
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1564715123
Short name T344
Test name
Test status
Simulation time 5767109601 ps
CPU time 4.04 seconds
Started Mar 07 12:33:50 PM PST 24
Finished Mar 07 12:33:54 PM PST 24
Peak memory 201176 kb
Host smart-270717f5-826a-45e5-93e1-14479f464df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564715123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1564715123
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3318348369
Short name T154
Test name
Test status
Simulation time 164572733706 ps
CPU time 97.6 seconds
Started Mar 07 12:33:59 PM PST 24
Finished Mar 07 12:35:37 PM PST 24
Peak memory 201424 kb
Host smart-dc5403d9-fae6-49e4-95b9-e6341e496fab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318348369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3318348369
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.554761209
Short name T436
Test name
Test status
Simulation time 422609591 ps
CPU time 0.87 seconds
Started Mar 07 12:33:59 PM PST 24
Finished Mar 07 12:34:00 PM PST 24
Peak memory 201144 kb
Host smart-bd857b9f-5198-49a4-abd8-7e55a0570d21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554761209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.554761209
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.3735836687
Short name T678
Test name
Test status
Simulation time 378217296705 ps
CPU time 824.29 seconds
Started Mar 07 12:33:54 PM PST 24
Finished Mar 07 12:47:40 PM PST 24
Peak memory 201380 kb
Host smart-460c4e6d-83af-40e6-b9b9-c5218814b7e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735836687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.3735836687
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3166777208
Short name T200
Test name
Test status
Simulation time 531521261935 ps
CPU time 1251.92 seconds
Started Mar 07 12:34:04 PM PST 24
Finished Mar 07 12:54:56 PM PST 24
Peak memory 201264 kb
Host smart-892d1d0c-c245-4570-8561-6a1bf897ab67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166777208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3166777208
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2548611137
Short name T319
Test name
Test status
Simulation time 331873475753 ps
CPU time 416.49 seconds
Started Mar 07 12:34:02 PM PST 24
Finished Mar 07 12:40:59 PM PST 24
Peak memory 201300 kb
Host smart-8f328009-92b1-45d7-932b-1e2cd101827e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548611137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2548611137
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3420369844
Short name T400
Test name
Test status
Simulation time 160664336167 ps
CPU time 108.29 seconds
Started Mar 07 12:33:59 PM PST 24
Finished Mar 07 12:35:47 PM PST 24
Peak memory 201360 kb
Host smart-23d4c6de-da7c-4454-8c00-26697cd3f98b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420369844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3420369844
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1428449470
Short name T671
Test name
Test status
Simulation time 165509564657 ps
CPU time 364.05 seconds
Started Mar 07 12:34:00 PM PST 24
Finished Mar 07 12:40:05 PM PST 24
Peak memory 201328 kb
Host smart-e9702eb1-97f5-4cc5-aec2-f25547bca67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428449470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1428449470
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3763063292
Short name T407
Test name
Test status
Simulation time 324519320105 ps
CPU time 833.19 seconds
Started Mar 07 12:34:04 PM PST 24
Finished Mar 07 12:47:58 PM PST 24
Peak memory 201204 kb
Host smart-79642e80-8204-4855-a63e-72740977d026
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763063292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3763063292
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3740750084
Short name T311
Test name
Test status
Simulation time 545882486152 ps
CPU time 1294.85 seconds
Started Mar 07 12:33:57 PM PST 24
Finished Mar 07 12:55:32 PM PST 24
Peak memory 201236 kb
Host smart-a668954f-0de5-42ad-81c2-dc3b8bf1a198
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740750084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3740750084
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2983797291
Short name T25
Test name
Test status
Simulation time 396634138424 ps
CPU time 168.88 seconds
Started Mar 07 12:34:04 PM PST 24
Finished Mar 07 12:36:53 PM PST 24
Peak memory 201384 kb
Host smart-37fa1745-3189-490c-9f07-6cfe11f4ccea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983797291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2983797291
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.469066340
Short name T788
Test name
Test status
Simulation time 21462594933 ps
CPU time 5.58 seconds
Started Mar 07 12:34:03 PM PST 24
Finished Mar 07 12:34:08 PM PST 24
Peak memory 201196 kb
Host smart-9451fc33-f676-4ad6-9b01-6c1de0be20ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469066340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.469066340
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3732477309
Short name T401
Test name
Test status
Simulation time 3209793240 ps
CPU time 1.79 seconds
Started Mar 07 12:34:04 PM PST 24
Finished Mar 07 12:34:06 PM PST 24
Peak memory 201080 kb
Host smart-12d2ca72-9308-47e3-af07-99a6d78aedfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732477309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3732477309
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1537439066
Short name T781
Test name
Test status
Simulation time 5561131290 ps
CPU time 6.8 seconds
Started Mar 07 12:33:51 PM PST 24
Finished Mar 07 12:33:58 PM PST 24
Peak memory 201188 kb
Host smart-1b261d86-01bd-420b-a9e4-388e14058bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537439066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1537439066
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.247717906
Short name T768
Test name
Test status
Simulation time 334066020155 ps
CPU time 128.3 seconds
Started Mar 07 12:34:03 PM PST 24
Finished Mar 07 12:36:11 PM PST 24
Peak memory 201348 kb
Host smart-6d2180f5-ccb2-4894-ab9b-184ff697807a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247717906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
247717906
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3325565866
Short name T770
Test name
Test status
Simulation time 517970972 ps
CPU time 0.91 seconds
Started Mar 07 12:33:58 PM PST 24
Finished Mar 07 12:33:59 PM PST 24
Peak memory 201128 kb
Host smart-6b1bd3d5-7a8a-4c08-8067-d323e0f483b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325565866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3325565866
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3449676354
Short name T139
Test name
Test status
Simulation time 544683714433 ps
CPU time 202.04 seconds
Started Mar 07 12:34:07 PM PST 24
Finished Mar 07 12:37:29 PM PST 24
Peak memory 201384 kb
Host smart-7ea20146-6649-4a3d-997e-e8b2a288d775
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449676354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3449676354
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.881192460
Short name T163
Test name
Test status
Simulation time 516816940768 ps
CPU time 234.8 seconds
Started Mar 07 12:33:54 PM PST 24
Finished Mar 07 12:37:50 PM PST 24
Peak memory 201312 kb
Host smart-63394e5b-bba9-462e-b980-dc5d30bb7a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881192460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.881192460
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1361903267
Short name T131
Test name
Test status
Simulation time 488640395177 ps
CPU time 1180.48 seconds
Started Mar 07 12:34:07 PM PST 24
Finished Mar 07 12:53:48 PM PST 24
Peak memory 201380 kb
Host smart-803b9f99-d3d8-4643-bb65-fd200dbc1c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361903267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1361903267
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1378580824
Short name T769
Test name
Test status
Simulation time 164961354504 ps
CPU time 102.08 seconds
Started Mar 07 12:33:58 PM PST 24
Finished Mar 07 12:35:40 PM PST 24
Peak memory 201312 kb
Host smart-12b87ab0-d89e-4faa-9a20-b513ac1a602f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378580824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1378580824
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.4009837857
Short name T234
Test name
Test status
Simulation time 162701309777 ps
CPU time 189.33 seconds
Started Mar 07 12:34:01 PM PST 24
Finished Mar 07 12:37:10 PM PST 24
Peak memory 201316 kb
Host smart-8a2027b7-2ce3-478b-9b64-7f090c50f540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009837857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.4009837857
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.368097602
Short name T97
Test name
Test status
Simulation time 492170698261 ps
CPU time 603.82 seconds
Started Mar 07 12:33:53 PM PST 24
Finished Mar 07 12:43:59 PM PST 24
Peak memory 201088 kb
Host smart-b2c00820-1129-4133-bdb2-53193393742f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=368097602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.368097602
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3698522009
Short name T615
Test name
Test status
Simulation time 171472207592 ps
CPU time 381.27 seconds
Started Mar 07 12:33:55 PM PST 24
Finished Mar 07 12:40:17 PM PST 24
Peak memory 201308 kb
Host smart-73105fc8-c380-4606-b4c5-30ea679a0a83
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698522009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3698522009
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3140605109
Short name T548
Test name
Test status
Simulation time 399547730080 ps
CPU time 122.68 seconds
Started Mar 07 12:34:09 PM PST 24
Finished Mar 07 12:36:12 PM PST 24
Peak memory 201320 kb
Host smart-b9656e73-703e-4cbf-b800-f5648540e787
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140605109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3140605109
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.1213221329
Short name T498
Test name
Test status
Simulation time 140587774489 ps
CPU time 744.56 seconds
Started Mar 07 12:34:00 PM PST 24
Finished Mar 07 12:46:25 PM PST 24
Peak memory 201700 kb
Host smart-21367bab-4abe-4736-b88c-4bf12f66033d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213221329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1213221329
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.528421666
Short name T463
Test name
Test status
Simulation time 29747466837 ps
CPU time 18.62 seconds
Started Mar 07 12:34:13 PM PST 24
Finished Mar 07 12:34:32 PM PST 24
Peak memory 201196 kb
Host smart-b715a0c8-4f12-47ce-a486-d2a5c6a611ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528421666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.528421666
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.703520393
Short name T481
Test name
Test status
Simulation time 4805410879 ps
CPU time 3.68 seconds
Started Mar 07 12:34:01 PM PST 24
Finished Mar 07 12:34:05 PM PST 24
Peak memory 201096 kb
Host smart-4e8a8723-fd88-4b2a-9cad-97c95018610b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703520393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.703520393
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3248771179
Short name T368
Test name
Test status
Simulation time 5452131045 ps
CPU time 3.83 seconds
Started Mar 07 12:34:00 PM PST 24
Finished Mar 07 12:34:04 PM PST 24
Peak memory 201180 kb
Host smart-0f91a5a5-3bf5-4b2c-badc-91b8391ce43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248771179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3248771179
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2545479557
Short name T649
Test name
Test status
Simulation time 510440449019 ps
CPU time 610.12 seconds
Started Mar 07 12:34:10 PM PST 24
Finished Mar 07 12:44:21 PM PST 24
Peak memory 201380 kb
Host smart-c23bd93c-023c-4a7b-8323-fb4c42872e2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545479557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2545479557
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3923253188
Short name T338
Test name
Test status
Simulation time 48803206065 ps
CPU time 92.42 seconds
Started Mar 07 12:34:01 PM PST 24
Finished Mar 07 12:35:34 PM PST 24
Peak memory 210056 kb
Host smart-db6b7ba2-7f1a-4428-bb45-469bb3ef54fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923253188 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3923253188
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.4095080348
Short name T63
Test name
Test status
Simulation time 428993377 ps
CPU time 1.14 seconds
Started Mar 07 12:34:00 PM PST 24
Finished Mar 07 12:34:01 PM PST 24
Peak memory 201096 kb
Host smart-0812be39-e8aa-4840-9a6e-6cc9f8a3c85c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095080348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.4095080348
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3145177888
Short name T167
Test name
Test status
Simulation time 157718550485 ps
CPU time 87.14 seconds
Started Mar 07 12:34:00 PM PST 24
Finished Mar 07 12:35:27 PM PST 24
Peak memory 201304 kb
Host smart-4ffbe444-8017-43d3-aacd-016662978c71
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145177888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3145177888
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2945202932
Short name T268
Test name
Test status
Simulation time 534270287732 ps
CPU time 1205.1 seconds
Started Mar 07 12:34:09 PM PST 24
Finished Mar 07 12:54:15 PM PST 24
Peak memory 201312 kb
Host smart-bb598794-d556-409d-b696-e88b7327ece5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945202932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2945202932
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.879965203
Short name T623
Test name
Test status
Simulation time 164233858528 ps
CPU time 162.55 seconds
Started Mar 07 12:34:14 PM PST 24
Finished Mar 07 12:36:57 PM PST 24
Peak memory 201324 kb
Host smart-ed067db9-d63d-4200-a73a-b99aad66ec7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879965203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.879965203
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.4159440208
Short name T166
Test name
Test status
Simulation time 497489549660 ps
CPU time 312.41 seconds
Started Mar 07 12:34:00 PM PST 24
Finished Mar 07 12:39:12 PM PST 24
Peak memory 201360 kb
Host smart-e7251d3c-4f57-46be-b520-939501e5a0c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159440208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.4159440208
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.827191802
Short name T165
Test name
Test status
Simulation time 319560005571 ps
CPU time 182.73 seconds
Started Mar 07 12:34:10 PM PST 24
Finished Mar 07 12:37:13 PM PST 24
Peak memory 201312 kb
Host smart-545e97ae-a887-4bde-b2d4-4931f2941e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827191802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.827191802
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1428381468
Short name T570
Test name
Test status
Simulation time 331386331709 ps
CPU time 105.63 seconds
Started Mar 07 12:33:59 PM PST 24
Finished Mar 07 12:35:44 PM PST 24
Peak memory 201384 kb
Host smart-a3d9ff05-1732-4f66-8a24-ebea9a743051
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428381468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1428381468
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1301140262
Short name T726
Test name
Test status
Simulation time 586753494474 ps
CPU time 269.36 seconds
Started Mar 07 12:34:02 PM PST 24
Finished Mar 07 12:38:32 PM PST 24
Peak memory 201320 kb
Host smart-1f2902eb-fdbf-4356-bd10-d01af1de1987
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301140262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1301140262
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.363575395
Short name T429
Test name
Test status
Simulation time 418941129503 ps
CPU time 105.48 seconds
Started Mar 07 12:34:13 PM PST 24
Finished Mar 07 12:35:59 PM PST 24
Peak memory 201380 kb
Host smart-451318f2-5962-4671-9efe-03db1abf1211
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363575395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.363575395
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.1473368861
Short name T423
Test name
Test status
Simulation time 148322860943 ps
CPU time 719.37 seconds
Started Mar 07 12:34:03 PM PST 24
Finished Mar 07 12:46:02 PM PST 24
Peak memory 201756 kb
Host smart-23c0fff8-d566-4c47-8d0d-d19c0ad202e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473368861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.1473368861
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.322553518
Short name T676
Test name
Test status
Simulation time 27470883152 ps
CPU time 68.78 seconds
Started Mar 07 12:34:04 PM PST 24
Finished Mar 07 12:35:13 PM PST 24
Peak memory 201196 kb
Host smart-4a55e46e-e3f5-4f0c-9f6a-e1d1488da8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322553518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.322553518
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3985022233
Short name T88
Test name
Test status
Simulation time 4546360031 ps
CPU time 3.67 seconds
Started Mar 07 12:33:58 PM PST 24
Finished Mar 07 12:34:07 PM PST 24
Peak memory 201176 kb
Host smart-c2ec3d40-3fe2-4fa2-bed4-4dded97505e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985022233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3985022233
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.4150586477
Short name T378
Test name
Test status
Simulation time 6111614625 ps
CPU time 4.62 seconds
Started Mar 07 12:34:13 PM PST 24
Finished Mar 07 12:34:19 PM PST 24
Peak memory 201180 kb
Host smart-9682814d-91c8-446b-a983-8455d31f3daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150586477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.4150586477
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2963958809
Short name T762
Test name
Test status
Simulation time 251194220743 ps
CPU time 749.11 seconds
Started Mar 07 12:34:05 PM PST 24
Finished Mar 07 12:46:35 PM PST 24
Peak memory 201688 kb
Host smart-fb99cc39-ac5e-4ddf-ba11-ec77a3a43f05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963958809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2963958809
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2714564805
Short name T99
Test name
Test status
Simulation time 82539272516 ps
CPU time 55.61 seconds
Started Mar 07 12:34:03 PM PST 24
Finished Mar 07 12:34:59 PM PST 24
Peak memory 210072 kb
Host smart-aacac628-9b9e-44b6-a5f3-4ff9a5a0fac3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714564805 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2714564805
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1231577963
Short name T385
Test name
Test status
Simulation time 369984289 ps
CPU time 1.05 seconds
Started Mar 07 12:34:09 PM PST 24
Finished Mar 07 12:34:10 PM PST 24
Peak memory 201120 kb
Host smart-9e7a7d3a-16df-461e-9bb9-da811745ba3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231577963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1231577963
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2045864179
Short name T774
Test name
Test status
Simulation time 519725482149 ps
CPU time 765.46 seconds
Started Mar 07 12:34:12 PM PST 24
Finished Mar 07 12:46:58 PM PST 24
Peak memory 201332 kb
Host smart-f91be372-07b9-4554-8741-ff054ad39294
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045864179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2045864179
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1234013708
Short name T670
Test name
Test status
Simulation time 168803378168 ps
CPU time 98.17 seconds
Started Mar 07 12:34:01 PM PST 24
Finished Mar 07 12:35:39 PM PST 24
Peak memory 201280 kb
Host smart-3be49f03-5c79-406c-83bd-b10e7570769e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234013708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1234013708
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3515788499
Short name T147
Test name
Test status
Simulation time 481751128476 ps
CPU time 275.2 seconds
Started Mar 07 12:34:05 PM PST 24
Finished Mar 07 12:38:41 PM PST 24
Peak memory 201304 kb
Host smart-2af55bf0-0211-4979-9663-6baa3a8d2d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515788499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3515788499
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.1475137179
Short name T487
Test name
Test status
Simulation time 165190417330 ps
CPU time 194.15 seconds
Started Mar 07 12:34:20 PM PST 24
Finished Mar 07 12:37:35 PM PST 24
Peak memory 201316 kb
Host smart-7d0b9404-acd0-4f78-bff2-401eedfe3080
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475137179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.1475137179
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.92255644
Short name T545
Test name
Test status
Simulation time 163049738348 ps
CPU time 383.15 seconds
Started Mar 07 12:34:06 PM PST 24
Finished Mar 07 12:40:30 PM PST 24
Peak memory 201320 kb
Host smart-18a6cb47-6fa7-4d74-8625-6b66ffc8aec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92255644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.92255644
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2651527392
Short name T693
Test name
Test status
Simulation time 163414209428 ps
CPU time 154.07 seconds
Started Mar 07 12:34:00 PM PST 24
Finished Mar 07 12:36:34 PM PST 24
Peak memory 201324 kb
Host smart-26e01fda-776d-4d9c-93a4-f910f720af14
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651527392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2651527392
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3987299240
Short name T587
Test name
Test status
Simulation time 371021133869 ps
CPU time 378.44 seconds
Started Mar 07 12:34:11 PM PST 24
Finished Mar 07 12:40:30 PM PST 24
Peak memory 201380 kb
Host smart-514828ec-4f5f-4063-92e3-bff4172d28af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987299240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3987299240
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1412903936
Short name T347
Test name
Test status
Simulation time 615716346336 ps
CPU time 1526.11 seconds
Started Mar 07 12:34:09 PM PST 24
Finished Mar 07 12:59:35 PM PST 24
Peak memory 201308 kb
Host smart-925f6e08-07cc-4efd-8075-8361f713cb34
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412903936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1412903936
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1462899549
Short name T778
Test name
Test status
Simulation time 116588145546 ps
CPU time 632.68 seconds
Started Mar 07 12:34:08 PM PST 24
Finished Mar 07 12:44:42 PM PST 24
Peak memory 201760 kb
Host smart-226bf512-2438-4e6e-8d16-3382ac369f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462899549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1462899549
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3145002858
Short name T717
Test name
Test status
Simulation time 33482228008 ps
CPU time 76.74 seconds
Started Mar 07 12:34:01 PM PST 24
Finished Mar 07 12:35:18 PM PST 24
Peak memory 201180 kb
Host smart-bca75b7f-4794-484a-96dc-ed015384aef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145002858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3145002858
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1487862547
Short name T10
Test name
Test status
Simulation time 3139483889 ps
CPU time 8.41 seconds
Started Mar 07 12:33:59 PM PST 24
Finished Mar 07 12:34:08 PM PST 24
Peak memory 201148 kb
Host smart-acca3801-9870-4d16-9a85-f7416665236a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487862547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1487862547
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2275910626
Short name T721
Test name
Test status
Simulation time 5845497127 ps
CPU time 2.16 seconds
Started Mar 07 12:34:06 PM PST 24
Finished Mar 07 12:34:09 PM PST 24
Peak memory 201152 kb
Host smart-e369c9c7-15dc-470e-b88e-76a6f95625c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275910626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2275910626
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2130288660
Short name T751
Test name
Test status
Simulation time 103764070097 ps
CPU time 44.16 seconds
Started Mar 07 12:34:09 PM PST 24
Finished Mar 07 12:34:53 PM PST 24
Peak memory 201488 kb
Host smart-d863b59c-778b-49b1-9aea-df6af91531a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130288660 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2130288660
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1410450959
Short name T405
Test name
Test status
Simulation time 586881946 ps
CPU time 0.69 seconds
Started Mar 07 12:34:07 PM PST 24
Finished Mar 07 12:34:08 PM PST 24
Peak memory 201124 kb
Host smart-63b13e37-2250-4d50-9d8d-07d659735141
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410450959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1410450959
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.819769492
Short name T211
Test name
Test status
Simulation time 356784995121 ps
CPU time 72.89 seconds
Started Mar 07 12:34:16 PM PST 24
Finished Mar 07 12:35:33 PM PST 24
Peak memory 201356 kb
Host smart-700cade6-7db4-4a17-afd6-d5d2fc49777c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819769492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.819769492
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3568455607
Short name T223
Test name
Test status
Simulation time 488877041943 ps
CPU time 181.89 seconds
Started Mar 07 12:34:00 PM PST 24
Finished Mar 07 12:37:02 PM PST 24
Peak memory 201404 kb
Host smart-cc2c32db-5a7a-4788-8d37-90c04f02863f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568455607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3568455607
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3861846745
Short name T476
Test name
Test status
Simulation time 492050946642 ps
CPU time 1088.95 seconds
Started Mar 07 12:34:02 PM PST 24
Finished Mar 07 12:52:12 PM PST 24
Peak memory 201388 kb
Host smart-270b4a77-2c65-42b4-803c-b88d5c85fc5b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861846745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3861846745
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2389305579
Short name T763
Test name
Test status
Simulation time 163564012028 ps
CPU time 207.79 seconds
Started Mar 07 12:34:00 PM PST 24
Finished Mar 07 12:37:28 PM PST 24
Peak memory 201336 kb
Host smart-0d41af9e-5b1e-4a26-82ae-981e560e965b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389305579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2389305579
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.4125496420
Short name T379
Test name
Test status
Simulation time 334918811250 ps
CPU time 212.76 seconds
Started Mar 07 12:34:04 PM PST 24
Finished Mar 07 12:37:37 PM PST 24
Peak memory 201236 kb
Host smart-0796760d-cf47-4599-95b2-05416d788b7d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125496420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.4125496420
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3838753940
Short name T317
Test name
Test status
Simulation time 515967304979 ps
CPU time 1319.87 seconds
Started Mar 07 12:34:12 PM PST 24
Finished Mar 07 12:56:12 PM PST 24
Peak memory 201392 kb
Host smart-50fb7d81-2b8c-47d8-a655-ce3be78c5597
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838753940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3838753940
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1286681779
Short name T621
Test name
Test status
Simulation time 587935582841 ps
CPU time 112.81 seconds
Started Mar 07 12:34:07 PM PST 24
Finished Mar 07 12:36:00 PM PST 24
Peak memory 201408 kb
Host smart-3eb93e4c-ca4a-414a-bff7-cf652a8e62f4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286681779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1286681779
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1203562467
Short name T333
Test name
Test status
Simulation time 94149727854 ps
CPU time 279.64 seconds
Started Mar 07 12:34:00 PM PST 24
Finished Mar 07 12:38:39 PM PST 24
Peak memory 201672 kb
Host smart-41919453-98ca-4d64-bc62-eb29651c3b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203562467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1203562467
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1960776336
Short name T716
Test name
Test status
Simulation time 31192929902 ps
CPU time 22.02 seconds
Started Mar 07 12:34:04 PM PST 24
Finished Mar 07 12:34:26 PM PST 24
Peak memory 201196 kb
Host smart-b05292d8-6676-4348-ac1c-2421d4ae1889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960776336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1960776336
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3548595062
Short name T482
Test name
Test status
Simulation time 3406393507 ps
CPU time 2.31 seconds
Started Mar 07 12:34:13 PM PST 24
Finished Mar 07 12:34:16 PM PST 24
Peak memory 201152 kb
Host smart-5377500d-9b08-4890-ab3f-ae669568d130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548595062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3548595062
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1882272825
Short name T352
Test name
Test status
Simulation time 6143212983 ps
CPU time 4.35 seconds
Started Mar 07 12:34:07 PM PST 24
Finished Mar 07 12:34:11 PM PST 24
Peak memory 201188 kb
Host smart-b8685cc4-483b-441e-9c79-29e2240fed4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882272825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1882272825
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3354870650
Short name T663
Test name
Test status
Simulation time 370239968721 ps
CPU time 206.34 seconds
Started Mar 07 12:34:15 PM PST 24
Finished Mar 07 12:37:44 PM PST 24
Peak memory 201304 kb
Host smart-409e4f0c-f58c-4431-81d5-27e0dd98808a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354870650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3354870650
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.85774490
Short name T410
Test name
Test status
Simulation time 397195669 ps
CPU time 1.54 seconds
Started Mar 07 12:34:00 PM PST 24
Finished Mar 07 12:34:02 PM PST 24
Peak memory 201136 kb
Host smart-a740f5b6-adbd-4aa7-817c-b33c4e293c48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85774490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.85774490
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.502863424
Short name T248
Test name
Test status
Simulation time 513872177319 ps
CPU time 781.16 seconds
Started Mar 07 12:34:06 PM PST 24
Finished Mar 07 12:47:07 PM PST 24
Peak memory 201360 kb
Host smart-789e9147-6b8d-4db5-a8ad-990c5ac541ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502863424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati
ng.502863424
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.966669211
Short name T662
Test name
Test status
Simulation time 185220618638 ps
CPU time 229.21 seconds
Started Mar 07 12:34:03 PM PST 24
Finished Mar 07 12:37:53 PM PST 24
Peak memory 201320 kb
Host smart-0d916294-19b8-4692-8c41-56ed791751eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966669211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.966669211
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.316238222
Short name T207
Test name
Test status
Simulation time 164653632245 ps
CPU time 357.43 seconds
Started Mar 07 12:34:09 PM PST 24
Finished Mar 07 12:40:07 PM PST 24
Peak memory 201336 kb
Host smart-67eec061-f492-4e91-a090-52f274a45b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316238222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.316238222
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.481647703
Short name T152
Test name
Test status
Simulation time 168486186502 ps
CPU time 43.49 seconds
Started Mar 07 12:34:07 PM PST 24
Finished Mar 07 12:34:50 PM PST 24
Peak memory 201460 kb
Host smart-8ecd273d-a256-48ce-8775-00595411aae3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=481647703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.481647703
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3150871407
Short name T294
Test name
Test status
Simulation time 167965248872 ps
CPU time 97.13 seconds
Started Mar 07 12:34:07 PM PST 24
Finished Mar 07 12:35:44 PM PST 24
Peak memory 201372 kb
Host smart-6d4f9cec-b550-4278-b097-5c59dc93d648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150871407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3150871407
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3015719402
Short name T515
Test name
Test status
Simulation time 160404417508 ps
CPU time 372.72 seconds
Started Mar 07 12:34:19 PM PST 24
Finished Mar 07 12:40:34 PM PST 24
Peak memory 201136 kb
Host smart-7c097fbd-dc14-4b2e-b32c-aab074445c55
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015719402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3015719402
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3973291540
Short name T225
Test name
Test status
Simulation time 374278269144 ps
CPU time 222.07 seconds
Started Mar 07 12:34:19 PM PST 24
Finished Mar 07 12:38:03 PM PST 24
Peak memory 201312 kb
Host smart-22ca5574-ee4d-45df-aa9c-98ce092b826e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973291540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3973291540
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2755543269
Short name T567
Test name
Test status
Simulation time 603223359150 ps
CPU time 728.59 seconds
Started Mar 07 12:34:07 PM PST 24
Finished Mar 07 12:46:15 PM PST 24
Peak memory 201288 kb
Host smart-c5e7256e-87cb-4721-b2ba-6fd0d35f5e34
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755543269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2755543269
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1983490717
Short name T425
Test name
Test status
Simulation time 109091296562 ps
CPU time 579.76 seconds
Started Mar 07 12:34:13 PM PST 24
Finished Mar 07 12:43:53 PM PST 24
Peak memory 201768 kb
Host smart-3c12d9c0-77a7-4fc6-ac1f-a3adf36ca7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983490717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1983490717
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1700235340
Short name T340
Test name
Test status
Simulation time 28786976328 ps
CPU time 63.03 seconds
Started Mar 07 12:34:09 PM PST 24
Finished Mar 07 12:35:12 PM PST 24
Peak memory 201184 kb
Host smart-b8659f81-ac73-468c-a128-405d4b873314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700235340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1700235340
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3516921721
Short name T414
Test name
Test status
Simulation time 4032703211 ps
CPU time 2.16 seconds
Started Mar 07 12:34:03 PM PST 24
Finished Mar 07 12:34:06 PM PST 24
Peak memory 201156 kb
Host smart-9be0d701-2881-44ec-84e4-325ef010191f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516921721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3516921721
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1892474187
Short name T395
Test name
Test status
Simulation time 5882416353 ps
CPU time 1.95 seconds
Started Mar 07 12:34:12 PM PST 24
Finished Mar 07 12:34:15 PM PST 24
Peak memory 201252 kb
Host smart-fb59c681-a019-41bf-9e0d-77e4dc90d5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892474187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1892474187
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.658121511
Short name T702
Test name
Test status
Simulation time 600143041587 ps
CPU time 352.78 seconds
Started Mar 07 12:34:06 PM PST 24
Finished Mar 07 12:39:59 PM PST 24
Peak memory 201320 kb
Host smart-097dd0c8-8c1e-4a47-8c98-33de89af5e47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658121511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
658121511
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.241441829
Short name T625
Test name
Test status
Simulation time 314667472500 ps
CPU time 317.67 seconds
Started Mar 07 12:34:08 PM PST 24
Finished Mar 07 12:39:26 PM PST 24
Peak memory 211160 kb
Host smart-7f3349e6-213f-4137-a3a4-0271f4cf3355
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241441829 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.241441829
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2362601267
Short name T544
Test name
Test status
Simulation time 316315429 ps
CPU time 0.92 seconds
Started Mar 07 12:34:07 PM PST 24
Finished Mar 07 12:34:08 PM PST 24
Peak memory 200984 kb
Host smart-385a9211-2660-4df6-991e-8135c85f58b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362601267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2362601267
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1536766237
Short name T443
Test name
Test status
Simulation time 258062758284 ps
CPU time 240.29 seconds
Started Mar 07 12:34:19 PM PST 24
Finished Mar 07 12:38:21 PM PST 24
Peak memory 201316 kb
Host smart-16e7205d-2b4b-4ee1-9fdf-4614871e2198
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536766237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1536766237
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1441810760
Short name T255
Test name
Test status
Simulation time 447716706492 ps
CPU time 1084.42 seconds
Started Mar 07 12:34:16 PM PST 24
Finished Mar 07 12:52:23 PM PST 24
Peak memory 201312 kb
Host smart-f567f030-dc13-46d9-85eb-64685607abfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441810760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1441810760
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.4082300915
Short name T392
Test name
Test status
Simulation time 166845721440 ps
CPU time 191.15 seconds
Started Mar 07 12:34:08 PM PST 24
Finished Mar 07 12:37:19 PM PST 24
Peak memory 201376 kb
Host smart-eebf9c3a-6548-4028-b543-2dfddc73082a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082300915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.4082300915
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2065830290
Short name T493
Test name
Test status
Simulation time 165736372344 ps
CPU time 389.53 seconds
Started Mar 07 12:34:17 PM PST 24
Finished Mar 07 12:40:50 PM PST 24
Peak memory 201376 kb
Host smart-ab16cb14-9833-41c1-9ed6-fcd32806d77e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065830290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2065830290
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.4158257691
Short name T148
Test name
Test status
Simulation time 331486856597 ps
CPU time 93.13 seconds
Started Mar 07 12:34:21 PM PST 24
Finished Mar 07 12:35:55 PM PST 24
Peak memory 201332 kb
Host smart-edc5a794-6ea8-49de-9482-de36edf5af3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158257691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.4158257691
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.274685097
Short name T422
Test name
Test status
Simulation time 326106950149 ps
CPU time 836.53 seconds
Started Mar 07 12:34:14 PM PST 24
Finished Mar 07 12:48:11 PM PST 24
Peak memory 201320 kb
Host smart-e785a409-3891-4eff-a384-73e67d74400b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=274685097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.274685097
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3095040568
Short name T760
Test name
Test status
Simulation time 195697417203 ps
CPU time 231.76 seconds
Started Mar 07 12:34:08 PM PST 24
Finished Mar 07 12:38:00 PM PST 24
Peak memory 201388 kb
Host smart-13f524c6-977a-4470-b40b-e17c8558a9a8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095040568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3095040568
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1461111976
Short name T483
Test name
Test status
Simulation time 405330429685 ps
CPU time 134.2 seconds
Started Mar 07 12:35:42 PM PST 24
Finished Mar 07 12:37:58 PM PST 24
Peak memory 200892 kb
Host smart-d84e923e-214f-47c5-b056-965268ef7cb3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461111976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.1461111976
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3398020160
Short name T605
Test name
Test status
Simulation time 104450925494 ps
CPU time 363.89 seconds
Started Mar 07 12:34:08 PM PST 24
Finished Mar 07 12:40:13 PM PST 24
Peak memory 201692 kb
Host smart-c8b75625-8135-4dfb-b32f-5ab5c2853748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398020160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3398020160
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3937040491
Short name T656
Test name
Test status
Simulation time 23103139580 ps
CPU time 13.09 seconds
Started Mar 07 12:33:58 PM PST 24
Finished Mar 07 12:34:11 PM PST 24
Peak memory 201288 kb
Host smart-e49d15fa-ae8f-4c7a-acc4-d40b25d1d3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937040491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3937040491
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3816012037
Short name T558
Test name
Test status
Simulation time 3280134793 ps
CPU time 2.54 seconds
Started Mar 07 12:34:19 PM PST 24
Finished Mar 07 12:34:23 PM PST 24
Peak memory 201156 kb
Host smart-5a19047f-c186-4d1d-965e-9778efe0309c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816012037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3816012037
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.1375995989
Short name T729
Test name
Test status
Simulation time 6015845949 ps
CPU time 14.58 seconds
Started Mar 07 12:34:00 PM PST 24
Finished Mar 07 12:34:15 PM PST 24
Peak memory 201196 kb
Host smart-db7fe5ae-976b-4234-8965-79ea43d92553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375995989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1375995989
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1410521707
Short name T21
Test name
Test status
Simulation time 187672544688 ps
CPU time 216.47 seconds
Started Mar 07 12:34:21 PM PST 24
Finished Mar 07 12:37:58 PM PST 24
Peak memory 209920 kb
Host smart-a240ac43-7003-4177-8337-bc2b2f21ebfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410521707 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.1410521707
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1732463514
Short name T387
Test name
Test status
Simulation time 507385368 ps
CPU time 1.7 seconds
Started Mar 07 12:34:21 PM PST 24
Finished Mar 07 12:34:23 PM PST 24
Peak memory 200196 kb
Host smart-24873787-2fc8-47a8-bec9-27df9e978f5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732463514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1732463514
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.443348846
Short name T14
Test name
Test status
Simulation time 167044031238 ps
CPU time 325.1 seconds
Started Mar 07 12:34:02 PM PST 24
Finished Mar 07 12:39:28 PM PST 24
Peak memory 201200 kb
Host smart-0760345c-fff8-42b4-aac8-87bed41110c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443348846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.443348846
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.2553639919
Short name T256
Test name
Test status
Simulation time 245265762235 ps
CPU time 58.93 seconds
Started Mar 07 12:35:27 PM PST 24
Finished Mar 07 12:36:27 PM PST 24
Peak memory 200120 kb
Host smart-dcfd2fe4-fc44-4112-82c4-22bb3f1de7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553639919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.2553639919
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2966154252
Short name T315
Test name
Test status
Simulation time 334516352386 ps
CPU time 399.03 seconds
Started Mar 07 12:34:04 PM PST 24
Finished Mar 07 12:40:44 PM PST 24
Peak memory 201376 kb
Host smart-80201105-c951-40d4-9ad5-ebeb94ff979e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966154252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2966154252
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3132109193
Short name T531
Test name
Test status
Simulation time 498560170368 ps
CPU time 333.24 seconds
Started Mar 07 12:34:02 PM PST 24
Finished Mar 07 12:39:36 PM PST 24
Peak memory 201184 kb
Host smart-1de59147-e581-4610-858f-a0e50d04219a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132109193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3132109193
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.206322418
Short name T564
Test name
Test status
Simulation time 339108204495 ps
CPU time 196.95 seconds
Started Mar 07 12:34:12 PM PST 24
Finished Mar 07 12:37:29 PM PST 24
Peak memory 201316 kb
Host smart-74d0c049-71ef-48f3-9bf3-3524b348304a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206322418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.206322418
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3760221287
Short name T542
Test name
Test status
Simulation time 160793055752 ps
CPU time 291.3 seconds
Started Mar 07 12:34:08 PM PST 24
Finished Mar 07 12:38:59 PM PST 24
Peak memory 201320 kb
Host smart-b9909f58-56be-480f-a2e6-88d0be447a60
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760221287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3760221287
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3293555392
Short name T325
Test name
Test status
Simulation time 350757193329 ps
CPU time 229.96 seconds
Started Mar 07 12:34:06 PM PST 24
Finished Mar 07 12:37:56 PM PST 24
Peak memory 201308 kb
Host smart-90a922b1-fe83-4c23-af27-0aa08d84e3b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293555392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3293555392
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1485814739
Short name T660
Test name
Test status
Simulation time 194801609619 ps
CPU time 455.11 seconds
Started Mar 07 12:34:15 PM PST 24
Finished Mar 07 12:41:51 PM PST 24
Peak memory 201376 kb
Host smart-b1ae094d-c8b7-4235-a114-2b917d8ad23c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485814739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1485814739
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.886464099
Short name T604
Test name
Test status
Simulation time 89755599240 ps
CPU time 468.82 seconds
Started Mar 07 12:35:42 PM PST 24
Finished Mar 07 12:43:32 PM PST 24
Peak memory 201304 kb
Host smart-1e0eeb83-6300-46e1-b4a8-91fc04407c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886464099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.886464099
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.20475595
Short name T559
Test name
Test status
Simulation time 38834799437 ps
CPU time 90.43 seconds
Started Mar 07 12:34:06 PM PST 24
Finished Mar 07 12:35:37 PM PST 24
Peak memory 201152 kb
Host smart-17da0dea-03f0-464e-80d4-aed1504d020b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20475595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.20475595
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3146798347
Short name T692
Test name
Test status
Simulation time 3418824502 ps
CPU time 5.14 seconds
Started Mar 07 12:34:00 PM PST 24
Finished Mar 07 12:34:05 PM PST 24
Peak memory 201168 kb
Host smart-c6c99e32-cdd1-459c-beaa-8fffbe9ea857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146798347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3146798347
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2796938065
Short name T124
Test name
Test status
Simulation time 5961203802 ps
CPU time 14.79 seconds
Started Mar 07 12:34:06 PM PST 24
Finished Mar 07 12:34:21 PM PST 24
Peak memory 201184 kb
Host smart-9895dfbe-67ae-4960-be66-9b23fbc57be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796938065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2796938065
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3090765457
Short name T665
Test name
Test status
Simulation time 504244839 ps
CPU time 1.79 seconds
Started Mar 07 12:34:24 PM PST 24
Finished Mar 07 12:34:26 PM PST 24
Peak memory 201124 kb
Host smart-137ea60a-c734-4a39-a03e-2cc34bc71051
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090765457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3090765457
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3173805294
Short name T245
Test name
Test status
Simulation time 513909049240 ps
CPU time 713.25 seconds
Started Mar 07 12:34:13 PM PST 24
Finished Mar 07 12:46:07 PM PST 24
Peak memory 201420 kb
Host smart-70d8c23b-8737-4bf2-9657-e52916f3880c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173805294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3173805294
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.2199125486
Short name T236
Test name
Test status
Simulation time 489991296871 ps
CPU time 1135.26 seconds
Started Mar 07 12:34:11 PM PST 24
Finished Mar 07 12:53:06 PM PST 24
Peak memory 201336 kb
Host smart-5f55fd42-5cfc-43ae-82bd-8ee58853af67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199125486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.2199125486
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.76575755
Short name T377
Test name
Test status
Simulation time 160793904611 ps
CPU time 198.13 seconds
Started Mar 07 12:34:08 PM PST 24
Finished Mar 07 12:37:26 PM PST 24
Peak memory 201320 kb
Host smart-5ae0d390-af39-4723-86a4-c6dc886efe65
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=76575755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt
_fixed.76575755
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3152215760
Short name T84
Test name
Test status
Simulation time 483453045262 ps
CPU time 355.55 seconds
Started Mar 07 12:34:04 PM PST 24
Finished Mar 07 12:40:00 PM PST 24
Peak memory 201296 kb
Host smart-4692f470-eefc-4816-bf63-abc5ce940d56
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152215760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3152215760
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.961614865
Short name T179
Test name
Test status
Simulation time 362518945251 ps
CPU time 260.14 seconds
Started Mar 07 12:34:25 PM PST 24
Finished Mar 07 12:38:46 PM PST 24
Peak memory 201416 kb
Host smart-f275d1aa-8406-40b9-815d-b42ed77f8d95
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961614865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_
wakeup.961614865
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.860013856
Short name T92
Test name
Test status
Simulation time 213844441411 ps
CPU time 502.52 seconds
Started Mar 07 12:34:21 PM PST 24
Finished Mar 07 12:42:44 PM PST 24
Peak memory 201156 kb
Host smart-2ef27480-0306-49c4-b5f8-9ef4c0918f54
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860013856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
adc_ctrl_filters_wakeup_fixed.860013856
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.216409559
Short name T190
Test name
Test status
Simulation time 81603085203 ps
CPU time 257.7 seconds
Started Mar 07 12:34:13 PM PST 24
Finished Mar 07 12:38:31 PM PST 24
Peak memory 201744 kb
Host smart-864edbfa-0518-4727-af18-eb9b71f825df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216409559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.216409559
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1836483037
Short name T668
Test name
Test status
Simulation time 30115198301 ps
CPU time 14.96 seconds
Started Mar 07 12:34:17 PM PST 24
Finished Mar 07 12:34:36 PM PST 24
Peak memory 201172 kb
Host smart-cb065ad6-f90f-41b2-a9fa-2423a25c6fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836483037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1836483037
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.1293250657
Short name T782
Test name
Test status
Simulation time 3543346506 ps
CPU time 4.55 seconds
Started Mar 07 12:34:24 PM PST 24
Finished Mar 07 12:34:29 PM PST 24
Peak memory 201160 kb
Host smart-72174a76-7d10-4ed9-ab00-6ce922d694f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293250657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1293250657
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1106509816
Short name T627
Test name
Test status
Simulation time 5922764512 ps
CPU time 15.9 seconds
Started Mar 07 12:34:14 PM PST 24
Finished Mar 07 12:34:30 PM PST 24
Peak memory 201144 kb
Host smart-94593474-5596-47ef-a9c7-9e3d6e95335f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106509816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1106509816
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.4008467583
Short name T142
Test name
Test status
Simulation time 176536407947 ps
CPU time 27.37 seconds
Started Mar 07 12:34:29 PM PST 24
Finished Mar 07 12:34:56 PM PST 24
Peak memory 201312 kb
Host smart-74172218-9ec6-48b1-957a-8a60fbd59732
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008467583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.4008467583
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3099022458
Short name T37
Test name
Test status
Simulation time 99667494721 ps
CPU time 54.94 seconds
Started Mar 07 12:34:14 PM PST 24
Finished Mar 07 12:35:09 PM PST 24
Peak memory 209720 kb
Host smart-996feba7-0b90-4595-ad98-d5495ba59d0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099022458 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3099022458
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1278802960
Short name T557
Test name
Test status
Simulation time 420442999 ps
CPU time 0.88 seconds
Started Mar 07 12:33:15 PM PST 24
Finished Mar 07 12:33:16 PM PST 24
Peak memory 201116 kb
Host smart-9611a978-80f2-4ab5-979c-4224052bd028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278802960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1278802960
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.99065501
Short name T153
Test name
Test status
Simulation time 496392970361 ps
CPU time 297.6 seconds
Started Mar 07 12:33:16 PM PST 24
Finished Mar 07 12:38:14 PM PST 24
Peak memory 201320 kb
Host smart-31cbe2c6-4443-4afd-8c58-12753cad9dfd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99065501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gating
.99065501
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.542478527
Short name T680
Test name
Test status
Simulation time 486439308966 ps
CPU time 1143.88 seconds
Started Mar 07 12:33:19 PM PST 24
Finished Mar 07 12:52:23 PM PST 24
Peak memory 201352 kb
Host smart-1e52f78b-27a7-4898-87cb-e6a608124a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542478527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.542478527
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.1661646741
Short name T752
Test name
Test status
Simulation time 165935977140 ps
CPU time 110.07 seconds
Started Mar 07 12:33:20 PM PST 24
Finished Mar 07 12:35:10 PM PST 24
Peak memory 201372 kb
Host smart-b48138d1-ffa3-487d-aec5-60af8ae6f6ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661646741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.1661646741
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1709425276
Short name T631
Test name
Test status
Simulation time 322411906065 ps
CPU time 770.5 seconds
Started Mar 07 12:33:20 PM PST 24
Finished Mar 07 12:46:11 PM PST 24
Peak memory 201284 kb
Host smart-7879b0b4-b995-4ee9-ad38-928a99cc2939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709425276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1709425276
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1425398593
Short name T370
Test name
Test status
Simulation time 163786667237 ps
CPU time 412.19 seconds
Started Mar 07 12:33:23 PM PST 24
Finished Mar 07 12:40:16 PM PST 24
Peak memory 201288 kb
Host smart-2eeea192-37c8-4cfb-9563-860981f15826
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425398593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1425398593
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2230152421
Short name T136
Test name
Test status
Simulation time 178853629627 ps
CPU time 103.85 seconds
Started Mar 07 12:33:33 PM PST 24
Finished Mar 07 12:35:17 PM PST 24
Peak memory 201328 kb
Host smart-b2182c8a-959b-405e-ba5f-61e9b35cf8c6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230152421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2230152421
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3630191872
Short name T490
Test name
Test status
Simulation time 202026823554 ps
CPU time 26.69 seconds
Started Mar 07 12:33:19 PM PST 24
Finished Mar 07 12:33:46 PM PST 24
Peak memory 201304 kb
Host smart-22be8e72-40b7-4255-8cc1-60654e07b9b1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630191872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3630191872
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1989061240
Short name T41
Test name
Test status
Simulation time 83611673455 ps
CPU time 279.94 seconds
Started Mar 07 12:33:28 PM PST 24
Finished Mar 07 12:38:10 PM PST 24
Peak memory 201716 kb
Host smart-f1966bb8-542a-4e73-bb86-bff924e985cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989061240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1989061240
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2803956117
Short name T374
Test name
Test status
Simulation time 31201624136 ps
CPU time 73.87 seconds
Started Mar 07 12:33:14 PM PST 24
Finished Mar 07 12:34:28 PM PST 24
Peak memory 201096 kb
Host smart-445310ea-62c0-46b0-ad25-2073ddbd8b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803956117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2803956117
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.695844210
Short name T367
Test name
Test status
Simulation time 4416086646 ps
CPU time 5.6 seconds
Started Mar 07 12:33:16 PM PST 24
Finished Mar 07 12:33:22 PM PST 24
Peak memory 201132 kb
Host smart-1fa3d9c1-3770-45e6-b1c9-8549c3187b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695844210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.695844210
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1521815024
Short name T57
Test name
Test status
Simulation time 8125455390 ps
CPU time 5.08 seconds
Started Mar 07 12:33:16 PM PST 24
Finished Mar 07 12:33:21 PM PST 24
Peak memory 217632 kb
Host smart-9ff4626c-cd50-40d6-a41a-07c30586fd94
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521815024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1521815024
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1800757452
Short name T685
Test name
Test status
Simulation time 5703431787 ps
CPU time 4.78 seconds
Started Mar 07 12:33:23 PM PST 24
Finished Mar 07 12:33:28 PM PST 24
Peak memory 201160 kb
Host smart-4d52c206-c77e-4699-b9d0-2eb8f02978a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800757452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1800757452
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.1976590799
Short name T302
Test name
Test status
Simulation time 658951868948 ps
CPU time 331.13 seconds
Started Mar 07 12:33:19 PM PST 24
Finished Mar 07 12:38:50 PM PST 24
Peak memory 201312 kb
Host smart-b7559f98-0d8e-4018-ba75-8bdc0c497a5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976590799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
1976590799
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3312260172
Short name T779
Test name
Test status
Simulation time 538846050781 ps
CPU time 510.6 seconds
Started Mar 07 12:33:15 PM PST 24
Finished Mar 07 12:41:46 PM PST 24
Peak memory 210160 kb
Host smart-f94f890e-8e32-4f22-8301-5e7938ddb36d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312260172 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.3312260172
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.4270843121
Short name T372
Test name
Test status
Simulation time 302233178 ps
CPU time 1.33 seconds
Started Mar 07 12:34:14 PM PST 24
Finished Mar 07 12:34:16 PM PST 24
Peak memory 201128 kb
Host smart-75853480-8e94-4933-b800-aee0ac6f6ace
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270843121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.4270843121
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.212476537
Short name T776
Test name
Test status
Simulation time 329663271119 ps
CPU time 209.02 seconds
Started Mar 07 12:34:19 PM PST 24
Finished Mar 07 12:37:50 PM PST 24
Peak memory 201348 kb
Host smart-8fa42214-579f-43e8-b050-24e254fc8e64
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=212476537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrup
t_fixed.212476537
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2855778025
Short name T202
Test name
Test status
Simulation time 492572825987 ps
CPU time 556.66 seconds
Started Mar 07 12:34:21 PM PST 24
Finished Mar 07 12:43:38 PM PST 24
Peak memory 201256 kb
Host smart-1c7fb6b3-fe91-4c2e-9fbd-15826a0a747b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855778025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2855778025
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1691265905
Short name T453
Test name
Test status
Simulation time 485528447460 ps
CPU time 427.27 seconds
Started Mar 07 12:34:18 PM PST 24
Finished Mar 07 12:41:28 PM PST 24
Peak memory 201264 kb
Host smart-cf8d67e3-1321-410e-b59a-971495ab9b81
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691265905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1691265905
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3730997145
Short name T40
Test name
Test status
Simulation time 537680674118 ps
CPU time 381.94 seconds
Started Mar 07 12:34:27 PM PST 24
Finished Mar 07 12:40:50 PM PST 24
Peak memory 201304 kb
Host smart-679ffe6e-2b1f-43d2-b5fc-2f71d3520ea2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730997145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3730997145
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3417313649
Short name T473
Test name
Test status
Simulation time 409276608109 ps
CPU time 899.24 seconds
Started Mar 07 12:34:07 PM PST 24
Finished Mar 07 12:49:07 PM PST 24
Peak memory 201360 kb
Host smart-b118b2ab-858e-4a5a-bf82-9eeef3bc57c5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417313649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3417313649
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1104965991
Short name T331
Test name
Test status
Simulation time 123522379548 ps
CPU time 634.65 seconds
Started Mar 07 12:34:20 PM PST 24
Finished Mar 07 12:44:56 PM PST 24
Peak memory 201648 kb
Host smart-86bad3dc-53bb-402c-97cd-8c4cd2a77170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104965991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1104965991
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2017745433
Short name T398
Test name
Test status
Simulation time 30370830992 ps
CPU time 16.83 seconds
Started Mar 07 12:34:06 PM PST 24
Finished Mar 07 12:34:23 PM PST 24
Peak memory 201088 kb
Host smart-ca429148-e2cc-4698-88db-952b2f08fb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017745433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2017745433
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.106497231
Short name T433
Test name
Test status
Simulation time 2961190173 ps
CPU time 2.48 seconds
Started Mar 07 12:34:10 PM PST 24
Finished Mar 07 12:34:13 PM PST 24
Peak memory 201164 kb
Host smart-745f8538-c591-498d-8555-20d7a872da62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106497231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.106497231
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2273985311
Short name T386
Test name
Test status
Simulation time 6260072286 ps
CPU time 4.45 seconds
Started Mar 07 12:34:23 PM PST 24
Finished Mar 07 12:34:28 PM PST 24
Peak memory 201168 kb
Host smart-aa3b98aa-0a74-4984-8c32-aa5bbd079131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273985311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2273985311
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3052983444
Short name T310
Test name
Test status
Simulation time 369240761070 ps
CPU time 184.72 seconds
Started Mar 07 12:34:23 PM PST 24
Finished Mar 07 12:37:28 PM PST 24
Peak memory 201312 kb
Host smart-03df0533-c0bf-4321-9dd8-5558c96d9c9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052983444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3052983444
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.4082571503
Short name T19
Test name
Test status
Simulation time 38556808018 ps
CPU time 26.49 seconds
Started Mar 07 12:34:11 PM PST 24
Finished Mar 07 12:34:38 PM PST 24
Peak memory 201520 kb
Host smart-acbc4c94-0695-4ccc-b381-dcf60268d2de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082571503 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.4082571503
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3673805066
Short name T464
Test name
Test status
Simulation time 315255976 ps
CPU time 0.88 seconds
Started Mar 07 12:34:28 PM PST 24
Finished Mar 07 12:34:29 PM PST 24
Peak memory 201128 kb
Host smart-5dd8482a-58c2-4d76-a1e7-fd4693638303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673805066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3673805066
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.3643845792
Short name T170
Test name
Test status
Simulation time 500369805046 ps
CPU time 309.02 seconds
Started Mar 07 12:34:21 PM PST 24
Finished Mar 07 12:39:30 PM PST 24
Peak memory 200524 kb
Host smart-b1d89209-8d96-4d75-a2e4-8ed018945d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643845792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.3643845792
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.923088341
Short name T586
Test name
Test status
Simulation time 169664874105 ps
CPU time 203.31 seconds
Started Mar 07 12:34:24 PM PST 24
Finished Mar 07 12:37:47 PM PST 24
Peak memory 201328 kb
Host smart-7d3313a8-6025-4514-9455-0df581997dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923088341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.923088341
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.754230330
Short name T743
Test name
Test status
Simulation time 161421044240 ps
CPU time 400.77 seconds
Started Mar 07 12:34:21 PM PST 24
Finished Mar 07 12:41:02 PM PST 24
Peak memory 201232 kb
Host smart-a6f1ff48-b195-4988-a708-02b04045862b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=754230330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.754230330
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3056447139
Short name T733
Test name
Test status
Simulation time 163627411161 ps
CPU time 348.97 seconds
Started Mar 07 12:34:17 PM PST 24
Finished Mar 07 12:40:10 PM PST 24
Peak memory 201360 kb
Host smart-18ae9612-9398-40f1-a004-53f466ce9074
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056447139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3056447139
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3743254731
Short name T228
Test name
Test status
Simulation time 530166174625 ps
CPU time 1348.95 seconds
Started Mar 07 12:34:10 PM PST 24
Finished Mar 07 12:56:40 PM PST 24
Peak memory 201292 kb
Host smart-a33d9775-51d9-402f-a100-d511ab5c5680
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743254731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3743254731
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.937343904
Short name T501
Test name
Test status
Simulation time 409408078266 ps
CPU time 176.85 seconds
Started Mar 07 12:34:24 PM PST 24
Finished Mar 07 12:37:21 PM PST 24
Peak memory 201328 kb
Host smart-eeba7961-9d6e-442e-aceb-dbcc2b886c21
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937343904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
adc_ctrl_filters_wakeup_fixed.937343904
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.1797997630
Short name T44
Test name
Test status
Simulation time 95268531392 ps
CPU time 341.21 seconds
Started Mar 07 12:34:20 PM PST 24
Finished Mar 07 12:40:02 PM PST 24
Peak memory 201640 kb
Host smart-a6679961-86de-40ef-a848-8e29cb073aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797997630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1797997630
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2096526631
Short name T172
Test name
Test status
Simulation time 35281102649 ps
CPU time 20.16 seconds
Started Mar 07 12:34:09 PM PST 24
Finished Mar 07 12:34:29 PM PST 24
Peak memory 201176 kb
Host smart-702dead3-95ad-4b42-b0e0-37ffa767eb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096526631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2096526631
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.2028083543
Short name T640
Test name
Test status
Simulation time 4436648078 ps
CPU time 2.22 seconds
Started Mar 07 12:34:13 PM PST 24
Finished Mar 07 12:34:16 PM PST 24
Peak memory 201188 kb
Host smart-fab5f6ae-5a1d-4ccb-a5b8-cac1d2c70d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028083543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2028083543
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.671955846
Short name T345
Test name
Test status
Simulation time 5736677418 ps
CPU time 8.13 seconds
Started Mar 07 12:34:17 PM PST 24
Finished Mar 07 12:34:29 PM PST 24
Peak memory 201148 kb
Host smart-3fc59020-1d11-4f19-a3b6-321b86bb9683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671955846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.671955846
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.702794118
Short name T756
Test name
Test status
Simulation time 184776932066 ps
CPU time 207.71 seconds
Started Mar 07 12:34:15 PM PST 24
Finished Mar 07 12:37:46 PM PST 24
Peak memory 209720 kb
Host smart-4421292e-8e41-46e4-bc2f-bbffc728fc03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702794118 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.702794118
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2844593676
Short name T529
Test name
Test status
Simulation time 308269481 ps
CPU time 1.29 seconds
Started Mar 07 12:34:30 PM PST 24
Finished Mar 07 12:34:31 PM PST 24
Peak memory 201060 kb
Host smart-6fa4201f-987b-47dd-af2a-e684efc8dd98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844593676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2844593676
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.952709728
Short name T718
Test name
Test status
Simulation time 203430696751 ps
CPU time 500.91 seconds
Started Mar 07 12:34:15 PM PST 24
Finished Mar 07 12:42:39 PM PST 24
Peak memory 201348 kb
Host smart-6ae60ffd-ad7c-47d6-ac38-e2c30b622a03
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952709728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.952709728
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.875633205
Short name T634
Test name
Test status
Simulation time 353674604526 ps
CPU time 442.37 seconds
Started Mar 07 12:34:15 PM PST 24
Finished Mar 07 12:41:38 PM PST 24
Peak memory 201300 kb
Host smart-2648a0e7-72bc-45e8-9d80-2944b1b7852c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875633205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.875633205
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2340095908
Short name T672
Test name
Test status
Simulation time 162555638685 ps
CPU time 205.72 seconds
Started Mar 07 12:34:39 PM PST 24
Finished Mar 07 12:38:07 PM PST 24
Peak memory 201312 kb
Host smart-8a3da874-f37e-4ba8-a98a-e5df677efa90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340095908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2340095908
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3741187720
Short name T447
Test name
Test status
Simulation time 326302430439 ps
CPU time 215.14 seconds
Started Mar 07 12:34:30 PM PST 24
Finished Mar 07 12:38:05 PM PST 24
Peak memory 201328 kb
Host smart-c40217a0-d409-42fd-a9c4-10f1b7b12228
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741187720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3741187720
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.385875615
Short name T203
Test name
Test status
Simulation time 490975059553 ps
CPU time 295.71 seconds
Started Mar 07 12:34:15 PM PST 24
Finished Mar 07 12:39:14 PM PST 24
Peak memory 201188 kb
Host smart-f46c3fa3-26cd-405d-a028-9b2f562dc7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385875615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.385875615
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1773870058
Short name T486
Test name
Test status
Simulation time 496916121694 ps
CPU time 194.41 seconds
Started Mar 07 12:34:15 PM PST 24
Finished Mar 07 12:37:30 PM PST 24
Peak memory 201300 kb
Host smart-78589218-a14f-4931-b0ac-5f4845082c70
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773870058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1773870058
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.449230654
Short name T630
Test name
Test status
Simulation time 386990067490 ps
CPU time 253.66 seconds
Started Mar 07 12:34:13 PM PST 24
Finished Mar 07 12:38:27 PM PST 24
Peak memory 201292 kb
Host smart-e3351a7f-9c26-455b-9147-04fabec4d7bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449230654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.449230654
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2059102090
Short name T402
Test name
Test status
Simulation time 201305987824 ps
CPU time 161.66 seconds
Started Mar 07 12:35:42 PM PST 24
Finished Mar 07 12:38:25 PM PST 24
Peak memory 200896 kb
Host smart-8921ae28-82b6-41f0-873e-7757dca6ef19
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059102090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2059102090
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.3609204140
Short name T334
Test name
Test status
Simulation time 101648136910 ps
CPU time 534.1 seconds
Started Mar 07 12:34:16 PM PST 24
Finished Mar 07 12:43:12 PM PST 24
Peak memory 201628 kb
Host smart-8329819b-38d8-4a46-8f9a-26390b56a32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609204140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3609204140
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.948155340
Short name T95
Test name
Test status
Simulation time 41041148801 ps
CPU time 50.1 seconds
Started Mar 07 12:34:17 PM PST 24
Finished Mar 07 12:35:11 PM PST 24
Peak memory 201236 kb
Host smart-6e74f371-8732-429c-9805-057518e0d406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948155340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.948155340
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.3716271017
Short name T750
Test name
Test status
Simulation time 2971027832 ps
CPU time 3.57 seconds
Started Mar 07 12:34:33 PM PST 24
Finished Mar 07 12:34:37 PM PST 24
Peak memory 201088 kb
Host smart-92a13091-289a-4995-b932-c221f1de54d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716271017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3716271017
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.161102415
Short name T503
Test name
Test status
Simulation time 5783788020 ps
CPU time 13.56 seconds
Started Mar 07 12:34:16 PM PST 24
Finished Mar 07 12:34:34 PM PST 24
Peak memory 201164 kb
Host smart-a709844b-6276-4810-b449-fc307eb36b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161102415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.161102415
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1599971404
Short name T568
Test name
Test status
Simulation time 190893087566 ps
CPU time 278.57 seconds
Started Mar 07 12:34:18 PM PST 24
Finished Mar 07 12:38:59 PM PST 24
Peak memory 201460 kb
Host smart-1f9389b0-cefa-4e4f-b73d-47e244adcb21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599971404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1599971404
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1899183100
Short name T705
Test name
Test status
Simulation time 209451701868 ps
CPU time 74.48 seconds
Started Mar 07 12:35:27 PM PST 24
Finished Mar 07 12:36:43 PM PST 24
Peak memory 208952 kb
Host smart-f1c6331f-b6b2-4ba2-b1fe-64b447ddd454
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899183100 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1899183100
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.4196707524
Short name T391
Test name
Test status
Simulation time 454488845 ps
CPU time 0.7 seconds
Started Mar 07 12:34:31 PM PST 24
Finished Mar 07 12:34:33 PM PST 24
Peak memory 201124 kb
Host smart-0f4f35b5-bd5c-4c85-a1d5-fe4015222cda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196707524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.4196707524
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3175605544
Short name T214
Test name
Test status
Simulation time 162274358764 ps
CPU time 333.53 seconds
Started Mar 07 12:35:42 PM PST 24
Finished Mar 07 12:41:17 PM PST 24
Peak memory 200920 kb
Host smart-9bcd9442-26d5-4b2a-957b-441165725ff6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175605544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3175605544
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.3009352465
Short name T201
Test name
Test status
Simulation time 163174869164 ps
CPU time 377.07 seconds
Started Mar 07 12:34:33 PM PST 24
Finished Mar 07 12:40:51 PM PST 24
Peak memory 201252 kb
Host smart-acbf92c8-a368-4a34-a715-a5a2778c2677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009352465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3009352465
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3305299506
Short name T514
Test name
Test status
Simulation time 164374356156 ps
CPU time 64.92 seconds
Started Mar 07 12:34:36 PM PST 24
Finished Mar 07 12:35:42 PM PST 24
Peak memory 201396 kb
Host smart-3fead576-25f7-4d42-846d-c9b6b38736b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305299506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3305299506
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1980977887
Short name T303
Test name
Test status
Simulation time 325914546173 ps
CPU time 366.71 seconds
Started Mar 07 12:34:29 PM PST 24
Finished Mar 07 12:40:36 PM PST 24
Peak memory 201312 kb
Host smart-8e8feaa4-0217-42c5-a5ea-154e44fe3969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980977887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1980977887
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2238148239
Short name T635
Test name
Test status
Simulation time 497865770032 ps
CPU time 1253.19 seconds
Started Mar 07 12:35:42 PM PST 24
Finished Mar 07 12:56:37 PM PST 24
Peak memory 200820 kb
Host smart-5f2fd559-19cd-4bec-982a-e6a13ea497e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238148239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2238148239
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3714174144
Short name T261
Test name
Test status
Simulation time 341369704170 ps
CPU time 811.03 seconds
Started Mar 07 12:34:30 PM PST 24
Finished Mar 07 12:48:01 PM PST 24
Peak memory 201384 kb
Host smart-52ac17ca-f89c-4775-9df1-369f3d5a3df4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714174144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3714174144
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.4151869537
Short name T552
Test name
Test status
Simulation time 592168263115 ps
CPU time 372.66 seconds
Started Mar 07 12:34:33 PM PST 24
Finished Mar 07 12:40:45 PM PST 24
Peak memory 201380 kb
Host smart-4df5d597-0bd0-43a4-8980-48c43f3805a2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151869537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.4151869537
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3006170245
Short name T337
Test name
Test status
Simulation time 127854273854 ps
CPU time 633.96 seconds
Started Mar 07 12:34:29 PM PST 24
Finished Mar 07 12:45:03 PM PST 24
Peak memory 201752 kb
Host smart-d235da85-f8cd-437b-82e0-6c3285f4f166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006170245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3006170245
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.636651644
Short name T708
Test name
Test status
Simulation time 25625489688 ps
CPU time 16.92 seconds
Started Mar 07 12:34:28 PM PST 24
Finished Mar 07 12:34:45 PM PST 24
Peak memory 201236 kb
Host smart-6626cad0-2420-4603-9ee7-34238c482121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636651644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.636651644
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3275988706
Short name T366
Test name
Test status
Simulation time 3498036210 ps
CPU time 1.2 seconds
Started Mar 07 12:34:36 PM PST 24
Finished Mar 07 12:34:37 PM PST 24
Peak memory 201240 kb
Host smart-bf240220-2b59-4218-a12c-e134267f83ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275988706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3275988706
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.4164738268
Short name T505
Test name
Test status
Simulation time 5995681789 ps
CPU time 7.85 seconds
Started Mar 07 12:34:23 PM PST 24
Finished Mar 07 12:34:31 PM PST 24
Peak memory 201184 kb
Host smart-b1a7b931-c5a2-402a-b44e-9c081cd5da8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164738268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.4164738268
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.82147488
Short name T646
Test name
Test status
Simulation time 17235992968 ps
CPU time 39.38 seconds
Started Mar 07 12:34:28 PM PST 24
Finished Mar 07 12:35:08 PM PST 24
Peak memory 201560 kb
Host smart-8956e86c-e426-408c-9986-76f4f54e033a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82147488 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.82147488
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.616818898
Short name T426
Test name
Test status
Simulation time 470369798 ps
CPU time 1.76 seconds
Started Mar 07 12:34:42 PM PST 24
Finished Mar 07 12:34:44 PM PST 24
Peak memory 201120 kb
Host smart-0813496b-d15e-4036-935e-9b01b2367f9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616818898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.616818898
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.3631167554
Short name T232
Test name
Test status
Simulation time 498054163436 ps
CPU time 414.34 seconds
Started Mar 07 12:35:42 PM PST 24
Finished Mar 07 12:42:38 PM PST 24
Peak memory 200824 kb
Host smart-ceea5af1-71b9-464c-ab07-38fdba46ca9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631167554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3631167554
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1402285664
Short name T75
Test name
Test status
Simulation time 490656334453 ps
CPU time 1056.6 seconds
Started Mar 07 12:34:36 PM PST 24
Finished Mar 07 12:52:13 PM PST 24
Peak memory 201420 kb
Host smart-7dc6d101-85e4-4fd9-89ad-c29fdb63f9c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402285664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1402285664
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1107789341
Short name T128
Test name
Test status
Simulation time 493275142332 ps
CPU time 1107.8 seconds
Started Mar 07 12:34:31 PM PST 24
Finished Mar 07 12:52:59 PM PST 24
Peak memory 201396 kb
Host smart-fb2bc00b-0cfe-4de4-9cbd-09ec17b3f612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107789341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1107789341
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3006407868
Short name T354
Test name
Test status
Simulation time 162825187218 ps
CPU time 205.12 seconds
Started Mar 07 12:34:38 PM PST 24
Finished Mar 07 12:38:06 PM PST 24
Peak memory 201264 kb
Host smart-48a57c41-514c-4c65-881e-07e6d127ca5d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006407868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3006407868
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2466978334
Short name T288
Test name
Test status
Simulation time 562544551511 ps
CPU time 315.97 seconds
Started Mar 07 12:34:33 PM PST 24
Finished Mar 07 12:39:49 PM PST 24
Peak memory 201408 kb
Host smart-fb31449b-ba99-4a84-a500-85929d7fa3f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466978334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2466978334
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.4054014658
Short name T504
Test name
Test status
Simulation time 623626957058 ps
CPU time 363.91 seconds
Started Mar 07 12:34:30 PM PST 24
Finished Mar 07 12:40:34 PM PST 24
Peak memory 201300 kb
Host smart-0346c047-7c81-460e-86ed-d9bb3ed1ba32
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054014658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.4054014658
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.4036085119
Short name T541
Test name
Test status
Simulation time 101757733905 ps
CPU time 554.71 seconds
Started Mar 07 12:34:37 PM PST 24
Finished Mar 07 12:43:53 PM PST 24
Peak memory 201800 kb
Host smart-2e0f3da5-2160-4c03-ad57-63a3df5acc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036085119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.4036085119
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.278771847
Short name T699
Test name
Test status
Simulation time 39079202235 ps
CPU time 13.95 seconds
Started Mar 07 12:34:38 PM PST 24
Finished Mar 07 12:34:54 PM PST 24
Peak memory 201200 kb
Host smart-0b836499-a0b5-482f-b1a1-4f5371bffddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278771847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.278771847
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.4103950376
Short name T722
Test name
Test status
Simulation time 3654249134 ps
CPU time 4.48 seconds
Started Mar 07 12:34:40 PM PST 24
Finished Mar 07 12:34:46 PM PST 24
Peak memory 201200 kb
Host smart-dbc5db1f-50fc-4582-a9d2-ace756097fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103950376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.4103950376
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.2508065370
Short name T554
Test name
Test status
Simulation time 5771044122 ps
CPU time 14.5 seconds
Started Mar 07 12:34:27 PM PST 24
Finished Mar 07 12:34:42 PM PST 24
Peak memory 201188 kb
Host smart-faaf65df-bd38-4fea-b439-ac5b85a90bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508065370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.2508065370
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.273224538
Short name T291
Test name
Test status
Simulation time 591190043702 ps
CPU time 778.68 seconds
Started Mar 07 12:34:38 PM PST 24
Finished Mar 07 12:47:39 PM PST 24
Peak memory 201764 kb
Host smart-d6e75152-8120-4198-ac5c-184803cf0314
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273224538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.
273224538
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1026512579
Short name T320
Test name
Test status
Simulation time 291341170123 ps
CPU time 281.03 seconds
Started Mar 07 12:34:40 PM PST 24
Finished Mar 07 12:39:22 PM PST 24
Peak memory 210148 kb
Host smart-feb153d1-b76e-4124-89a1-41fcbf12cdb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026512579 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1026512579
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1638976517
Short name T64
Test name
Test status
Simulation time 414325992 ps
CPU time 1.6 seconds
Started Mar 07 12:34:40 PM PST 24
Finished Mar 07 12:34:43 PM PST 24
Peak memory 201100 kb
Host smart-f4820011-3b57-4190-8f86-5216972da133
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638976517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1638976517
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3811740722
Short name T681
Test name
Test status
Simulation time 509926843007 ps
CPU time 823.03 seconds
Started Mar 07 12:34:40 PM PST 24
Finished Mar 07 12:48:25 PM PST 24
Peak memory 201328 kb
Host smart-e8b07df3-0dac-481a-b8e8-8376ef037df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811740722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3811740722
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.178345482
Short name T98
Test name
Test status
Simulation time 165464801655 ps
CPU time 193.84 seconds
Started Mar 07 12:34:38 PM PST 24
Finished Mar 07 12:37:52 PM PST 24
Peak memory 201372 kb
Host smart-868b3bd3-0680-4690-b818-9dbccbf56bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178345482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.178345482
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3223762843
Short name T210
Test name
Test status
Simulation time 166939758324 ps
CPU time 416.79 seconds
Started Mar 07 12:34:42 PM PST 24
Finished Mar 07 12:41:39 PM PST 24
Peak memory 201308 kb
Host smart-b0613b20-b398-45c5-a2c5-c5436496bae7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223762843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.3223762843
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2899601160
Short name T540
Test name
Test status
Simulation time 330497195868 ps
CPU time 751.71 seconds
Started Mar 07 12:34:41 PM PST 24
Finished Mar 07 12:47:13 PM PST 24
Peak memory 201324 kb
Host smart-a4612b33-23bc-49f9-9432-510335b510c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899601160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2899601160
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1504155069
Short name T530
Test name
Test status
Simulation time 163730129326 ps
CPU time 95.74 seconds
Started Mar 07 12:34:39 PM PST 24
Finished Mar 07 12:36:17 PM PST 24
Peak memory 201332 kb
Host smart-64cd087f-3bb4-49ef-b592-1ed4f610265d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504155069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1504155069
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3209012233
Short name T645
Test name
Test status
Simulation time 181762286060 ps
CPU time 166.71 seconds
Started Mar 07 12:34:39 PM PST 24
Finished Mar 07 12:37:28 PM PST 24
Peak memory 201336 kb
Host smart-d7eeab2f-b797-4b52-a5b0-f604be3fb556
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209012233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3209012233
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3146229230
Short name T609
Test name
Test status
Simulation time 403000192734 ps
CPU time 1017.39 seconds
Started Mar 07 12:34:38 PM PST 24
Finished Mar 07 12:51:38 PM PST 24
Peak memory 201304 kb
Host smart-0bf1beaa-6621-404c-b5a2-f0366aa92109
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146229230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3146229230
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1836245301
Short name T198
Test name
Test status
Simulation time 114271680499 ps
CPU time 498.95 seconds
Started Mar 07 12:34:38 PM PST 24
Finished Mar 07 12:42:59 PM PST 24
Peak memory 201608 kb
Host smart-02ebee5c-d571-42fd-878d-47fbeca32268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836245301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1836245301
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3162115395
Short name T360
Test name
Test status
Simulation time 23641366176 ps
CPU time 25.7 seconds
Started Mar 07 12:34:37 PM PST 24
Finished Mar 07 12:35:03 PM PST 24
Peak memory 201164 kb
Host smart-de4d4919-ed37-46a5-99fe-4d91fbd1f514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162115395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3162115395
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2223194571
Short name T456
Test name
Test status
Simulation time 3075291688 ps
CPU time 2.58 seconds
Started Mar 07 12:34:38 PM PST 24
Finished Mar 07 12:34:43 PM PST 24
Peak memory 201184 kb
Host smart-27762b34-ddaa-49bd-be13-805648481961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223194571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2223194571
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3436313205
Short name T448
Test name
Test status
Simulation time 5705455145 ps
CPU time 14.48 seconds
Started Mar 07 12:34:36 PM PST 24
Finished Mar 07 12:34:52 PM PST 24
Peak memory 201140 kb
Host smart-eb20185a-f6d2-47d9-ba6b-35aea9b3bcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436313205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3436313205
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2160488529
Short name T189
Test name
Test status
Simulation time 260610106191 ps
CPU time 732.75 seconds
Started Mar 07 12:34:39 PM PST 24
Finished Mar 07 12:46:54 PM PST 24
Peak memory 212028 kb
Host smart-2d593291-2140-4dbd-a455-5f859a45a5ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160488529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2160488529
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.203392243
Short name T274
Test name
Test status
Simulation time 376539906257 ps
CPU time 134.44 seconds
Started Mar 07 12:34:37 PM PST 24
Finished Mar 07 12:36:52 PM PST 24
Peak memory 201428 kb
Host smart-5d3fb13b-df88-48e9-9857-bc52f33c7fed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203392243 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.203392243
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1086076676
Short name T382
Test name
Test status
Simulation time 353978205 ps
CPU time 1.52 seconds
Started Mar 07 12:34:39 PM PST 24
Finished Mar 07 12:34:43 PM PST 24
Peak memory 201136 kb
Host smart-57dd103a-5448-4c28-aa79-835e1a8669ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086076676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1086076676
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2107288323
Short name T413
Test name
Test status
Simulation time 493441548292 ps
CPU time 436.36 seconds
Started Mar 07 12:34:42 PM PST 24
Finished Mar 07 12:41:59 PM PST 24
Peak memory 201376 kb
Host smart-95f06a96-13f3-43b1-974a-02e13f7bbc5f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107288323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2107288323
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2280027744
Short name T273
Test name
Test status
Simulation time 502873360203 ps
CPU time 1187.21 seconds
Started Mar 07 12:34:42 PM PST 24
Finished Mar 07 12:54:30 PM PST 24
Peak memory 201292 kb
Host smart-f9017d67-79ea-4534-8c71-c0522240e68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280027744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2280027744
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3854907517
Short name T150
Test name
Test status
Simulation time 492842338296 ps
CPU time 117.12 seconds
Started Mar 07 12:34:39 PM PST 24
Finished Mar 07 12:36:39 PM PST 24
Peak memory 201268 kb
Host smart-b1f5f451-ab1e-49b0-8589-a5baa94511a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854907517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.3854907517
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.456340450
Short name T502
Test name
Test status
Simulation time 163690483935 ps
CPU time 97.22 seconds
Started Mar 07 12:34:40 PM PST 24
Finished Mar 07 12:36:19 PM PST 24
Peak memory 201320 kb
Host smart-f58e9681-80f4-4d29-8006-3537d538c8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456340450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.456340450
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3767482691
Short name T553
Test name
Test status
Simulation time 488383212266 ps
CPU time 268.9 seconds
Started Mar 07 12:34:42 PM PST 24
Finished Mar 07 12:39:11 PM PST 24
Peak memory 201344 kb
Host smart-80567167-27a3-4eaa-91b9-c13e909277de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767482691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3767482691
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.627876969
Short name T555
Test name
Test status
Simulation time 196167908366 ps
CPU time 218.64 seconds
Started Mar 07 12:34:36 PM PST 24
Finished Mar 07 12:38:16 PM PST 24
Peak memory 201396 kb
Host smart-cd8dc451-be82-4406-a77e-dea5e6da44bf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627876969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
adc_ctrl_filters_wakeup_fixed.627876969
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3862046998
Short name T5
Test name
Test status
Simulation time 77204204775 ps
CPU time 407.35 seconds
Started Mar 07 12:34:42 PM PST 24
Finished Mar 07 12:41:30 PM PST 24
Peak memory 201772 kb
Host smart-e8375924-0d46-45c6-b7de-553498fda721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862046998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3862046998
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2918632575
Short name T518
Test name
Test status
Simulation time 28137330535 ps
CPU time 59.45 seconds
Started Mar 07 12:34:42 PM PST 24
Finished Mar 07 12:35:43 PM PST 24
Peak memory 201208 kb
Host smart-260ae166-7ee0-4a0e-b8b8-400e7815aee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918632575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2918632575
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1416096154
Short name T560
Test name
Test status
Simulation time 5222995954 ps
CPU time 5.04 seconds
Started Mar 07 12:34:37 PM PST 24
Finished Mar 07 12:34:43 PM PST 24
Peak memory 201160 kb
Host smart-ab35402b-8741-44fc-80a2-557d1ef95f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416096154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1416096154
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.161440053
Short name T591
Test name
Test status
Simulation time 5568023225 ps
CPU time 3.84 seconds
Started Mar 07 12:34:38 PM PST 24
Finished Mar 07 12:34:44 PM PST 24
Peak memory 201160 kb
Host smart-28c93b49-141b-4716-acbc-7653a301372f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161440053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.161440053
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2270562262
Short name T22
Test name
Test status
Simulation time 312609297400 ps
CPU time 340.17 seconds
Started Mar 07 12:34:42 PM PST 24
Finished Mar 07 12:40:22 PM PST 24
Peak memory 217616 kb
Host smart-0545c4f8-b1ba-4bea-9ac1-cf2de67e4451
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270562262 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2270562262
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.457963092
Short name T712
Test name
Test status
Simulation time 348451650 ps
CPU time 0.78 seconds
Started Mar 07 12:34:47 PM PST 24
Finished Mar 07 12:34:48 PM PST 24
Peak memory 201112 kb
Host smart-87369270-3668-450c-9942-4ff5865ad747
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457963092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.457963092
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3194384744
Short name T305
Test name
Test status
Simulation time 335343899848 ps
CPU time 719.67 seconds
Started Mar 07 12:34:46 PM PST 24
Finished Mar 07 12:46:46 PM PST 24
Peak memory 201240 kb
Host smart-637560fc-639e-4621-a04a-4b088d7904cc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194384744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3194384744
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1065110784
Short name T221
Test name
Test status
Simulation time 163931580316 ps
CPU time 50.03 seconds
Started Mar 07 12:34:37 PM PST 24
Finished Mar 07 12:35:28 PM PST 24
Peak memory 201336 kb
Host smart-fac0cc3d-b13a-458c-8a13-ad64c80886b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065110784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1065110784
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.143671261
Short name T522
Test name
Test status
Simulation time 487909204896 ps
CPU time 591.62 seconds
Started Mar 07 12:34:48 PM PST 24
Finished Mar 07 12:44:40 PM PST 24
Peak memory 201260 kb
Host smart-02be7fb2-a433-4969-8a30-e37ee0424f3b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=143671261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.143671261
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.4275249200
Short name T180
Test name
Test status
Simulation time 504335928403 ps
CPU time 310.85 seconds
Started Mar 07 12:34:44 PM PST 24
Finished Mar 07 12:39:57 PM PST 24
Peak memory 201328 kb
Host smart-63e10060-b65e-423e-a6e8-b84130e5e9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275249200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.4275249200
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3411323561
Short name T787
Test name
Test status
Simulation time 164423289340 ps
CPU time 177.74 seconds
Started Mar 07 12:34:38 PM PST 24
Finished Mar 07 12:37:36 PM PST 24
Peak memory 201380 kb
Host smart-ea3ac8c4-9e6c-46fb-b71f-9bb0c3733bd0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411323561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.3411323561
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3670182916
Short name T691
Test name
Test status
Simulation time 202995350438 ps
CPU time 123.38 seconds
Started Mar 07 12:34:47 PM PST 24
Finished Mar 07 12:36:51 PM PST 24
Peak memory 201372 kb
Host smart-ab60b0c7-b3de-43b7-b7b6-f226dd764316
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670182916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3670182916
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1418913898
Short name T742
Test name
Test status
Simulation time 422364135703 ps
CPU time 1008.06 seconds
Started Mar 07 12:36:53 PM PST 24
Finished Mar 07 12:53:42 PM PST 24
Peak memory 200996 kb
Host smart-af00f6c4-2323-4e0b-9c64-efdfb2212c1f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418913898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1418913898
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.381001281
Short name T700
Test name
Test status
Simulation time 136739720633 ps
CPU time 751.42 seconds
Started Mar 07 12:34:46 PM PST 24
Finished Mar 07 12:47:18 PM PST 24
Peak memory 201700 kb
Host smart-d46a1496-ee50-4f35-b9ae-7ab57f797e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381001281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.381001281
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3731594470
Short name T664
Test name
Test status
Simulation time 31147013217 ps
CPU time 66.56 seconds
Started Mar 07 12:34:47 PM PST 24
Finished Mar 07 12:35:54 PM PST 24
Peak memory 201180 kb
Host smart-b7dee68d-9434-41a0-8167-38a9acf8b534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731594470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3731594470
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2349467370
Short name T582
Test name
Test status
Simulation time 4870421246 ps
CPU time 5.74 seconds
Started Mar 07 12:36:53 PM PST 24
Finished Mar 07 12:37:00 PM PST 24
Peak memory 200812 kb
Host smart-9a8ebf59-d596-4b95-a120-4a466f4ea41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349467370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2349467370
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3359782188
Short name T471
Test name
Test status
Simulation time 5632717031 ps
CPU time 4.13 seconds
Started Mar 07 12:34:43 PM PST 24
Finished Mar 07 12:34:48 PM PST 24
Peak memory 201252 kb
Host smart-37d7a295-e438-41c4-81bf-a3fe38733b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359782188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3359782188
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.75734457
Short name T608
Test name
Test status
Simulation time 184218774298 ps
CPU time 398.62 seconds
Started Mar 07 12:34:48 PM PST 24
Finished Mar 07 12:41:27 PM PST 24
Peak memory 201352 kb
Host smart-8fb35f4c-d03e-42d3-bc76-55028598aa9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75734457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.75734457
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3321146944
Short name T765
Test name
Test status
Simulation time 61225834396 ps
CPU time 69.53 seconds
Started Mar 07 12:34:52 PM PST 24
Finished Mar 07 12:36:04 PM PST 24
Peak memory 209644 kb
Host smart-03391f5b-414c-4b6b-a99e-0c46592b4e45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321146944 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.3321146944
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2370292040
Short name T715
Test name
Test status
Simulation time 407201297 ps
CPU time 0.88 seconds
Started Mar 07 12:34:47 PM PST 24
Finished Mar 07 12:34:48 PM PST 24
Peak memory 201120 kb
Host smart-6b9bd6a7-1188-4703-8983-09ba80dc4e78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370292040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2370292040
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3225191556
Short name T488
Test name
Test status
Simulation time 539838842872 ps
CPU time 1287.65 seconds
Started Mar 07 12:34:45 PM PST 24
Finished Mar 07 12:56:13 PM PST 24
Peak memory 201308 kb
Host smart-ce56a0c6-b601-4477-9391-af683e33653d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225191556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3225191556
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.951790853
Short name T571
Test name
Test status
Simulation time 159309197936 ps
CPU time 132.27 seconds
Started Mar 07 12:35:56 PM PST 24
Finished Mar 07 12:38:08 PM PST 24
Peak memory 200896 kb
Host smart-b6d49516-869d-4a82-8fab-275fdc6fecf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951790853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.951790853
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2352736579
Short name T72
Test name
Test status
Simulation time 489684830337 ps
CPU time 304.02 seconds
Started Mar 07 12:34:48 PM PST 24
Finished Mar 07 12:39:52 PM PST 24
Peak memory 201280 kb
Host smart-14f57d39-8087-4267-becf-3d52f1d0dcde
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352736579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2352736579
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.491829413
Short name T703
Test name
Test status
Simulation time 158183352678 ps
CPU time 356.98 seconds
Started Mar 07 12:34:47 PM PST 24
Finished Mar 07 12:40:44 PM PST 24
Peak memory 201308 kb
Host smart-ed4d84a2-ea67-4f54-831f-414fc9b10245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491829413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.491829413
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2251706154
Short name T343
Test name
Test status
Simulation time 166910400934 ps
CPU time 380.08 seconds
Started Mar 07 12:34:51 PM PST 24
Finished Mar 07 12:41:12 PM PST 24
Peak memory 201360 kb
Host smart-10d0179c-eb5e-4476-876d-a664a70491c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251706154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2251706154
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.4230159156
Short name T446
Test name
Test status
Simulation time 228091371276 ps
CPU time 498.1 seconds
Started Mar 07 12:34:47 PM PST 24
Finished Mar 07 12:43:05 PM PST 24
Peak memory 201380 kb
Host smart-da27e4f2-c35f-4b8e-9326-37896b659a1d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230159156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.4230159156
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1544902010
Short name T418
Test name
Test status
Simulation time 202286606207 ps
CPU time 480.07 seconds
Started Mar 07 12:34:48 PM PST 24
Finished Mar 07 12:42:48 PM PST 24
Peak memory 201392 kb
Host smart-209e3d5f-b5a4-483e-a951-03a7c98cfe58
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544902010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1544902010
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.4026657640
Short name T192
Test name
Test status
Simulation time 89827782747 ps
CPU time 464.82 seconds
Started Mar 07 12:34:49 PM PST 24
Finished Mar 07 12:42:34 PM PST 24
Peak memory 201752 kb
Host smart-7daca6c7-dcc0-4699-92da-ea4797dbd2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026657640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.4026657640
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3767117809
Short name T516
Test name
Test status
Simulation time 23906007360 ps
CPU time 14.93 seconds
Started Mar 07 12:35:56 PM PST 24
Finished Mar 07 12:36:11 PM PST 24
Peak memory 200752 kb
Host smart-639dffc3-ce82-4522-858d-31fa91a2f134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767117809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3767117809
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3333297799
Short name T601
Test name
Test status
Simulation time 5219212251 ps
CPU time 6.66 seconds
Started Mar 07 12:34:46 PM PST 24
Finished Mar 07 12:34:53 PM PST 24
Peak memory 201128 kb
Host smart-4f6492c7-1fa0-4d2d-9930-5eacfef5d920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333297799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3333297799
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1658847051
Short name T720
Test name
Test status
Simulation time 5610063989 ps
CPU time 4.12 seconds
Started Mar 07 12:34:46 PM PST 24
Finished Mar 07 12:34:50 PM PST 24
Peak memory 201180 kb
Host smart-f157d378-d9cf-4e43-a4d5-6afe862e24a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658847051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1658847051
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.2445988438
Short name T450
Test name
Test status
Simulation time 162796951578 ps
CPU time 102.6 seconds
Started Mar 07 12:34:48 PM PST 24
Finished Mar 07 12:36:32 PM PST 24
Peak memory 201296 kb
Host smart-ffaed54c-919d-47f3-b88c-1d36ae85daf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445988438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.2445988438
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3830483512
Short name T18
Test name
Test status
Simulation time 304454891317 ps
CPU time 128.44 seconds
Started Mar 07 12:34:47 PM PST 24
Finished Mar 07 12:36:55 PM PST 24
Peak memory 209884 kb
Host smart-82874691-8c63-4f71-87aa-f3a67cbb136e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830483512 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3830483512
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3721291368
Short name T441
Test name
Test status
Simulation time 404114030 ps
CPU time 0.78 seconds
Started Mar 07 12:34:58 PM PST 24
Finished Mar 07 12:34:59 PM PST 24
Peak memory 201128 kb
Host smart-a3507cce-4170-45fb-b751-20a5b12a3255
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721291368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3721291368
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3119410224
Short name T208
Test name
Test status
Simulation time 171869527072 ps
CPU time 384.74 seconds
Started Mar 07 12:34:57 PM PST 24
Finished Mar 07 12:41:23 PM PST 24
Peak memory 201300 kb
Host smart-a8c70bb3-efaf-45d0-a111-176d9529ed52
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119410224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3119410224
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.196197622
Short name T238
Test name
Test status
Simulation time 351930620964 ps
CPU time 232.42 seconds
Started Mar 07 12:36:39 PM PST 24
Finished Mar 07 12:40:33 PM PST 24
Peak memory 200412 kb
Host smart-f63ac308-d63c-434d-aa77-d488a87fd0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196197622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.196197622
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.4236077123
Short name T301
Test name
Test status
Simulation time 166717455371 ps
CPU time 339.11 seconds
Started Mar 07 12:34:46 PM PST 24
Finished Mar 07 12:40:25 PM PST 24
Peak memory 201324 kb
Host smart-50568403-7e9f-4b80-88d5-67bc4584914b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236077123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.4236077123
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.4109299285
Short name T383
Test name
Test status
Simulation time 493474075713 ps
CPU time 326.15 seconds
Started Mar 07 12:34:51 PM PST 24
Finished Mar 07 12:40:18 PM PST 24
Peak memory 201420 kb
Host smart-b374784b-c396-4cb7-b678-7b23397a996f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109299285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.4109299285
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3234628950
Short name T76
Test name
Test status
Simulation time 319116585402 ps
CPU time 100.1 seconds
Started Mar 07 12:34:52 PM PST 24
Finished Mar 07 12:36:34 PM PST 24
Peak memory 201392 kb
Host smart-669ee73e-48c8-488c-8140-c3c0abbf267f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234628950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3234628950
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1044574557
Short name T575
Test name
Test status
Simulation time 499442939979 ps
CPU time 92.61 seconds
Started Mar 07 12:34:49 PM PST 24
Finished Mar 07 12:36:22 PM PST 24
Peak memory 201276 kb
Host smart-e5cd139c-87aa-4bec-a351-60347ababd54
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044574557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1044574557
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.738168262
Short name T227
Test name
Test status
Simulation time 577399672140 ps
CPU time 377.64 seconds
Started Mar 07 12:34:56 PM PST 24
Finished Mar 07 12:41:14 PM PST 24
Peak memory 201260 kb
Host smart-18524a84-7dff-404c-b302-50a574354447
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738168262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.738168262
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.522298477
Short name T96
Test name
Test status
Simulation time 602213519396 ps
CPU time 1352.56 seconds
Started Mar 07 12:34:56 PM PST 24
Finished Mar 07 12:57:29 PM PST 24
Peak memory 201308 kb
Host smart-1cf687d2-8afe-416a-9395-19896d7b9809
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522298477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.522298477
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.4192022591
Short name T42
Test name
Test status
Simulation time 124582082691 ps
CPU time 511.88 seconds
Started Mar 07 12:34:58 PM PST 24
Finished Mar 07 12:43:31 PM PST 24
Peak memory 201756 kb
Host smart-fdb0c419-79c5-4f48-81db-7b58c940502b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192022591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.4192022591
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2210537077
Short name T561
Test name
Test status
Simulation time 28934778017 ps
CPU time 34.58 seconds
Started Mar 07 12:34:56 PM PST 24
Finished Mar 07 12:35:31 PM PST 24
Peak memory 201176 kb
Host smart-3d576c7f-0fdc-404b-adc5-8d9bd1354189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210537077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2210537077
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1687881575
Short name T517
Test name
Test status
Simulation time 3627248346 ps
CPU time 5.18 seconds
Started Mar 07 12:34:58 PM PST 24
Finished Mar 07 12:35:04 PM PST 24
Peak memory 201156 kb
Host smart-9bcdbe71-7e1a-4c80-bccc-c4ec78d2c266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687881575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1687881575
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2346894888
Short name T461
Test name
Test status
Simulation time 5777501936 ps
CPU time 14 seconds
Started Mar 07 12:36:53 PM PST 24
Finished Mar 07 12:37:08 PM PST 24
Peak memory 200808 kb
Host smart-b246ef3d-76d9-4212-9922-5da9fa8c293b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346894888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2346894888
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.2933787534
Short name T710
Test name
Test status
Simulation time 117273159096 ps
CPU time 128.3 seconds
Started Mar 07 12:34:54 PM PST 24
Finished Mar 07 12:37:04 PM PST 24
Peak memory 209768 kb
Host smart-c29a97a4-d86d-4884-9a70-ca8cb15093ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933787534 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.2933787534
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.447407579
Short name T353
Test name
Test status
Simulation time 421673732 ps
CPU time 0.84 seconds
Started Mar 07 12:33:14 PM PST 24
Finished Mar 07 12:33:15 PM PST 24
Peak memory 201044 kb
Host smart-6537b310-fad3-4d77-8540-5b7b18ed03ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447407579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.447407579
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.810272
Short name T537
Test name
Test status
Simulation time 598297092805 ps
CPU time 360.96 seconds
Started Mar 07 12:33:22 PM PST 24
Finished Mar 07 12:39:23 PM PST 24
Peak memory 201328 kb
Host smart-a6beb9aa-790b-4fe1-8bfd-a78ffa0f18f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.810272
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.501311641
Short name T780
Test name
Test status
Simulation time 326268697913 ps
CPU time 784.98 seconds
Started Mar 07 12:33:40 PM PST 24
Finished Mar 07 12:46:45 PM PST 24
Peak memory 201348 kb
Host smart-47cdcb4a-93e5-4c4f-a948-bab1f0facf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501311641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.501311641
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1254399262
Short name T583
Test name
Test status
Simulation time 162825080557 ps
CPU time 87.49 seconds
Started Mar 07 12:33:15 PM PST 24
Finished Mar 07 12:34:43 PM PST 24
Peak memory 201376 kb
Host smart-03be8b74-546c-45c5-829c-95510ca593bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254399262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1254399262
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2322735666
Short name T233
Test name
Test status
Simulation time 323907786202 ps
CPU time 729.42 seconds
Started Mar 07 12:33:22 PM PST 24
Finished Mar 07 12:45:32 PM PST 24
Peak memory 201328 kb
Host smart-40ca7602-d464-4441-878f-f12b691f4bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322735666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2322735666
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.3225503784
Short name T424
Test name
Test status
Simulation time 165023424076 ps
CPU time 102.37 seconds
Started Mar 07 12:33:22 PM PST 24
Finished Mar 07 12:35:05 PM PST 24
Peak memory 201404 kb
Host smart-afc6fea5-b2df-4f29-a276-1f56762b89ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225503784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.3225503784
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1924636130
Short name T246
Test name
Test status
Simulation time 378664122326 ps
CPU time 889.84 seconds
Started Mar 07 12:33:19 PM PST 24
Finished Mar 07 12:48:09 PM PST 24
Peak memory 201328 kb
Host smart-7c8e191c-ac31-4b2f-ab9d-21ff846f96bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924636130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1924636130
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3951658942
Short name T357
Test name
Test status
Simulation time 395638309278 ps
CPU time 961.83 seconds
Started Mar 07 12:33:20 PM PST 24
Finished Mar 07 12:49:22 PM PST 24
Peak memory 201288 kb
Host smart-b40af3db-2a62-4bf9-bc0b-e3512194c569
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951658942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3951658942
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2026446602
Short name T45
Test name
Test status
Simulation time 123553101563 ps
CPU time 432.75 seconds
Started Mar 07 12:33:20 PM PST 24
Finished Mar 07 12:40:33 PM PST 24
Peak memory 201688 kb
Host smart-297fb02a-8a42-41f7-85de-9ad0cb3229bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026446602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2026446602
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2808304343
Short name T479
Test name
Test status
Simulation time 40410799825 ps
CPU time 44.9 seconds
Started Mar 07 12:33:20 PM PST 24
Finished Mar 07 12:34:05 PM PST 24
Peak memory 201156 kb
Host smart-3ab30f50-c98b-4157-af44-3255ceb81a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808304343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2808304343
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.752972494
Short name T434
Test name
Test status
Simulation time 4216902816 ps
CPU time 10.63 seconds
Started Mar 07 12:33:24 PM PST 24
Finished Mar 07 12:33:34 PM PST 24
Peak memory 201112 kb
Host smart-dcf51862-25bd-4e7b-adb1-b166cbdd0788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752972494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.752972494
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3804277623
Short name T719
Test name
Test status
Simulation time 5705315257 ps
CPU time 4.42 seconds
Started Mar 07 12:33:23 PM PST 24
Finished Mar 07 12:33:28 PM PST 24
Peak memory 201164 kb
Host smart-411741ff-d40a-4a68-9f93-4ee6233c53f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804277623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3804277623
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2801243795
Short name T326
Test name
Test status
Simulation time 264411814920 ps
CPU time 694.18 seconds
Started Mar 07 12:33:35 PM PST 24
Finished Mar 07 12:45:09 PM PST 24
Peak memory 201668 kb
Host smart-44ecefe5-2cdb-48c7-a965-c8bc42591b30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801243795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2801243795
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.635050079
Short name T709
Test name
Test status
Simulation time 432835555 ps
CPU time 0.88 seconds
Started Mar 07 12:35:10 PM PST 24
Finished Mar 07 12:35:11 PM PST 24
Peak memory 201108 kb
Host smart-755dfc01-1074-4d96-8b56-906ea2249779
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635050079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.635050079
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2899058522
Short name T611
Test name
Test status
Simulation time 327084913813 ps
CPU time 213.26 seconds
Started Mar 07 12:34:56 PM PST 24
Finished Mar 07 12:38:30 PM PST 24
Peak memory 201396 kb
Host smart-ecc4fb3b-18ac-4f78-953c-16e381361f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899058522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2899058522
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.590610207
Short name T351
Test name
Test status
Simulation time 324603117127 ps
CPU time 202.42 seconds
Started Mar 07 12:34:57 PM PST 24
Finished Mar 07 12:38:21 PM PST 24
Peak memory 201304 kb
Host smart-bfbc36dc-5958-4385-9ef1-235f91367f22
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=590610207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.590610207
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.406539075
Short name T766
Test name
Test status
Simulation time 320675218260 ps
CPU time 182.34 seconds
Started Mar 07 12:34:55 PM PST 24
Finished Mar 07 12:37:58 PM PST 24
Peak memory 201308 kb
Host smart-3aa09fc6-8c41-469a-87f6-5360562a6047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406539075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.406539075
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3640203641
Short name T466
Test name
Test status
Simulation time 162044303282 ps
CPU time 103.76 seconds
Started Mar 07 12:34:57 PM PST 24
Finished Mar 07 12:36:42 PM PST 24
Peak memory 201304 kb
Host smart-8e5177c9-d599-45f3-b228-5f5fdc9ca6fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640203641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3640203641
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.555887262
Short name T312
Test name
Test status
Simulation time 357811310720 ps
CPU time 822.83 seconds
Started Mar 07 12:34:58 PM PST 24
Finished Mar 07 12:48:42 PM PST 24
Peak memory 201332 kb
Host smart-292220a5-0746-43de-a837-a7f68e4d47eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555887262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.555887262
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.1536501917
Short name T755
Test name
Test status
Simulation time 200430457881 ps
CPU time 487.77 seconds
Started Mar 07 12:36:53 PM PST 24
Finished Mar 07 12:45:02 PM PST 24
Peak memory 200940 kb
Host smart-edda5c56-9cf8-40cc-b83e-5a3611c82456
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536501917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.1536501917
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2427019345
Short name T613
Test name
Test status
Simulation time 75766064696 ps
CPU time 390.42 seconds
Started Mar 07 12:35:10 PM PST 24
Finished Mar 07 12:41:41 PM PST 24
Peak memory 201628 kb
Host smart-7a323dfd-56f4-4c87-abf5-4da149f2ca84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427019345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2427019345
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2961023922
Short name T525
Test name
Test status
Simulation time 30543215032 ps
CPU time 16.85 seconds
Started Mar 07 12:35:04 PM PST 24
Finished Mar 07 12:35:21 PM PST 24
Peak memory 201128 kb
Host smart-6bf755c9-e2c0-4a3d-9792-01e9d443a0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961023922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2961023922
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.458097442
Short name T547
Test name
Test status
Simulation time 4720025951 ps
CPU time 1.87 seconds
Started Mar 07 12:35:05 PM PST 24
Finished Mar 07 12:35:07 PM PST 24
Peak memory 201152 kb
Host smart-194295f5-d7a6-4f0d-985a-6258f411447a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458097442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.458097442
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1714641254
Short name T534
Test name
Test status
Simulation time 5631330191 ps
CPU time 7.14 seconds
Started Mar 07 12:34:57 PM PST 24
Finished Mar 07 12:35:06 PM PST 24
Peak memory 201252 kb
Host smart-d1f53e5e-3459-4098-96b6-213652aeeb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714641254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1714641254
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2811481453
Short name T335
Test name
Test status
Simulation time 864713018541 ps
CPU time 2085.86 seconds
Started Mar 07 12:35:11 PM PST 24
Finished Mar 07 01:09:57 PM PST 24
Peak memory 209940 kb
Host smart-7e4a7990-37b4-476e-ae63-675268cd5ac3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811481453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2811481453
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3715896495
Short name T181
Test name
Test status
Simulation time 52335370292 ps
CPU time 127.48 seconds
Started Mar 07 12:35:10 PM PST 24
Finished Mar 07 12:37:17 PM PST 24
Peak memory 209728 kb
Host smart-9fd1da04-9f04-4124-b628-5160e196b6d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715896495 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3715896495
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1863024752
Short name T362
Test name
Test status
Simulation time 312373845 ps
CPU time 0.93 seconds
Started Mar 07 12:35:17 PM PST 24
Finished Mar 07 12:35:18 PM PST 24
Peak memory 201128 kb
Host smart-6f3c9518-a53f-49a8-bc9e-1a5933c0d28f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863024752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1863024752
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.3052686458
Short name T573
Test name
Test status
Simulation time 510176341534 ps
CPU time 134.21 seconds
Started Mar 07 12:35:17 PM PST 24
Finished Mar 07 12:37:32 PM PST 24
Peak memory 201328 kb
Host smart-3a92b2a7-f61f-48f3-96da-f9e4865a200c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052686458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.3052686458
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.4267973858
Short name T469
Test name
Test status
Simulation time 494186408590 ps
CPU time 632.8 seconds
Started Mar 07 12:35:18 PM PST 24
Finished Mar 07 12:45:51 PM PST 24
Peak memory 201352 kb
Host smart-0c87f154-6a8b-44cb-aac8-75818005ea4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267973858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.4267973858
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2984132065
Short name T240
Test name
Test status
Simulation time 167172990149 ps
CPU time 201.5 seconds
Started Mar 07 12:35:11 PM PST 24
Finished Mar 07 12:38:32 PM PST 24
Peak memory 201216 kb
Host smart-1ef11d9d-790d-4f21-b207-01771b01a579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984132065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2984132065
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3373661200
Short name T403
Test name
Test status
Simulation time 160673362469 ps
CPU time 96.66 seconds
Started Mar 07 12:35:10 PM PST 24
Finished Mar 07 12:36:47 PM PST 24
Peak memory 201236 kb
Host smart-0b5cb758-3f35-481b-b6da-56bf8234a5d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373661200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3373661200
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.673103942
Short name T164
Test name
Test status
Simulation time 495150228093 ps
CPU time 280.61 seconds
Started Mar 07 12:35:05 PM PST 24
Finished Mar 07 12:39:46 PM PST 24
Peak memory 201340 kb
Host smart-9e42c149-151d-40fb-acb0-f993f39812ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673103942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.673103942
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1274290257
Short name T143
Test name
Test status
Simulation time 324555828292 ps
CPU time 796.42 seconds
Started Mar 07 12:35:07 PM PST 24
Finished Mar 07 12:48:24 PM PST 24
Peak memory 201316 kb
Host smart-c3d97d40-b64a-4fc9-9b3e-2d9247155de5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274290257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1274290257
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.849533869
Short name T217
Test name
Test status
Simulation time 164648250260 ps
CPU time 210.32 seconds
Started Mar 07 12:35:11 PM PST 24
Finished Mar 07 12:38:41 PM PST 24
Peak memory 201248 kb
Host smart-0b04381b-ac98-4b65-803d-242d67a62dfb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849533869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.849533869
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2860522316
Short name T732
Test name
Test status
Simulation time 607362396265 ps
CPU time 1381.57 seconds
Started Mar 07 12:35:17 PM PST 24
Finished Mar 07 12:58:18 PM PST 24
Peak memory 201352 kb
Host smart-40e17310-ef2c-495e-a8f6-ac3898dc78b0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860522316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2860522316
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.17714561
Short name T46
Test name
Test status
Simulation time 129608876849 ps
CPU time 592.64 seconds
Started Mar 07 12:35:17 PM PST 24
Finished Mar 07 12:45:10 PM PST 24
Peak memory 201676 kb
Host smart-e6c06e69-b48c-4494-9163-7cadd3903b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17714561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.17714561
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2007923626
Short name T507
Test name
Test status
Simulation time 42434593339 ps
CPU time 42.98 seconds
Started Mar 07 12:35:16 PM PST 24
Finished Mar 07 12:35:59 PM PST 24
Peak memory 201184 kb
Host smart-33844517-f116-4d3e-9fa1-45a369a55eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007923626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2007923626
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1678140015
Short name T451
Test name
Test status
Simulation time 3684454959 ps
CPU time 5.74 seconds
Started Mar 07 12:35:18 PM PST 24
Finished Mar 07 12:35:24 PM PST 24
Peak memory 201088 kb
Host smart-610fb491-8432-4517-b7d5-f4f046a12176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678140015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1678140015
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.2297177018
Short name T376
Test name
Test status
Simulation time 5904580426 ps
CPU time 3.87 seconds
Started Mar 07 12:35:05 PM PST 24
Finished Mar 07 12:35:08 PM PST 24
Peak memory 201192 kb
Host smart-1cadd6fb-44fd-4af6-8ee4-42e0c01e054a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297177018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2297177018
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3870713905
Short name T262
Test name
Test status
Simulation time 11577232132 ps
CPU time 22.7 seconds
Started Mar 07 12:35:17 PM PST 24
Finished Mar 07 12:35:39 PM PST 24
Peak memory 209780 kb
Host smart-d0076c40-610c-466e-9535-6b37fbd06423
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870713905 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3870713905
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2010364574
Short name T421
Test name
Test status
Simulation time 456451667 ps
CPU time 1.57 seconds
Started Mar 07 12:35:28 PM PST 24
Finished Mar 07 12:35:30 PM PST 24
Peak memory 201108 kb
Host smart-64545489-e3cc-46a9-ba02-eb37b6a69d00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010364574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2010364574
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3583008399
Short name T588
Test name
Test status
Simulation time 177378595101 ps
CPU time 59.41 seconds
Started Mar 07 12:35:16 PM PST 24
Finished Mar 07 12:36:15 PM PST 24
Peak memory 201312 kb
Host smart-f17591b5-7283-413c-b8c1-e108932a3bbc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583008399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3583008399
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3302844229
Short name T746
Test name
Test status
Simulation time 555723280289 ps
CPU time 1258.12 seconds
Started Mar 07 12:35:17 PM PST 24
Finished Mar 07 12:56:15 PM PST 24
Peak memory 201304 kb
Host smart-59642efa-4a4d-4d47-ac36-b5a5981615d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302844229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3302844229
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1165633916
Short name T688
Test name
Test status
Simulation time 484944613374 ps
CPU time 595.48 seconds
Started Mar 07 12:35:17 PM PST 24
Finished Mar 07 12:45:12 PM PST 24
Peak memory 201380 kb
Host smart-ca2725a9-c4ee-4171-8a54-41ec5fdceb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165633916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1165633916
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2624659238
Short name T565
Test name
Test status
Simulation time 492741119093 ps
CPU time 1143.55 seconds
Started Mar 07 12:35:17 PM PST 24
Finished Mar 07 12:54:21 PM PST 24
Peak memory 201360 kb
Host smart-fbfac7ca-34f9-4497-8df1-fb1b1c3ac8a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624659238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2624659238
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1645987851
Short name T624
Test name
Test status
Simulation time 167311341714 ps
CPU time 103.79 seconds
Started Mar 07 12:35:17 PM PST 24
Finished Mar 07 12:37:01 PM PST 24
Peak memory 201324 kb
Host smart-f2e751af-629d-4eb2-9955-ab361f54a32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645987851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1645987851
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2572776414
Short name T470
Test name
Test status
Simulation time 474802518114 ps
CPU time 1060.05 seconds
Started Mar 07 12:35:17 PM PST 24
Finished Mar 07 12:52:57 PM PST 24
Peak memory 201300 kb
Host smart-edd49d02-e772-4e7e-a321-77e7087b0c66
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572776414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2572776414
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3250565485
Short name T39
Test name
Test status
Simulation time 177459078392 ps
CPU time 193.69 seconds
Started Mar 07 12:35:18 PM PST 24
Finished Mar 07 12:38:32 PM PST 24
Peak memory 201396 kb
Host smart-11b57a1b-9ff0-4088-95ad-ef6dc013b2ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250565485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3250565485
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2664960526
Short name T684
Test name
Test status
Simulation time 390807718676 ps
CPU time 462.04 seconds
Started Mar 07 12:35:16 PM PST 24
Finished Mar 07 12:42:59 PM PST 24
Peak memory 201252 kb
Host smart-f0eb6315-abfd-43e3-bb44-1ac652198cb4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664960526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.2664960526
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.21567416
Short name T566
Test name
Test status
Simulation time 120417549132 ps
CPU time 436.09 seconds
Started Mar 07 12:35:28 PM PST 24
Finished Mar 07 12:42:44 PM PST 24
Peak memory 201700 kb
Host smart-e6a0ba45-e5d6-4afa-b2e5-a5300bd817c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21567416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.21567416
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.214476284
Short name T689
Test name
Test status
Simulation time 24271691258 ps
CPU time 40.15 seconds
Started Mar 07 12:35:27 PM PST 24
Finished Mar 07 12:36:08 PM PST 24
Peak memory 201204 kb
Host smart-98d0d901-e1a6-47a2-ba94-9c73cbcefbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214476284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.214476284
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3399720678
Short name T532
Test name
Test status
Simulation time 3140859631 ps
CPU time 4.66 seconds
Started Mar 07 12:35:28 PM PST 24
Finished Mar 07 12:35:33 PM PST 24
Peak memory 201188 kb
Host smart-3a974181-3dec-471b-ad13-9e18d0071f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399720678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3399720678
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2085074656
Short name T359
Test name
Test status
Simulation time 5716542178 ps
CPU time 14.41 seconds
Started Mar 07 12:35:18 PM PST 24
Finished Mar 07 12:35:32 PM PST 24
Peak memory 201112 kb
Host smart-87d44699-b8a9-478e-be02-6b12df827a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085074656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2085074656
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3638253374
Short name T465
Test name
Test status
Simulation time 35496201428 ps
CPU time 83.06 seconds
Started Mar 07 12:35:30 PM PST 24
Finished Mar 07 12:36:53 PM PST 24
Peak memory 201252 kb
Host smart-6e0486ab-e79e-4f35-a2ef-9f28e2fe1db5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638253374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3638253374
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.1140210548
Short name T616
Test name
Test status
Simulation time 505333096 ps
CPU time 1.23 seconds
Started Mar 07 12:35:31 PM PST 24
Finished Mar 07 12:35:32 PM PST 24
Peak memory 201120 kb
Host smart-78de9568-94f4-4636-bd60-1c1a32cd7125
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140210548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1140210548
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3888256406
Short name T157
Test name
Test status
Simulation time 489880197238 ps
CPU time 1040.98 seconds
Started Mar 07 12:35:29 PM PST 24
Finished Mar 07 12:52:50 PM PST 24
Peak memory 201368 kb
Host smart-72d29952-ca6d-4028-ad14-5c11f006abbc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888256406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3888256406
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.2152981953
Short name T654
Test name
Test status
Simulation time 167505115772 ps
CPU time 47.6 seconds
Started Mar 07 12:35:30 PM PST 24
Finished Mar 07 12:36:17 PM PST 24
Peak memory 201384 kb
Host smart-90ae69fd-b8dd-4bbd-8bde-f8e2ba5588b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152981953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2152981953
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3626915951
Short name T510
Test name
Test status
Simulation time 160080349800 ps
CPU time 392.63 seconds
Started Mar 07 12:35:28 PM PST 24
Finished Mar 07 12:42:01 PM PST 24
Peak memory 201288 kb
Host smart-b105cf7b-d495-4f39-a611-3158e74204ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626915951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.3626915951
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3322006016
Short name T543
Test name
Test status
Simulation time 163809765491 ps
CPU time 104.52 seconds
Started Mar 07 12:35:28 PM PST 24
Finished Mar 07 12:37:13 PM PST 24
Peak memory 201372 kb
Host smart-759ea4a8-ddb8-4bc8-b81c-21c38748180b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322006016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3322006016
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3595418297
Short name T618
Test name
Test status
Simulation time 159748618451 ps
CPU time 91.53 seconds
Started Mar 07 12:35:28 PM PST 24
Finished Mar 07 12:37:00 PM PST 24
Peak memory 201368 kb
Host smart-d5b81bb1-cdec-40e1-8d57-cdbc5352543c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595418297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3595418297
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2305401112
Short name T224
Test name
Test status
Simulation time 604651745949 ps
CPU time 383.75 seconds
Started Mar 07 12:35:29 PM PST 24
Finished Mar 07 12:41:53 PM PST 24
Peak memory 201272 kb
Host smart-0f57b699-abf1-4b52-bcc6-3fc575fea433
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305401112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2305401112
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.286088137
Short name T399
Test name
Test status
Simulation time 619766886422 ps
CPU time 1388.72 seconds
Started Mar 07 12:35:32 PM PST 24
Finished Mar 07 12:58:41 PM PST 24
Peak memory 200516 kb
Host smart-48deda6b-4b17-41d4-b721-1c0372612e24
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286088137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
adc_ctrl_filters_wakeup_fixed.286088137
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.403511975
Short name T738
Test name
Test status
Simulation time 46242285012 ps
CPU time 98.52 seconds
Started Mar 07 12:35:27 PM PST 24
Finished Mar 07 12:37:06 PM PST 24
Peak memory 201164 kb
Host smart-554a3b02-f67f-4703-8e1d-87b43816a4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403511975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.403511975
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.1270448015
Short name T576
Test name
Test status
Simulation time 4914741979 ps
CPU time 12.7 seconds
Started Mar 07 12:35:27 PM PST 24
Finished Mar 07 12:35:40 PM PST 24
Peak memory 201160 kb
Host smart-ab3b4625-5fdc-4d0e-b735-f427bedd9a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270448015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.1270448015
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2564186120
Short name T775
Test name
Test status
Simulation time 5938768917 ps
CPU time 4.57 seconds
Started Mar 07 12:35:30 PM PST 24
Finished Mar 07 12:35:34 PM PST 24
Peak memory 201268 kb
Host smart-359c2bf3-afad-44d2-b393-7631eb8544f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564186120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2564186120
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.206836912
Short name T28
Test name
Test status
Simulation time 482767460070 ps
CPU time 1196.24 seconds
Started Mar 07 12:35:31 PM PST 24
Finished Mar 07 12:55:27 PM PST 24
Peak memory 201756 kb
Host smart-5b764fd2-a32f-4ae2-bad6-0441cda5e7b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206836912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
206836912
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3225631251
Short name T409
Test name
Test status
Simulation time 485777984 ps
CPU time 0.9 seconds
Started Mar 07 12:35:38 PM PST 24
Finished Mar 07 12:35:39 PM PST 24
Peak memory 201172 kb
Host smart-894c9616-932e-497a-bb44-cef8244ddf38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225631251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3225631251
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3786886034
Short name T786
Test name
Test status
Simulation time 330308154842 ps
CPU time 773.7 seconds
Started Mar 07 12:36:53 PM PST 24
Finished Mar 07 12:49:48 PM PST 24
Peak memory 200948 kb
Host smart-6f03c5e2-9c61-48c0-adbe-daa3103a1483
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786886034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3786886034
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2840633545
Short name T651
Test name
Test status
Simulation time 180861108727 ps
CPU time 194.94 seconds
Started Mar 07 12:35:37 PM PST 24
Finished Mar 07 12:38:52 PM PST 24
Peak memory 201292 kb
Host smart-266e241b-72d7-459c-a7be-7d07f135fe4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840633545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2840633545
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.1314570988
Short name T653
Test name
Test status
Simulation time 163597490620 ps
CPU time 355.54 seconds
Started Mar 07 12:35:28 PM PST 24
Finished Mar 07 12:41:23 PM PST 24
Peak memory 201324 kb
Host smart-44539916-0b95-445d-807d-1af1673e90f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314570988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1314570988
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1273228591
Short name T714
Test name
Test status
Simulation time 327790189272 ps
CPU time 181.08 seconds
Started Mar 07 12:35:36 PM PST 24
Finished Mar 07 12:38:38 PM PST 24
Peak memory 201308 kb
Host smart-87b542e5-5c80-4d35-9698-ff67ecd7af53
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273228591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1273228591
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.99296484
Short name T101
Test name
Test status
Simulation time 161320135499 ps
CPU time 165.83 seconds
Started Mar 07 12:35:28 PM PST 24
Finished Mar 07 12:38:14 PM PST 24
Peak memory 201364 kb
Host smart-46aa85a8-e8d3-4af4-801f-b74f1498c5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99296484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.99296484
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.4214186455
Short name T607
Test name
Test status
Simulation time 330533803393 ps
CPU time 832.39 seconds
Started Mar 07 12:35:32 PM PST 24
Finished Mar 07 12:49:25 PM PST 24
Peak memory 201288 kb
Host smart-0ec2df8e-33ea-48cc-a356-4fd62a4871e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214186455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.4214186455
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.3252024218
Short name T706
Test name
Test status
Simulation time 171597534056 ps
CPU time 70.86 seconds
Started Mar 07 12:35:37 PM PST 24
Finished Mar 07 12:36:48 PM PST 24
Peak memory 201292 kb
Host smart-e06e9151-7ff0-44e4-80f5-8090ec96f072
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252024218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.3252024218
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3742323072
Short name T478
Test name
Test status
Simulation time 402909202819 ps
CPU time 228.16 seconds
Started Mar 07 12:35:36 PM PST 24
Finished Mar 07 12:39:24 PM PST 24
Peak memory 201324 kb
Host smart-3444d832-9e43-4766-9fff-1d4d74c57efd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742323072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3742323072
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.4069640255
Short name T659
Test name
Test status
Simulation time 41223711429 ps
CPU time 91.55 seconds
Started Mar 07 12:35:36 PM PST 24
Finished Mar 07 12:37:08 PM PST 24
Peak memory 201064 kb
Host smart-23d38d36-a97e-47f1-8c51-cfbe805479a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069640255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.4069640255
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1992340535
Short name T657
Test name
Test status
Simulation time 4703768280 ps
CPU time 2.85 seconds
Started Mar 07 12:35:37 PM PST 24
Finished Mar 07 12:35:40 PM PST 24
Peak memory 201208 kb
Host smart-76d36db5-15b4-4817-a8e4-da75c99bfacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992340535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1992340535
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1211560806
Short name T500
Test name
Test status
Simulation time 6021695648 ps
CPU time 8.52 seconds
Started Mar 07 12:35:34 PM PST 24
Finished Mar 07 12:35:42 PM PST 24
Peak memory 201188 kb
Host smart-5747eeaa-d1b1-47e1-93f5-90b6115f2ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211560806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1211560806
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.358018258
Short name T17
Test name
Test status
Simulation time 391345292606 ps
CPU time 218.8 seconds
Started Mar 07 12:35:36 PM PST 24
Finished Mar 07 12:39:15 PM PST 24
Peak memory 212164 kb
Host smart-e96f942a-d826-4e5e-b7a6-fc918d2a915a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358018258 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.358018258
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.183824523
Short name T641
Test name
Test status
Simulation time 416729227 ps
CPU time 1.69 seconds
Started Mar 07 12:36:53 PM PST 24
Finished Mar 07 12:36:56 PM PST 24
Peak memory 200716 kb
Host smart-122cec54-ea5e-4c46-8ead-0b0f051ddaa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183824523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.183824523
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.88828325
Short name T411
Test name
Test status
Simulation time 165044164676 ps
CPU time 102.62 seconds
Started Mar 07 12:35:36 PM PST 24
Finished Mar 07 12:37:19 PM PST 24
Peak memory 201324 kb
Host smart-8db84daa-a1ba-4a17-ad5c-1057ff1a840e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88828325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gatin
g.88828325
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2008645641
Short name T8
Test name
Test status
Simulation time 212198766992 ps
CPU time 114.39 seconds
Started Mar 07 12:35:38 PM PST 24
Finished Mar 07 12:37:32 PM PST 24
Peak memory 201332 kb
Host smart-e81fbcf9-d84a-4bc7-9fe1-c9bd79fbb005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008645641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2008645641
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2402387463
Short name T206
Test name
Test status
Simulation time 491242030290 ps
CPU time 1264.21 seconds
Started Mar 07 12:35:36 PM PST 24
Finished Mar 07 12:56:41 PM PST 24
Peak memory 201216 kb
Host smart-06fe2186-dcbc-4581-bb7a-f5ba7bd80d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402387463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2402387463
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.4125539707
Short name T563
Test name
Test status
Simulation time 336747260374 ps
CPU time 404.64 seconds
Started Mar 07 12:35:39 PM PST 24
Finished Mar 07 12:42:24 PM PST 24
Peak memory 201312 kb
Host smart-fdcdc22e-19d1-4240-98d7-9e994a66d0a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125539707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.4125539707
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.2878709771
Short name T307
Test name
Test status
Simulation time 331838631251 ps
CPU time 184.98 seconds
Started Mar 07 12:35:35 PM PST 24
Finished Mar 07 12:38:40 PM PST 24
Peak memory 201324 kb
Host smart-5a375da5-885b-4e64-93eb-cb80055966c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878709771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2878709771
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2144706354
Short name T440
Test name
Test status
Simulation time 325060483021 ps
CPU time 179.02 seconds
Started Mar 07 12:35:41 PM PST 24
Finished Mar 07 12:38:40 PM PST 24
Peak memory 201320 kb
Host smart-d0477fe4-45fc-453c-bc5a-b450ae3f0b1f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144706354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2144706354
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1021649208
Short name T771
Test name
Test status
Simulation time 394925973960 ps
CPU time 186.43 seconds
Started Mar 07 12:35:36 PM PST 24
Finished Mar 07 12:38:42 PM PST 24
Peak memory 201316 kb
Host smart-5f2cedb4-9cb2-432c-9e6c-477635145161
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021649208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1021649208
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2406035056
Short name T187
Test name
Test status
Simulation time 116903028459 ps
CPU time 455.36 seconds
Started Mar 07 12:35:43 PM PST 24
Finished Mar 07 12:43:19 PM PST 24
Peak memory 201708 kb
Host smart-2c191283-5904-4c29-86f8-2fb220ffd09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406035056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2406035056
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1709002884
Short name T499
Test name
Test status
Simulation time 35590902329 ps
CPU time 6 seconds
Started Mar 07 12:35:38 PM PST 24
Finished Mar 07 12:35:44 PM PST 24
Peak memory 201184 kb
Host smart-ef228fd7-3ae7-4bb2-be82-e7b1232bbbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709002884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1709002884
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2392888154
Short name T539
Test name
Test status
Simulation time 4898861332 ps
CPU time 3.1 seconds
Started Mar 07 12:35:40 PM PST 24
Finished Mar 07 12:35:44 PM PST 24
Peak memory 201068 kb
Host smart-66c1cf86-dc38-4dec-9489-9204c53a53b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392888154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2392888154
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3191995867
Short name T707
Test name
Test status
Simulation time 5929130249 ps
CPU time 15.17 seconds
Started Mar 07 12:35:36 PM PST 24
Finished Mar 07 12:35:52 PM PST 24
Peak memory 201164 kb
Host smart-35f9f4ac-1654-4c7f-b3b6-f0223a8ef779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191995867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3191995867
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1382573121
Short name T727
Test name
Test status
Simulation time 19554416802 ps
CPU time 59.73 seconds
Started Mar 07 12:35:38 PM PST 24
Finished Mar 07 12:36:38 PM PST 24
Peak memory 210096 kb
Host smart-abbb9d39-166b-4ac1-8bd1-65fc94a6b1fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382573121 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1382573121
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1981666484
Short name T524
Test name
Test status
Simulation time 486258588 ps
CPU time 1.17 seconds
Started Mar 07 12:35:47 PM PST 24
Finished Mar 07 12:35:48 PM PST 24
Peak memory 201116 kb
Host smart-88507adb-0b5b-4d50-96ee-dc8db867b868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981666484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1981666484
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1263261087
Short name T13
Test name
Test status
Simulation time 161521093357 ps
CPU time 65.46 seconds
Started Mar 07 12:35:47 PM PST 24
Finished Mar 07 12:36:53 PM PST 24
Peak memory 201388 kb
Host smart-61333138-7ce7-41cd-af9f-01ba62ce5ab0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263261087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1263261087
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.1680825514
Short name T270
Test name
Test status
Simulation time 364378957156 ps
CPU time 863.46 seconds
Started Mar 07 12:35:46 PM PST 24
Finished Mar 07 12:50:10 PM PST 24
Peak memory 201324 kb
Host smart-63cda2bb-70f9-478a-9d1d-763e2b1bf02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680825514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.1680825514
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.4043968637
Short name T149
Test name
Test status
Simulation time 492919921144 ps
CPU time 294.55 seconds
Started Mar 07 12:35:46 PM PST 24
Finished Mar 07 12:40:41 PM PST 24
Peak memory 201340 kb
Host smart-1ccca23f-8f0e-4e1c-8f0a-a13fc9830402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043968637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.4043968637
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2060669523
Short name T472
Test name
Test status
Simulation time 491636830670 ps
CPU time 590.35 seconds
Started Mar 07 12:35:47 PM PST 24
Finished Mar 07 12:45:38 PM PST 24
Peak memory 201380 kb
Host smart-2d3bd59f-deba-4df3-b690-6566e2a33142
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060669523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2060669523
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.4032785450
Short name T218
Test name
Test status
Simulation time 326042631299 ps
CPU time 770.97 seconds
Started Mar 07 12:35:36 PM PST 24
Finished Mar 07 12:48:27 PM PST 24
Peak memory 201276 kb
Host smart-5f1185e1-c8a9-4568-9393-4eb70743a8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032785450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.4032785450
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3711643066
Short name T369
Test name
Test status
Simulation time 335350383882 ps
CPU time 367.57 seconds
Started Mar 07 12:35:48 PM PST 24
Finished Mar 07 12:41:56 PM PST 24
Peak memory 201320 kb
Host smart-70e25e06-398e-4e1d-aed6-0f97215a8fb3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711643066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3711643066
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.753754865
Short name T322
Test name
Test status
Simulation time 348417003050 ps
CPU time 142.41 seconds
Started Mar 07 12:35:47 PM PST 24
Finished Mar 07 12:38:10 PM PST 24
Peak memory 201332 kb
Host smart-24f3ba49-76d7-4643-a4d8-5fa152fbaf65
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753754865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.753754865
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3847042143
Short name T595
Test name
Test status
Simulation time 198807133643 ps
CPU time 458.09 seconds
Started Mar 07 12:35:47 PM PST 24
Finished Mar 07 12:43:25 PM PST 24
Peak memory 201300 kb
Host smart-c7560cce-6ddd-4970-8187-8c957ecb681e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847042143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3847042143
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.2184023732
Short name T336
Test name
Test status
Simulation time 142701937655 ps
CPU time 711.53 seconds
Started Mar 07 12:35:45 PM PST 24
Finished Mar 07 12:47:37 PM PST 24
Peak memory 201644 kb
Host smart-0770c75c-fc42-439f-8c45-f8f405fe7c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184023732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.2184023732
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2719959858
Short name T475
Test name
Test status
Simulation time 24264030862 ps
CPU time 48.73 seconds
Started Mar 07 12:35:47 PM PST 24
Finished Mar 07 12:36:36 PM PST 24
Peak memory 201268 kb
Host smart-11483c71-60af-47cf-b817-da2546ac39d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719959858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2719959858
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2715238232
Short name T519
Test name
Test status
Simulation time 3423966000 ps
CPU time 8.79 seconds
Started Mar 07 12:35:49 PM PST 24
Finished Mar 07 12:35:58 PM PST 24
Peak memory 201200 kb
Host smart-e6b3f126-f927-409d-be14-8f4435eee5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715238232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2715238232
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3756066804
Short name T572
Test name
Test status
Simulation time 5789885792 ps
CPU time 7.92 seconds
Started Mar 07 12:35:36 PM PST 24
Finished Mar 07 12:35:44 PM PST 24
Peak memory 201180 kb
Host smart-a32e412c-3de3-432e-af11-18c7df354893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756066804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3756066804
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1396354633
Short name T145
Test name
Test status
Simulation time 339292238604 ps
CPU time 387.45 seconds
Started Mar 07 12:35:47 PM PST 24
Finished Mar 07 12:42:15 PM PST 24
Peak memory 201280 kb
Host smart-6aec50ca-57af-43cb-9423-a1a3f0b3f4ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396354633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1396354633
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.58536064
Short name T373
Test name
Test status
Simulation time 387961874 ps
CPU time 1.08 seconds
Started Mar 07 12:37:10 PM PST 24
Finished Mar 07 12:37:12 PM PST 24
Peak memory 200964 kb
Host smart-5707b61e-7c02-4781-97c5-6451cb627989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58536064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.58536064
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1512200607
Short name T73
Test name
Test status
Simulation time 162162930012 ps
CPU time 126.43 seconds
Started Mar 07 12:35:58 PM PST 24
Finished Mar 07 12:38:05 PM PST 24
Peak memory 201260 kb
Host smart-b31aaafc-5b01-47fe-8a5f-29f33621619b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512200607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1512200607
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.926191937
Short name T135
Test name
Test status
Simulation time 366181463390 ps
CPU time 787.95 seconds
Started Mar 07 12:35:59 PM PST 24
Finished Mar 07 12:49:08 PM PST 24
Peak memory 201316 kb
Host smart-35e7946c-f613-46fd-bab9-12fef54ec21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926191937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.926191937
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.4230487142
Short name T296
Test name
Test status
Simulation time 490702763198 ps
CPU time 593.92 seconds
Started Mar 07 12:35:46 PM PST 24
Finished Mar 07 12:45:40 PM PST 24
Peak memory 201312 kb
Host smart-590330d7-e054-4f51-86ee-cfa8cb45ac8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230487142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.4230487142
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.539852272
Short name T431
Test name
Test status
Simulation time 166058959170 ps
CPU time 194.8 seconds
Started Mar 07 12:35:45 PM PST 24
Finished Mar 07 12:39:00 PM PST 24
Peak memory 201200 kb
Host smart-879d766f-58c8-43a2-8a95-ea758fec6043
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=539852272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.539852272
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1510541497
Short name T643
Test name
Test status
Simulation time 164275787256 ps
CPU time 123.04 seconds
Started Mar 07 12:35:46 PM PST 24
Finished Mar 07 12:37:49 PM PST 24
Peak memory 201328 kb
Host smart-0f493fca-41b3-409a-9c45-246a22eafd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510541497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1510541497
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2803145334
Short name T82
Test name
Test status
Simulation time 165126419194 ps
CPU time 211.17 seconds
Started Mar 07 12:35:45 PM PST 24
Finished Mar 07 12:39:17 PM PST 24
Peak memory 201316 kb
Host smart-d1e21ae8-b551-4a5c-b889-3db2f3a5bbef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803145334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2803145334
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1948425378
Short name T747
Test name
Test status
Simulation time 542110574333 ps
CPU time 1359.42 seconds
Started Mar 07 12:35:46 PM PST 24
Finished Mar 07 12:58:26 PM PST 24
Peak memory 201384 kb
Host smart-166b38f9-ede2-4ac5-9888-81f0bec5781d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948425378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1948425378
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1970541747
Short name T38
Test name
Test status
Simulation time 402068632250 ps
CPU time 851.63 seconds
Started Mar 07 12:35:58 PM PST 24
Finished Mar 07 12:50:10 PM PST 24
Peak memory 201240 kb
Host smart-36d04b18-96e7-4a67-985e-423c93270557
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970541747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1970541747
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2998496903
Short name T199
Test name
Test status
Simulation time 111297663997 ps
CPU time 511.94 seconds
Started Mar 07 12:37:09 PM PST 24
Finished Mar 07 12:45:42 PM PST 24
Peak memory 201568 kb
Host smart-6ae0a4ec-cc03-407f-b5fe-0ad1e4170137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998496903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2998496903
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.1381366689
Short name T80
Test name
Test status
Simulation time 38472263112 ps
CPU time 21.83 seconds
Started Mar 07 12:37:10 PM PST 24
Finished Mar 07 12:37:33 PM PST 24
Peak memory 201028 kb
Host smart-278d40ff-e229-42f1-83d4-5d6021772fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381366689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.1381366689
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3206596605
Short name T416
Test name
Test status
Simulation time 4321814709 ps
CPU time 10.1 seconds
Started Mar 07 12:35:58 PM PST 24
Finished Mar 07 12:36:09 PM PST 24
Peak memory 201196 kb
Host smart-7bf57201-312c-4424-8deb-f0844db89647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206596605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3206596605
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1936162760
Short name T550
Test name
Test status
Simulation time 5655761106 ps
CPU time 7.48 seconds
Started Mar 07 12:35:47 PM PST 24
Finished Mar 07 12:35:54 PM PST 24
Peak memory 201164 kb
Host smart-7cca8498-5abf-46c6-893b-d7129d6c323c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936162760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1936162760
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3534736487
Short name T6
Test name
Test status
Simulation time 28098461543 ps
CPU time 47.84 seconds
Started Mar 07 12:35:58 PM PST 24
Finished Mar 07 12:36:46 PM PST 24
Peak memory 210004 kb
Host smart-bd1f4198-f773-4a9e-ae2b-b2a9de1b0f9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534736487 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3534736487
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1917951611
Short name T614
Test name
Test status
Simulation time 420355884 ps
CPU time 1.62 seconds
Started Mar 07 12:36:19 PM PST 24
Finished Mar 07 12:36:21 PM PST 24
Peak memory 201120 kb
Host smart-db6a1044-ac99-4f37-b0a8-50feded14980
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917951611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1917951611
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1277454213
Short name T264
Test name
Test status
Simulation time 553104980853 ps
CPU time 306.7 seconds
Started Mar 07 12:36:06 PM PST 24
Finished Mar 07 12:41:17 PM PST 24
Peak memory 201304 kb
Host smart-fb1fc401-4dd8-4493-b0d5-b7f01ba545e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277454213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1277454213
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1570311405
Short name T253
Test name
Test status
Simulation time 164369198836 ps
CPU time 397.14 seconds
Started Mar 07 12:36:06 PM PST 24
Finished Mar 07 12:42:48 PM PST 24
Peak memory 201396 kb
Host smart-fc7aa339-8df9-4290-8c3a-fbe1dfc5249d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570311405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1570311405
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1052690455
Short name T593
Test name
Test status
Simulation time 167128655924 ps
CPU time 196.78 seconds
Started Mar 07 12:36:08 PM PST 24
Finished Mar 07 12:39:28 PM PST 24
Peak memory 201372 kb
Host smart-239b0876-bbfc-4ff5-9a50-ab0e9a80c191
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052690455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.1052690455
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3328139900
Short name T9
Test name
Test status
Simulation time 326316602746 ps
CPU time 341.78 seconds
Started Mar 07 12:35:58 PM PST 24
Finished Mar 07 12:41:40 PM PST 24
Peak memory 201336 kb
Host smart-39791f38-3969-4eb6-8dc7-b493b42d9934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328139900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3328139900
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2507644668
Short name T12
Test name
Test status
Simulation time 160890804848 ps
CPU time 78.77 seconds
Started Mar 07 12:37:10 PM PST 24
Finished Mar 07 12:38:30 PM PST 24
Peak memory 201156 kb
Host smart-e128cd4d-1b07-48a2-8279-d6f4651984d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507644668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2507644668
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3304656733
Short name T484
Test name
Test status
Simulation time 613929135579 ps
CPU time 728.59 seconds
Started Mar 07 12:36:08 PM PST 24
Finished Mar 07 12:48:20 PM PST 24
Peak memory 201336 kb
Host smart-d9185743-c9dc-44ca-9e73-4c2fc77ba9de
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304656733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3304656733
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1515312045
Short name T182
Test name
Test status
Simulation time 60247818643 ps
CPU time 247.33 seconds
Started Mar 07 12:36:06 PM PST 24
Finished Mar 07 12:40:18 PM PST 24
Peak memory 201772 kb
Host smart-5658e276-162f-4937-a952-2e983099add2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515312045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1515312045
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1299161493
Short name T459
Test name
Test status
Simulation time 23101888306 ps
CPU time 53.63 seconds
Started Mar 07 12:36:06 PM PST 24
Finished Mar 07 12:37:04 PM PST 24
Peak memory 201136 kb
Host smart-409655d3-3d72-43bf-9516-4807e4af2a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299161493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1299161493
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3788706289
Short name T485
Test name
Test status
Simulation time 2883723274 ps
CPU time 3.9 seconds
Started Mar 07 12:36:07 PM PST 24
Finished Mar 07 12:36:15 PM PST 24
Peak memory 201180 kb
Host smart-2f5d3bbd-df8e-4179-8072-36ccf7f20912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788706289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3788706289
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1579578957
Short name T535
Test name
Test status
Simulation time 6125872266 ps
CPU time 14.71 seconds
Started Mar 07 12:35:58 PM PST 24
Finished Mar 07 12:36:13 PM PST 24
Peak memory 201180 kb
Host smart-59be64a5-e5e5-4bd6-85f3-9f0c5b8c42dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579578957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1579578957
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3906889510
Short name T460
Test name
Test status
Simulation time 71859293019 ps
CPU time 52.23 seconds
Started Mar 07 12:36:08 PM PST 24
Finished Mar 07 12:37:03 PM PST 24
Peak memory 209604 kb
Host smart-c53f2a0a-4d34-4337-aa4a-12349c044d37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906889510 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3906889510
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.4072792733
Short name T606
Test name
Test status
Simulation time 372184520 ps
CPU time 0.84 seconds
Started Mar 07 12:36:19 PM PST 24
Finished Mar 07 12:36:20 PM PST 24
Peak memory 201180 kb
Host smart-be76c715-cb6b-4964-805e-2b515fc218d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072792733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.4072792733
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2870299550
Short name T584
Test name
Test status
Simulation time 201935024985 ps
CPU time 108.97 seconds
Started Mar 07 12:36:19 PM PST 24
Finished Mar 07 12:38:08 PM PST 24
Peak memory 201420 kb
Host smart-6ed653b3-f7b9-4557-9269-81d269a4ea3d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870299550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2870299550
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.432861285
Short name T655
Test name
Test status
Simulation time 493368312788 ps
CPU time 603.36 seconds
Started Mar 07 12:36:14 PM PST 24
Finished Mar 07 12:46:17 PM PST 24
Peak memory 201300 kb
Host smart-879ff8cc-803f-46ee-9046-001a4c769036
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=432861285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrup
t_fixed.432861285
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1060011589
Short name T313
Test name
Test status
Simulation time 335993071421 ps
CPU time 786.47 seconds
Started Mar 07 12:36:16 PM PST 24
Finished Mar 07 12:49:23 PM PST 24
Peak memory 201304 kb
Host smart-2030651c-29f8-43c8-9609-1edb6f2d7b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060011589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1060011589
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.4014762292
Short name T496
Test name
Test status
Simulation time 322811302464 ps
CPU time 166.72 seconds
Started Mar 07 12:36:15 PM PST 24
Finished Mar 07 12:39:02 PM PST 24
Peak memory 201372 kb
Host smart-bfb4fef3-5ffd-4c66-9380-7ab36ccfbfdc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014762292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.4014762292
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.472211653
Short name T636
Test name
Test status
Simulation time 167625197641 ps
CPU time 398.26 seconds
Started Mar 07 12:36:15 PM PST 24
Finished Mar 07 12:42:53 PM PST 24
Peak memory 201260 kb
Host smart-cb206fc3-b7d7-490a-9683-778511fee37c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472211653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.472211653
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3000101609
Short name T644
Test name
Test status
Simulation time 198346165827 ps
CPU time 458.24 seconds
Started Mar 07 12:36:15 PM PST 24
Finished Mar 07 12:43:54 PM PST 24
Peak memory 201312 kb
Host smart-b2f425f3-0f32-40d3-8bc6-21b9bce2c5ce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000101609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.3000101609
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3165515294
Short name T622
Test name
Test status
Simulation time 94125148016 ps
CPU time 401.87 seconds
Started Mar 07 12:36:17 PM PST 24
Finished Mar 07 12:42:59 PM PST 24
Peak memory 201696 kb
Host smart-3350c670-00bf-49dc-9423-7b7b58f40a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165515294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3165515294
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3950085817
Short name T724
Test name
Test status
Simulation time 45018947118 ps
CPU time 108.09 seconds
Started Mar 07 12:36:17 PM PST 24
Finished Mar 07 12:38:05 PM PST 24
Peak memory 201088 kb
Host smart-78fa0c78-c678-4bf7-b183-6af6160e6d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950085817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3950085817
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2222015143
Short name T679
Test name
Test status
Simulation time 3416106248 ps
CPU time 4.73 seconds
Started Mar 07 12:36:15 PM PST 24
Finished Mar 07 12:36:20 PM PST 24
Peak memory 201164 kb
Host smart-aafdc49e-7395-4a40-8cb1-4bd5992a5d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222015143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2222015143
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.1549749924
Short name T390
Test name
Test status
Simulation time 6032617285 ps
CPU time 4.21 seconds
Started Mar 07 12:36:15 PM PST 24
Finished Mar 07 12:36:20 PM PST 24
Peak memory 201176 kb
Host smart-2570701a-f2f7-4eca-9ca4-940d751ae35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549749924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.1549749924
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2828967116
Short name T600
Test name
Test status
Simulation time 7349900464 ps
CPU time 5.28 seconds
Started Mar 07 12:36:16 PM PST 24
Finished Mar 07 12:36:21 PM PST 24
Peak memory 201144 kb
Host smart-b1e057f9-19eb-45ae-98b1-fdf3c045b93c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828967116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2828967116
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.685730036
Short name T15
Test name
Test status
Simulation time 213665101851 ps
CPU time 220.86 seconds
Started Mar 07 12:36:19 PM PST 24
Finished Mar 07 12:40:00 PM PST 24
Peak memory 209784 kb
Host smart-e99b744f-eeb7-4bc9-8554-6e0494391e27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685730036 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.685730036
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3237985566
Short name T687
Test name
Test status
Simulation time 319942067 ps
CPU time 1.01 seconds
Started Mar 07 12:33:23 PM PST 24
Finished Mar 07 12:33:24 PM PST 24
Peak memory 201100 kb
Host smart-78da3001-96ed-4db5-8f58-ea0dc615d047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237985566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3237985566
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1396525457
Short name T467
Test name
Test status
Simulation time 173761020538 ps
CPU time 418.94 seconds
Started Mar 07 12:33:19 PM PST 24
Finished Mar 07 12:40:18 PM PST 24
Peak memory 201304 kb
Host smart-d094bcaa-62ea-42b0-ae57-4bb958ac1eaa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396525457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1396525457
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.958205540
Short name T213
Test name
Test status
Simulation time 331801671492 ps
CPU time 694.29 seconds
Started Mar 07 12:33:34 PM PST 24
Finished Mar 07 12:45:13 PM PST 24
Peak memory 201296 kb
Host smart-19c42038-af31-46fb-af46-94927f9db18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958205540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.958205540
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1865284718
Short name T304
Test name
Test status
Simulation time 324716582634 ps
CPU time 380.31 seconds
Started Mar 07 12:33:24 PM PST 24
Finished Mar 07 12:39:44 PM PST 24
Peak memory 201304 kb
Host smart-1e084cef-45d7-4330-b774-6b6c3f91ed95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865284718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1865284718
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2103553662
Short name T686
Test name
Test status
Simulation time 333716720757 ps
CPU time 103.93 seconds
Started Mar 07 12:33:16 PM PST 24
Finished Mar 07 12:35:00 PM PST 24
Peak memory 201344 kb
Host smart-176e5b41-7bc0-4569-836e-9c94b3bdb8bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103553662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2103553662
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.65518329
Short name T133
Test name
Test status
Simulation time 495555082932 ps
CPU time 90.39 seconds
Started Mar 07 12:33:25 PM PST 24
Finished Mar 07 12:34:56 PM PST 24
Peak memory 201340 kb
Host smart-7b6f1e5b-6004-426f-a5d8-6b438ca9aa97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65518329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.65518329
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3915488089
Short name T103
Test name
Test status
Simulation time 325836050116 ps
CPU time 794.81 seconds
Started Mar 07 12:33:25 PM PST 24
Finished Mar 07 12:46:41 PM PST 24
Peak memory 201280 kb
Host smart-8123f663-88f6-4d52-8b11-e4da6a516f1f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915488089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3915488089
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.769905774
Short name T130
Test name
Test status
Simulation time 525584024476 ps
CPU time 1276.45 seconds
Started Mar 07 12:33:33 PM PST 24
Finished Mar 07 12:54:50 PM PST 24
Peak memory 200820 kb
Host smart-7efd361e-23cf-4e06-b02e-731082bbaa07
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769905774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_w
akeup.769905774
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.4028046097
Short name T430
Test name
Test status
Simulation time 403046969057 ps
CPU time 220.84 seconds
Started Mar 07 12:33:34 PM PST 24
Finished Mar 07 12:37:15 PM PST 24
Peak memory 201352 kb
Host smart-ed87161e-3c64-4a06-9897-9b348fa8998c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028046097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.4028046097
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1929405433
Short name T184
Test name
Test status
Simulation time 103527422366 ps
CPU time 554.09 seconds
Started Mar 07 12:33:19 PM PST 24
Finished Mar 07 12:42:33 PM PST 24
Peak memory 201760 kb
Host smart-0302a675-c955-4ca4-bc4b-694d9c0e0d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929405433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1929405433
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2350360937
Short name T381
Test name
Test status
Simulation time 29884462200 ps
CPU time 37.83 seconds
Started Mar 07 12:33:25 PM PST 24
Finished Mar 07 12:34:03 PM PST 24
Peak memory 201144 kb
Host smart-579bd869-791b-4990-83fe-71da7bdf4da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350360937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2350360937
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2903365322
Short name T626
Test name
Test status
Simulation time 3818912912 ps
CPU time 2.4 seconds
Started Mar 07 12:33:13 PM PST 24
Finished Mar 07 12:33:16 PM PST 24
Peak memory 201288 kb
Host smart-dae4f284-bb09-489d-8eb9-d41bbdbb749c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903365322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2903365322
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1352126753
Short name T497
Test name
Test status
Simulation time 5695604625 ps
CPU time 4.12 seconds
Started Mar 07 12:33:20 PM PST 24
Finished Mar 07 12:33:25 PM PST 24
Peak memory 201152 kb
Host smart-c25ad076-e973-464d-b0d0-fe87592dd5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352126753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1352126753
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2956306008
Short name T29
Test name
Test status
Simulation time 333320737326 ps
CPU time 394.19 seconds
Started Mar 07 12:33:27 PM PST 24
Finished Mar 07 12:40:01 PM PST 24
Peak memory 201292 kb
Host smart-adbcab86-fe31-43af-9d09-747faf4ba2d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956306008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2956306008
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3862153872
Short name T658
Test name
Test status
Simulation time 404677751 ps
CPU time 1.03 seconds
Started Mar 07 12:33:38 PM PST 24
Finished Mar 07 12:33:40 PM PST 24
Peak memory 201120 kb
Host smart-c61b7be5-3961-448e-9054-97d1ca467a6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862153872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3862153872
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1659313638
Short name T285
Test name
Test status
Simulation time 191140166827 ps
CPU time 124.81 seconds
Started Mar 07 12:33:21 PM PST 24
Finished Mar 07 12:35:26 PM PST 24
Peak memory 201300 kb
Host smart-ef6f5f2e-b318-43f4-ab45-38442e752e9a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659313638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1659313638
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.879805087
Short name T772
Test name
Test status
Simulation time 536835851462 ps
CPU time 107.35 seconds
Started Mar 07 12:33:19 PM PST 24
Finished Mar 07 12:35:06 PM PST 24
Peak memory 201316 kb
Host smart-f9be1a9f-9600-4860-87e5-eed3f12499b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879805087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.879805087
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1786804989
Short name T597
Test name
Test status
Simulation time 330830085900 ps
CPU time 108.46 seconds
Started Mar 07 12:33:24 PM PST 24
Finished Mar 07 12:35:13 PM PST 24
Peak memory 201260 kb
Host smart-250e31d4-88ec-4890-90e0-f2c023004c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786804989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1786804989
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.680587265
Short name T419
Test name
Test status
Simulation time 327470181339 ps
CPU time 749.8 seconds
Started Mar 07 12:33:19 PM PST 24
Finished Mar 07 12:45:49 PM PST 24
Peak memory 201320 kb
Host smart-f7e2f926-e1c2-4b9f-9a74-83ad58e97325
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=680587265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.680587265
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1406184093
Short name T71
Test name
Test status
Simulation time 162484313856 ps
CPU time 400.01 seconds
Started Mar 07 12:33:23 PM PST 24
Finished Mar 07 12:40:03 PM PST 24
Peak memory 201388 kb
Host smart-97f19eea-bb59-4ff8-972c-18553588dd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406184093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1406184093
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2300820647
Short name T602
Test name
Test status
Simulation time 163207545819 ps
CPU time 404.74 seconds
Started Mar 07 12:33:26 PM PST 24
Finished Mar 07 12:40:11 PM PST 24
Peak memory 201248 kb
Host smart-eff64012-fea9-47c2-9e4b-8fd0bd154cf2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300820647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.2300820647
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1940915221
Short name T158
Test name
Test status
Simulation time 367575609464 ps
CPU time 911.26 seconds
Started Mar 07 12:33:20 PM PST 24
Finished Mar 07 12:48:32 PM PST 24
Peak memory 201336 kb
Host smart-072b17f9-ae38-4da5-8f67-5b579eb2ba24
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940915221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1940915221
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3642808974
Short name T620
Test name
Test status
Simulation time 398940104693 ps
CPU time 145.14 seconds
Started Mar 07 12:33:19 PM PST 24
Finished Mar 07 12:35:44 PM PST 24
Peak memory 201388 kb
Host smart-b96f4a17-0296-426c-8ead-3600143b4527
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642808974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3642808974
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3903629811
Short name T661
Test name
Test status
Simulation time 124240656547 ps
CPU time 626.78 seconds
Started Mar 07 12:33:34 PM PST 24
Finished Mar 07 12:44:01 PM PST 24
Peak memory 201644 kb
Host smart-7dc76d67-1e75-46f4-81d2-9bee83214a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903629811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3903629811
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.788831322
Short name T341
Test name
Test status
Simulation time 27862076056 ps
CPU time 35.83 seconds
Started Mar 07 12:33:35 PM PST 24
Finished Mar 07 12:34:11 PM PST 24
Peak memory 201044 kb
Host smart-bea9df66-84ef-4b1e-a13d-b71b9202f9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788831322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.788831322
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.60675010
Short name T397
Test name
Test status
Simulation time 4659780593 ps
CPU time 12.2 seconds
Started Mar 07 12:33:35 PM PST 24
Finished Mar 07 12:33:49 PM PST 24
Peak memory 201140 kb
Host smart-a05ac9f8-5a1a-491d-b011-a626814451c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60675010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.60675010
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2455518837
Short name T737
Test name
Test status
Simulation time 5885514267 ps
CPU time 4.14 seconds
Started Mar 07 12:33:25 PM PST 24
Finished Mar 07 12:33:30 PM PST 24
Peak memory 201156 kb
Host smart-dd7b7bc3-7d64-4868-88df-99d201356aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455518837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2455518837
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.2734744549
Short name T704
Test name
Test status
Simulation time 203266093024 ps
CPU time 227.01 seconds
Started Mar 07 12:33:33 PM PST 24
Finished Mar 07 12:37:20 PM PST 24
Peak memory 201404 kb
Host smart-b9bd5231-9b80-484c-9051-441938685590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734744549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
2734744549
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.108410570
Short name T428
Test name
Test status
Simulation time 356834216036 ps
CPU time 624.26 seconds
Started Mar 07 12:33:33 PM PST 24
Finished Mar 07 12:43:57 PM PST 24
Peak memory 210100 kb
Host smart-afcebebd-0f74-4e2d-b50a-90ffb1334ddd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108410570 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.108410570
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.356978909
Short name T767
Test name
Test status
Simulation time 432994331 ps
CPU time 0.85 seconds
Started Mar 07 12:33:31 PM PST 24
Finished Mar 07 12:33:32 PM PST 24
Peak memory 201096 kb
Host smart-879764db-e3a6-4b5e-a24b-13e1386837c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356978909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.356978909
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3373943181
Short name T94
Test name
Test status
Simulation time 343071040118 ps
CPU time 682.2 seconds
Started Mar 07 12:33:37 PM PST 24
Finished Mar 07 12:44:59 PM PST 24
Peak memory 201328 kb
Host smart-fa34600b-b2c8-4359-9f0a-2599eafe5038
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373943181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3373943181
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3013229954
Short name T789
Test name
Test status
Simulation time 207899821068 ps
CPU time 158.04 seconds
Started Mar 07 12:33:32 PM PST 24
Finished Mar 07 12:36:10 PM PST 24
Peak memory 201288 kb
Host smart-61dc7b89-9af2-42e2-8246-84bcc4699ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013229954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3013229954
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.2480489343
Short name T231
Test name
Test status
Simulation time 167736908073 ps
CPU time 206.18 seconds
Started Mar 07 12:33:40 PM PST 24
Finished Mar 07 12:37:06 PM PST 24
Peak memory 201520 kb
Host smart-56c96193-017e-4cb1-bf64-4d9cf980afc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480489343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.2480489343
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1638799154
Short name T647
Test name
Test status
Simulation time 324247302740 ps
CPU time 193.6 seconds
Started Mar 07 12:33:51 PM PST 24
Finished Mar 07 12:37:05 PM PST 24
Peak memory 201388 kb
Host smart-293b30a9-ebf3-41cc-9b01-445fdcad9a00
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638799154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.1638799154
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.536864501
Short name T581
Test name
Test status
Simulation time 159189038232 ps
CPU time 52.02 seconds
Started Mar 07 12:33:22 PM PST 24
Finished Mar 07 12:34:14 PM PST 24
Peak memory 201324 kb
Host smart-00e560bc-aebc-4ac3-aecc-ac8a9ca49c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536864501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.536864501
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3627005183
Short name T417
Test name
Test status
Simulation time 332272486179 ps
CPU time 87.38 seconds
Started Mar 07 12:33:58 PM PST 24
Finished Mar 07 12:35:26 PM PST 24
Peak memory 201288 kb
Host smart-9bc52f1c-4786-43dd-854a-1e5a4bb86530
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627005183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3627005183
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2827221474
Short name T415
Test name
Test status
Simulation time 234098432722 ps
CPU time 143.21 seconds
Started Mar 07 12:33:37 PM PST 24
Finished Mar 07 12:36:00 PM PST 24
Peak memory 201320 kb
Host smart-76f0a772-13d4-4b91-8b50-b730ff1f3d42
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827221474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2827221474
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.2203096489
Short name T394
Test name
Test status
Simulation time 192736026306 ps
CPU time 245.44 seconds
Started Mar 07 12:33:41 PM PST 24
Finished Mar 07 12:37:46 PM PST 24
Peak memory 201368 kb
Host smart-21b4d786-9f3c-4a85-81fd-4c483100de75
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203096489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.2203096489
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.2971726426
Short name T93
Test name
Test status
Simulation time 116710495383 ps
CPU time 599.44 seconds
Started Mar 07 12:33:41 PM PST 24
Finished Mar 07 12:43:41 PM PST 24
Peak memory 201744 kb
Host smart-91f6c649-4f94-446f-8760-d235dcf4d04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971726426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.2971726426
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3837731778
Short name T523
Test name
Test status
Simulation time 26854865038 ps
CPU time 17.96 seconds
Started Mar 07 12:33:23 PM PST 24
Finished Mar 07 12:33:41 PM PST 24
Peak memory 201008 kb
Host smart-442c4889-7076-4228-9cc1-03c9d7750bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837731778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3837731778
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.913465719
Short name T408
Test name
Test status
Simulation time 3276519674 ps
CPU time 2.72 seconds
Started Mar 07 12:33:37 PM PST 24
Finished Mar 07 12:33:40 PM PST 24
Peak memory 201136 kb
Host smart-d81495a4-ef6b-4210-98ff-be21a3401ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913465719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.913465719
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2001598460
Short name T638
Test name
Test status
Simulation time 5735233418 ps
CPU time 3.9 seconds
Started Mar 07 12:33:43 PM PST 24
Finished Mar 07 12:33:47 PM PST 24
Peak memory 201148 kb
Host smart-c674310a-3e2a-4b44-88f2-13caa9823425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001598460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2001598460
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.4212820651
Short name T30
Test name
Test status
Simulation time 280105331778 ps
CPU time 876.67 seconds
Started Mar 07 12:33:45 PM PST 24
Finished Mar 07 12:48:22 PM PST 24
Peak memory 201672 kb
Host smart-0de7de9b-4e3c-47ed-84df-ead600df4d67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212820651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
4212820651
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2612639894
Short name T480
Test name
Test status
Simulation time 510811654 ps
CPU time 1.93 seconds
Started Mar 07 12:33:48 PM PST 24
Finished Mar 07 12:33:50 PM PST 24
Peak memory 201100 kb
Host smart-8be7afa9-8507-4e5f-acec-c7a959c28e99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612639894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2612639894
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2628992236
Short name T590
Test name
Test status
Simulation time 487758745119 ps
CPU time 252.93 seconds
Started Mar 07 12:33:23 PM PST 24
Finished Mar 07 12:37:36 PM PST 24
Peak memory 201112 kb
Host smart-36f1c787-6275-40ba-85f3-e31624b1d328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628992236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2628992236
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1511657957
Short name T437
Test name
Test status
Simulation time 162845816431 ps
CPU time 193.77 seconds
Started Mar 07 12:33:46 PM PST 24
Finished Mar 07 12:37:00 PM PST 24
Peak memory 201360 kb
Host smart-4a28be0e-07f1-45f4-b0c5-221fd926f21d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511657957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.1511657957
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2627475865
Short name T175
Test name
Test status
Simulation time 324091814236 ps
CPU time 207.24 seconds
Started Mar 07 12:33:48 PM PST 24
Finished Mar 07 12:37:15 PM PST 24
Peak memory 201360 kb
Host smart-75a08241-4e74-46a2-bf91-e1c4d4451bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627475865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2627475865
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1283752477
Short name T677
Test name
Test status
Simulation time 494316085728 ps
CPU time 486.1 seconds
Started Mar 07 12:33:36 PM PST 24
Finished Mar 07 12:41:43 PM PST 24
Peak memory 201276 kb
Host smart-0503f317-a854-46ed-b024-4e4c9f52a398
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283752477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.1283752477
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2628290774
Short name T741
Test name
Test status
Simulation time 189886533825 ps
CPU time 122.11 seconds
Started Mar 07 12:33:30 PM PST 24
Finished Mar 07 12:35:33 PM PST 24
Peak memory 201188 kb
Host smart-f8994e98-3a00-46fb-9bd4-614f9e54062c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628290774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2628290774
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.2526164226
Short name T562
Test name
Test status
Simulation time 589947655130 ps
CPU time 379.01 seconds
Started Mar 07 12:33:56 PM PST 24
Finished Mar 07 12:40:15 PM PST 24
Peak memory 201284 kb
Host smart-c7ed905d-27fb-4906-ac1a-6a3cff5ca8e7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526164226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.2526164226
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.3881365670
Short name T725
Test name
Test status
Simulation time 99241917616 ps
CPU time 414.26 seconds
Started Mar 07 12:33:24 PM PST 24
Finished Mar 07 12:40:18 PM PST 24
Peak memory 201704 kb
Host smart-6bb1a551-514a-4433-8136-6edefb071371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881365670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.3881365670
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3379741287
Short name T711
Test name
Test status
Simulation time 33670199529 ps
CPU time 22.3 seconds
Started Mar 07 12:33:22 PM PST 24
Finished Mar 07 12:33:45 PM PST 24
Peak memory 201144 kb
Host smart-2b1b356d-55af-4d32-bfad-8acd1ae78d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379741287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3379741287
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.1068659669
Short name T713
Test name
Test status
Simulation time 4659133288 ps
CPU time 3.52 seconds
Started Mar 07 12:33:31 PM PST 24
Finished Mar 07 12:33:34 PM PST 24
Peak memory 201184 kb
Host smart-98b636c7-c63d-42d4-8c4f-5df121103147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068659669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1068659669
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.797418269
Short name T442
Test name
Test status
Simulation time 5743348424 ps
CPU time 4.27 seconds
Started Mar 07 12:33:43 PM PST 24
Finished Mar 07 12:33:47 PM PST 24
Peak memory 201148 kb
Host smart-ef42a5c1-cd0e-4b7c-9b33-0730da36c617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797418269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.797418269
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.518658918
Short name T193
Test name
Test status
Simulation time 240219913622 ps
CPU time 798.34 seconds
Started Mar 07 12:33:38 PM PST 24
Finished Mar 07 12:46:57 PM PST 24
Peak memory 210052 kb
Host smart-ddccb6b0-ac9c-472a-a2ec-27d11a2aa8ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518658918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.518658918
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2753709187
Short name T36
Test name
Test status
Simulation time 228785011286 ps
CPU time 225.09 seconds
Started Mar 07 12:33:44 PM PST 24
Finished Mar 07 12:37:29 PM PST 24
Peak memory 216448 kb
Host smart-b3199b06-277f-42f0-b904-95e30e9a1ee4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753709187 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2753709187
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1566566627
Short name T348
Test name
Test status
Simulation time 355851198 ps
CPU time 0.99 seconds
Started Mar 07 12:33:47 PM PST 24
Finished Mar 07 12:33:48 PM PST 24
Peak memory 201120 kb
Host smart-bace45ad-e3bc-4b1f-b320-7e5d943b8183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566566627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1566566627
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3221706713
Short name T260
Test name
Test status
Simulation time 184624830994 ps
CPU time 27.68 seconds
Started Mar 07 12:33:40 PM PST 24
Finished Mar 07 12:34:08 PM PST 24
Peak memory 201412 kb
Host smart-033769b4-5c33-4661-ad5c-3de5375b61b7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221706713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3221706713
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.332262191
Short name T247
Test name
Test status
Simulation time 505870801528 ps
CPU time 1129.44 seconds
Started Mar 07 12:33:50 PM PST 24
Finished Mar 07 12:52:40 PM PST 24
Peak memory 201328 kb
Host smart-5a85fe11-75b5-469d-a381-5839462f6c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332262191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.332262191
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1153515931
Short name T673
Test name
Test status
Simulation time 162090281985 ps
CPU time 93.58 seconds
Started Mar 07 12:33:38 PM PST 24
Finished Mar 07 12:35:12 PM PST 24
Peak memory 201272 kb
Host smart-173212f0-e6e8-46cd-b193-822c32323609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153515931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1153515931
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.34189911
Short name T585
Test name
Test status
Simulation time 326788600670 ps
CPU time 419.02 seconds
Started Mar 07 12:33:50 PM PST 24
Finished Mar 07 12:40:49 PM PST 24
Peak memory 201356 kb
Host smart-1fa4727a-300f-45d4-b184-6d64c6255c0f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=34189911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt_
fixed.34189911
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.1659265799
Short name T323
Test name
Test status
Simulation time 333272904704 ps
CPU time 839.62 seconds
Started Mar 07 12:33:34 PM PST 24
Finished Mar 07 12:47:34 PM PST 24
Peak memory 201244 kb
Host smart-5c2053da-d22b-4050-ae22-60ea3f148b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659265799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1659265799
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2640691829
Short name T619
Test name
Test status
Simulation time 169733144244 ps
CPU time 46.63 seconds
Started Mar 07 12:33:47 PM PST 24
Finished Mar 07 12:34:33 PM PST 24
Peak memory 201308 kb
Host smart-7abf89bf-2c2c-41b8-af1a-05b75002d73d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640691829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2640691829
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1151127309
Short name T292
Test name
Test status
Simulation time 570908811093 ps
CPU time 324.1 seconds
Started Mar 07 12:33:35 PM PST 24
Finished Mar 07 12:39:00 PM PST 24
Peak memory 201368 kb
Host smart-9d790c94-a3c7-453c-a774-8f1522fdf03c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151127309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1151127309
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.27246160
Short name T589
Test name
Test status
Simulation time 391790267349 ps
CPU time 141.49 seconds
Started Mar 07 12:33:32 PM PST 24
Finished Mar 07 12:35:54 PM PST 24
Peak memory 201380 kb
Host smart-d22d2ff0-9840-4797-8d3e-fecdcac287ec
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27246160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.ad
c_ctrl_filters_wakeup_fixed.27246160
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2552317132
Short name T43
Test name
Test status
Simulation time 108582595806 ps
CPU time 472.39 seconds
Started Mar 07 12:33:23 PM PST 24
Finished Mar 07 12:41:15 PM PST 24
Peak memory 201768 kb
Host smart-fbf6fbb4-37fe-42c6-ad7c-6e4140bb2f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552317132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2552317132
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.748297999
Short name T596
Test name
Test status
Simulation time 34159538823 ps
CPU time 25.41 seconds
Started Mar 07 12:33:43 PM PST 24
Finished Mar 07 12:34:09 PM PST 24
Peak memory 201152 kb
Host smart-6d3b3d49-4b62-415c-93f7-78ff53e03698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748297999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.748297999
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1247164666
Short name T435
Test name
Test status
Simulation time 5158450187 ps
CPU time 10.79 seconds
Started Mar 07 12:33:26 PM PST 24
Finished Mar 07 12:33:37 PM PST 24
Peak memory 201192 kb
Host smart-02d14772-e545-4745-8823-bb9b6536d9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247164666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1247164666
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.1727329047
Short name T388
Test name
Test status
Simulation time 5855839596 ps
CPU time 3.97 seconds
Started Mar 07 12:33:46 PM PST 24
Finished Mar 07 12:33:50 PM PST 24
Peak memory 201200 kb
Host smart-55babb8a-fb3a-4eb7-969b-1b4772946823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727329047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1727329047
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1079268177
Short name T259
Test name
Test status
Simulation time 213822474366 ps
CPU time 241.15 seconds
Started Mar 07 12:33:32 PM PST 24
Finished Mar 07 12:37:34 PM PST 24
Peak memory 201332 kb
Host smart-abec0454-f277-4c6b-9b9c-18461badcaae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079268177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1079268177
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2133768927
Short name T277
Test name
Test status
Simulation time 130617715717 ps
CPU time 196.73 seconds
Started Mar 07 12:33:25 PM PST 24
Finished Mar 07 12:36:43 PM PST 24
Peak memory 210112 kb
Host smart-0c2ee786-0955-4996-b540-278cdbaba892
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133768927 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2133768927
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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