Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1197448	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1169142

1

T1

1806

T2

1472

T4

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2071685	1			T1	3308		T2	2555		T4	1
values[0x0]	146733	1			T1	188		T2	169		T4	9
values[0x1]	148172	1			T1	212		T2	141		T4	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	958696	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1407894

1

T1

2199

T2

1758

T4

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7121	1			T1	13		T2	8		T3	14
valid_sources[0x01]	11628	1			T1	11		T2	13		T3	10
valid_sources[0x02]	19848	1			T1	21		T2	5		T3	11
valid_sources[0x03]	7162	1			T1	44		T2	7		T3	9
valid_sources[0x04]	7991	1			T1	10		T2	9		T3	17
valid_sources[0x05]	11678	1			T1	11		T2	3		T3	15
valid_sources[0x06]	7070	1			T1	8		T2	8		T3	14
valid_sources[0x07]	10087	1			T1	7		T2	9		T3	12
valid_sources[0x08]	8133	1			T1	31		T2	15		T3	5
valid_sources[0x09]	7307	1			T1	16		T2	7		T3	12
valid_sources[0x0a]	11605	1			T1	13		T2	13		T3	11
valid_sources[0x0b]	7255	1			T1	39		T2	12		T3	10
valid_sources[0x0c]	7330	1			T1	6		T2	5		T4	1
valid_sources[0x0d]	11475	1			T1	19		T2	7		T3	13
valid_sources[0x0e]	9752	1			T1	16		T2	10		T3	8
valid_sources[0x0f]	9537	1			T1	17		T2	6		T3	15
valid_sources[0x10]	10523	1			T1	9		T2	4		T3	12
valid_sources[0x11]	7691	1			T1	12		T2	4		T3	15
valid_sources[0x12]	7807	1			T1	16		T2	11		T3	12
valid_sources[0x13]	7625	1			T1	10		T2	4		T3	11
valid_sources[0x14]	7039	1			T1	9		T2	22		T3	19
valid_sources[0x15]	11647	1			T1	12		T2	17		T3	8
valid_sources[0x16]	7259	1			T1	12		T2	8		T3	16
valid_sources[0x17]	12419	1			T1	9		T2	11		T3	12
valid_sources[0x18]	11216	1			T1	9		T2	24		T3	6
valid_sources[0x19]	13491	1			T1	11		T2	8		T4	2
valid_sources[0x1a]	7331	1			T1	22		T2	8		T3	6
valid_sources[0x1b]	7533	1			T1	28		T2	12		T3	15
valid_sources[0x1c]	7587	1			T1	20		T2	2		T3	14
valid_sources[0x1d]	8996	1			T1	30		T2	11		T3	4
valid_sources[0x1e]	7215	1			T1	17		T2	24		T4	2
valid_sources[0x1f]	11455	1			T1	13		T2	19		T3	10
valid_sources[0x20]	7564	1			T1	14		T2	33		T3	8
valid_sources[0x21]	7157	1			T1	15		T2	6		T3	12
valid_sources[0x22]	11132	1			T1	14		T2	10		T3	14
valid_sources[0x23]	7553	1			T1	7		T2	17		T3	13
valid_sources[0x24]	10049	1			T1	10		T2	13		T3	6
valid_sources[0x25]	14589	1			T1	20		T2	1		T4	2
valid_sources[0x26]	8632	1			T1	8		T2	14		T3	13
valid_sources[0x27]	7305	1			T1	11		T2	4		T3	15
valid_sources[0x28]	7126	1			T1	23		T2	5		T3	8
valid_sources[0x29]	9114	1			T1	11		T2	23		T3	9
valid_sources[0x2a]	7365	1			T1	13		T2	8		T3	10
valid_sources[0x2b]	11664	1			T1	9		T2	7		T3	8
valid_sources[0x2c]	13835	1			T1	17		T2	7		T3	8
valid_sources[0x2d]	11124	1			T1	12		T2	21		T3	10
valid_sources[0x2e]	6987	1			T1	11		T2	9		T3	8
valid_sources[0x2f]	7875	1			T1	25		T2	8		T3	7
valid_sources[0x30]	8200	1			T1	21		T2	7		T3	11
valid_sources[0x31]	7420	1			T1	9		T2	25		T3	2
valid_sources[0x32]	7467	1			T1	14		T3	12		T6	11
valid_sources[0x33]	7265	1			T1	19		T2	9		T3	11
valid_sources[0x34]	8545	1			T1	12		T2	7		T3	14
valid_sources[0x35]	6949	1			T1	28		T2	14		T3	10
valid_sources[0x36]	7227	1			T1	29		T2	13		T3	8
valid_sources[0x37]	6873	1			T1	22		T2	4		T3	9
valid_sources[0x38]	7309	1			T1	15		T2	10		T3	11
valid_sources[0x39]	11515	1			T1	13		T2	10		T3	11
valid_sources[0x3a]	7407	1			T1	23		T2	14		T3	14
valid_sources[0x3b]	7224	1			T1	17		T2	22		T3	3
valid_sources[0x3c]	7396	1			T1	9		T2	8		T3	5
valid_sources[0x3d]	7475	1			T1	9		T2	17		T3	14
valid_sources[0x3e]	11587	1			T1	23		T2	15		T3	12
valid_sources[0x3f]	7386	1			T1	31		T2	16		T3	17
valid_sources[0x40]	11621	1			T1	15		T2	13		T3	10
valid_sources[0x41]	11580	1			T1	11		T2	6		T3	8
valid_sources[0x42]	11467	1			T1	16		T2	9		T3	10
valid_sources[0x43]	7186	1			T1	6		T2	4		T3	9
valid_sources[0x44]	9240	1			T1	12		T2	6		T3	11
valid_sources[0x45]	11868	1			T1	7		T2	10		T3	9
valid_sources[0x46]	8907	1			T1	20		T2	5		T3	7
valid_sources[0x47]	7902	1			T1	9		T2	11		T3	6
valid_sources[0x48]	11530	1			T1	8		T2	9		T3	8
valid_sources[0x49]	9911	1			T1	14		T2	6		T3	11
valid_sources[0x4a]	7461	1			T1	5		T2	15		T3	20
valid_sources[0x4b]	7058	1			T1	23		T2	7		T3	13
valid_sources[0x4c]	7453	1			T1	13		T2	5		T4	1
valid_sources[0x4d]	7018	1			T1	13		T2	11		T3	9
valid_sources[0x4e]	7601	1			T1	14		T2	8		T3	15
valid_sources[0x4f]	12480	1			T1	13		T2	5		T3	5
valid_sources[0x50]	7387	1			T1	7		T2	8		T3	6
valid_sources[0x51]	9631	1			T1	12		T2	16		T3	22
valid_sources[0x52]	7263	1			T1	19		T2	11		T3	15
valid_sources[0x53]	6832	1			T1	9		T2	10		T4	1
valid_sources[0x54]	11441	1			T1	8		T2	6		T3	11
valid_sources[0x55]	12028	1			T1	9		T2	14		T3	8
valid_sources[0x56]	8416	1			T1	14		T2	23		T3	8
valid_sources[0x57]	7700	1			T1	9		T2	17		T3	11
valid_sources[0x58]	14040	1			T1	8		T2	3		T3	10
valid_sources[0x59]	8070	1			T1	19		T2	19		T4	1
valid_sources[0x5a]	9320	1			T1	7		T2	7		T3	14
valid_sources[0x5b]	7259	1			T1	4		T2	10		T3	10
valid_sources[0x5c]	7615	1			T1	25		T2	5		T3	9
valid_sources[0x5d]	7456	1			T1	22		T2	4		T4	1
valid_sources[0x5e]	7209	1			T1	10		T2	3		T3	10
valid_sources[0x5f]	6883	1			T1	16		T2	9		T3	17
valid_sources[0x60]	7754	1			T1	13		T2	14		T3	11
valid_sources[0x61]	7522	1			T1	13		T2	9		T3	13
valid_sources[0x62]	7891	1			T1	3		T2	17		T3	11
valid_sources[0x63]	22138	1			T1	16		T2	5		T3	21
valid_sources[0x64]	12670	1			T1	16		T2	9		T3	13
valid_sources[0x65]	6769	1			T1	12		T2	8		T3	11
valid_sources[0x66]	11398	1			T1	11		T2	8		T3	6
valid_sources[0x67]	7257	1			T1	18		T2	6		T3	8
valid_sources[0x68]	7945	1			T1	11		T2	13		T3	7
valid_sources[0x69]	7498	1			T1	17		T2	18		T3	11
valid_sources[0x6a]	12730	1			T1	13		T2	1		T3	8
valid_sources[0x6b]	16962	1			T1	21		T2	20		T3	8
valid_sources[0x6c]	10012	1			T1	15		T2	6		T3	6
valid_sources[0x6d]	7153	1			T1	9		T2	11		T3	18
valid_sources[0x6e]	11764	1			T1	7		T2	27		T3	11
valid_sources[0x6f]	13002	1			T1	13		T2	15		T3	11
valid_sources[0x70]	7984	1			T1	8		T2	9		T3	11
valid_sources[0x71]	6784	1			T1	16		T2	8		T3	11
valid_sources[0x72]	8513	1			T1	7		T2	10		T3	7
valid_sources[0x73]	7398	1			T1	22		T2	7		T3	11
valid_sources[0x74]	11637	1			T1	15		T2	15		T3	6
valid_sources[0x75]	7005	1			T1	13		T2	16		T3	8
valid_sources[0x76]	7085	1			T1	17		T2	16		T4	1
valid_sources[0x77]	7620	1			T1	10		T2	30		T3	15
valid_sources[0x78]	11123	1			T1	14		T2	6		T3	17
valid_sources[0x79]	11428	1			T1	13		T2	7		T3	7
valid_sources[0x7a]	7138	1			T1	19		T2	7		T3	11
valid_sources[0x7b]	7435	1			T1	11		T2	3		T3	12
valid_sources[0x7c]	7405	1			T1	7		T2	8		T3	13
valid_sources[0x7d]	6899	1			T1	19		T2	9		T3	15
valid_sources[0x7e]	10179	1			T1	8		T2	8		T3	7
valid_sources[0x7f]	14308	1			T1	14		T2	19		T3	10
valid_sources[0x80]	7093	1			T1	15		T2	10		T3	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1030975

1

T1

1630

T2

1298

T3

1232

values[0x0]

all_enables

biggest_size

80019

1

T1

105

T2

105

T4

5

values[0x1]

all_enables

biggest_size

58148

1

T1

71

T2

69

T4

2